Lines Matching refs:surf
291 struct radeon_surf *surf, bool is_stencil,
330 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
332 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
336 AddrSurfInfoIn->basePitch *= surf->blk_w;
346 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
347 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
367 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
369 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
371 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
393 surf_level->dcc_offset = surf->dcc_size;
394 surf->num_dcc_levels = level + 1;
395 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
396 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
437 surf->htile_size = AddrHtileOut->htileBytes;
438 surf->htile_slice_size = AddrHtileOut->sliceSize;
439 surf->htile_alignment = AddrHtileOut->baseAlign;
450 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
453 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
456 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
458 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
461 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
465 tileb = 8 * 8 * surf->bpe;
466 tileb = MIN2(surf->u.legacy.tile_split, tileb);
476 const struct radeon_surf *surf)
479 unsigned bpe = surf->bpe;
481 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
482 surf->flags & RADEON_SURF_SCANOUT &&
484 surf->blk_w <= 2 && surf->blk_h == 1) {
486 if (surf->blk_w == 2 && surf->blk_h == 1)
510 struct radeon_surf *surf)
512 surf->surf_alignment = csio->baseAlign;
513 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
514 gfx6_set_micro_tile_mode(surf, info);
518 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
519 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
520 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
521 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
522 surf->u.legacy.num_banks = csio->pTileInfo->banks;
523 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
525 surf->u.legacy.macro_tile_index = 0;
532 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
533 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
534 !get_display_flag(config, surf)) {
553 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
554 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
561 struct radeon_surf *surf)
567 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
596 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8);
597 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8);
603 surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128);
604 if (surf->u.legacy.cmask_slice_tile_max)
605 surf->u.legacy.cmask_slice_tile_max -= 1;
615 surf->cmask_alignment = MAX2(256, base_align);
616 surf->cmask_size = align(slice_bytes, base_align) * num_layers;
620 * Fill in the tiling information in \p surf based on the given surface config.
622 * The following fields of \p surf must be initialized by the caller:
629 struct radeon_surf *surf)
651 compressed = surf->blk_w == 4 && surf->blk_h == 4;
658 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
681 switch (surf->bpe) {
693 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
700 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
706 if (surf->flags & RADEON_SURF_SCANOUT)
708 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
713 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
714 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
716 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
718 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
726 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
736 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
737 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
742 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
743 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
778 surf->u.legacy.bankw && surf->u.legacy.bankh &&
779 surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
782 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
783 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
784 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
785 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
786 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
787 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
799 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
804 if (surf->bpe == 2)
809 if (surf->bpe == 1)
811 else if (surf->bpe == 2)
813 else if (surf->bpe == 4)
826 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
830 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
831 surf->num_dcc_levels = 0;
832 surf->surf_size = 0;
833 surf->dcc_size = 0;
834 surf->dcc_alignment = 1;
835 surf->htile_size = 0;
836 surf->htile_slice_size = 0;
837 surf->htile_alignment = 1;
839 const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
840 !(surf->flags & RADEON_SURF_ZBUFFER);
845 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed,
864 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
875 &AddrSurfInfoOut, surf);
882 if (surf->flags & RADEON_SURF_SBUFFER) {
889 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
892 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
901 if (surf->u.legacy.stencil_level[level].nblk_x !=
902 surf->u.legacy.level[level].nblk_x)
903 surf->u.legacy.stencil_adjusted = true;
905 surf->u.legacy.level[level].nblk_x =
906 surf->u.legacy.stencil_level[level].nblk_x;
912 &AddrSurfInfoOut, surf);
919 surf->u.legacy.stencil_tile_split =
948 surf->fmask_size = fout.fmaskBytes;
949 surf->fmask_alignment = fout.baseAlign;
950 surf->fmask_tile_swizzle = 0;
952 surf->u.legacy.fmask.slice_tile_max =
954 if (surf->u.legacy.fmask.slice_tile_max)
955 surf->u.legacy.fmask.slice_tile_max -= 1;
957 surf->u.legacy.fmask.tiling_index = fout.tileIndex;
958 surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
959 surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
963 !(surf->flags & RADEON_SURF_SHAREABLE)) {
982 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
983 surf->fmask_tile_swizzle = xout.tileSwizzle;
991 if (surf->dcc_size && config->info.levels > 1) {
1000 surf->dcc_size = align64(surf->surf_size >> 8,
1001 surf->dcc_alignment * 4);
1007 if (surf->htile_size && config->info.levels > 1 &&
1008 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
1010 const unsigned total_pixels = surf->surf_size / surf->bpe;
1014 surf->htile_size = (total_pixels / htile_block_size) *
1016 surf->htile_size = align(surf->htile_size, surf->htile_alignment);
1019 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
1020 surf->is_displayable = surf->is_linear ||
1021 surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
1022 surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
1029 if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
1034 ac_compute_cmask(info, config, surf);
1084 struct radeon_surf *surf, bool compressed,
1099 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1100 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1102 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1103 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1104 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1108 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1109 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1115 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1116 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
1118 surf->u.gfx9.surf_slice_size = out.sliceSize;
1119 surf->u.gfx9.surf_pitch = out.pitch;
1120 surf->u.gfx9.surf_height = out.height;
1121 surf->surf_size = out.surfSize;
1122 surf->surf_alignment = out.baseAlign;
1126 surf->u.gfx9.offset[i] = mip_info[i].offset;
1153 surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
1154 surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
1155 surf->htile_size = hout.htileBytes;
1156 surf->htile_slice_size = hout.sliceSize;
1157 surf->htile_alignment = hout.baseAlign;
1165 !(surf->flags & RADEON_SURF_SHAREABLE) &&
1186 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1187 surf->tile_swizzle = xout.pipeBankXor;
1191 if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1220 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1221 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1222 surf->dcc_size = dout.dccRamSize;
1223 surf->dcc_alignment = dout.dccRamBaseAlign;
1224 surf->num_dcc_levels = in->numMipLevels;
1250 surf->num_dcc_levels = i;
1255 if (!surf->num_dcc_levels)
1256 surf->dcc_size = 0;
1258 surf->u.gfx9.display_dcc_size = surf->dcc_size;
1259 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment;
1260 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1264 surf->num_dcc_levels &&
1273 assert(surf->tile_swizzle == 0);
1274 assert(surf->u.gfx9.dcc.pipe_aligned ||
1275 surf->u.gfx9.dcc.rb_aligned);
1281 surf->u.gfx9.display_dcc_size = dout.dccRamSize;
1282 surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign;
1283 surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1;
1284 assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size);
1302 surf->u.gfx9.dcc_retile_num_elements =
1306 surf->u.gfx9.dcc_retile_num_elements =
1307 align(surf->u.gfx9.dcc_retile_num_elements, 4);
1309 surf->u.gfx9.dcc_retile_map =
1310 malloc(surf->u.gfx9.dcc_retile_num_elements * 4);
1311 if (!surf->u.gfx9.dcc_retile_map)
1315 surf->u.gfx9.dcc_retile_use_uint16 = true;
1324 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1325 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1332 surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr;
1334 surf->u.gfx9.dcc_retile_use_uint16 = false;
1345 surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr;
1347 surf->u.gfx9.dcc_retile_use_uint16 = false;
1349 assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements);
1354 for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++)
1355 surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2];
1382 surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
1383 surf->u.gfx9.fmask.epitch = fout.pitch - 1;
1384 surf->fmask_size = fout.fmaskBytes;
1385 surf->fmask_alignment = fout.baseAlign;
1390 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1411 u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1412 surf->fmask_tile_swizzle = xout.pipeBankXor;
1439 cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
1447 surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
1448 surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
1449 surf->cmask_size = cout.cmaskBytes;
1450 surf->cmask_alignment = cout.baseAlign;
1461 struct radeon_surf *surf)
1469 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1474 switch (surf->bpe) {
1485 switch (surf->bpe) {
1487 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
1491 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1492 !(surf->flags & RADEON_SURF_SBUFFER));
1496 assert(surf->flags & RADEON_SURF_ZBUFFER ||
1497 !(surf->flags & RADEON_SURF_SBUFFER));
1501 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1505 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1509 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1515 AddrSurfInfoIn.bpp = surf->bpe * 8;
1518 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1520 !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
1521 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1522 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1525 surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1532 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
1573 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1579 if (surf->flags & RADEON_SURF_IMPORTED) {
1580 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode;
1594 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
1595 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1597 surf->num_dcc_levels = 0;
1598 surf->surf_size = 0;
1599 surf->fmask_size = 0;
1600 surf->dcc_size = 0;
1601 surf->htile_size = 0;
1602 surf->htile_slice_size = 0;
1603 surf->u.gfx9.surf_offset = 0;
1604 surf->u.gfx9.stencil_offset = 0;
1605 surf->cmask_size = 0;
1606 surf->u.gfx9.dcc_retile_use_uint16 = false;
1607 surf->u.gfx9.dcc_retile_num_elements = 0;
1608 surf->u.gfx9.dcc_retile_map = NULL;
1611 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1617 if (surf->flags & RADEON_SURF_SBUFFER) {
1630 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed,
1636 surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
1641 r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode,
1642 surf->bpe * 8, &displayable);
1648 surf->num_dcc_levels &&
1649 (surf->u.gfx9.dcc.pipe_aligned ||
1650 surf->u.gfx9.dcc.rb_aligned))
1653 surf->is_displayable = displayable;
1655 switch (surf->u.gfx9.surf.swizzle_mode) {
1665 surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
1678 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
1707 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
1717 free(surf->u.gfx9.dcc_retile_map);
1718 surf->u.gfx9.dcc_retile_map = NULL;
1725 struct radeon_surf *surf)
1729 r = surf_config_sanity(config, surf->flags);
1734 return gfx9_compute_surface(addrlib, info, config, mode, surf);
1736 return gfx6_compute_surface(addrlib, info, config, mode, surf);