Cross Reference: /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/radv

Lines Matching defs:cs
34                                       struct radeon_cmdbuf *cs,
37         if (cs->max_dw - cs->cdw < needed)
38                 ws->cs_grow(cs, needed);
39         return cs->cdw + needed;
42 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
45         assert(cs->cdw + 2 + num <= cs->max_dw);
47         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
48         radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
51 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
53         radeon_set_config_reg_seq(cs, reg, 1);
54         radeon_emit(cs, value);
57 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
60         assert(cs->cdw + 2 + num <= cs->max_dw);
62         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
63         radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
66 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
68         radeon_set_context_reg_seq(cs, reg, 1);
69         radeon_emit(cs, value);
73 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
78 	assert(cs->cdw + 3 <= cs->max_dw);
79 	radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
80 	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
81 	radeon_emit(cs, value);
84 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
87 	assert(cs->cdw + 2 + num <= cs->max_dw);
89 	radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
90 	radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
93 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
95 	radeon_set_sh_reg_seq(cs, reg, 1);
96 	radeon_emit(cs, value);
99 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
102 	assert(cs->cdw + 2 + num <= cs->max_dw);
104 	radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
105 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
108 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
110 	radeon_set_uconfig_reg_seq(cs, reg, 1);
111 	radeon_emit(cs, value);
114 static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs,
119 	assert(cs->cdw + 3 <= cs->max_dw);
120 	radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
121 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
122 	radeon_emit(cs, value);