Cross Reference: /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/radv

Lines Matching refs:planes
93 	 * 16-bit depth surfaces if no Z planes are compressed.
353 	struct radv_image_plane *plane = &image->planes[plane_id];
668 			fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
670 					  S_008F20_PITCH_GFX9(image->planes[0].surface.u.gfx9.fmask.epitch);
671 			fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
672 					  S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
716 	si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
717 				       image->planes[0].surface.blk_w, false, false, desc);
730 			md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
741 	struct radeon_surf *surface = &image->planes[0].surface;
772 		out->alignment = image->planes[0].surface.fmask_alignment;
773 		out->size = image->planes[0].surface.fmask_size;
774 		out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
778 	out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
779 	out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
780 	out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
781 	out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
782 	out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
783 	out->alignment = image->planes[0].surface.fmask_alignment;
784 	out->size = image->planes[0].surface.fmask_size;
812 		out->alignment = image->planes[0].surface.cmask_alignment;
813 		out->size = image->planes[0].surface.cmask_size;
841 	unsigned width = align(image->planes[0].surface.u.legacy.level[0].nblk_x, cl_width*8);
842 	unsigned height = align(image->planes[0].surface.u.legacy.level[0].nblk_y, cl_height*8);
884 	image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
886 	image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
889 	image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24;
890 	image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
896 	image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
899 	image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
909 	image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
939 	if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
950 	       !image->planes[0].surface.is_linear;
970 		image->planes[i].surface.dcc_size = 0;
976 		image->planes[i].surface.htile_size = 0;
1040 		radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1051 		device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1053 		image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1054 		image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1055 		image->alignment = image->planes[plane].surface.surf_alignment;
1057 		image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1086 				image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1124 	struct radv_image_plane *plane = &image->planes[plane_id];
1189 		return image->planes[0].format;
1191 		return image->planes[1].format;
1193 		return image->planes[2].format;
1253 	if (iview->vk_format != image->planes[iview->plane_id].format) {
1298 			 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1299 			 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1432 	struct radv_image_plane *plane = &image->planes[plane_id];