Lines Matching defs:outinfo
1749 return &pipeline->gs_copy_shader->info.vs.outinfo;
1751 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1753 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2934 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2948 } else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) {
2971 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2973 clip_dist_mask = outinfo->clip_dist_mask;
2974 cull_dist_mask = outinfo->cull_dist_mask;
2976 bool misc_vec_ena = outinfo->writes_pointsize ||
2977 outinfo->writes_layer ||
2978 outinfo->writes_viewport_index;
2981 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2985 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2988 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2991 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3002 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3003 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3004 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3014 outinfo->writes_viewport_index);
3237 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3243 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3253 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3271 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
3277 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
3292 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];