Lines Matching defs:waddr
30 v3d_qpu_magic_waddr_name(enum v3d_qpu_waddr waddr)
76 return waddr_magic[waddr];
520 v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr)
522 switch (waddr) {
536 v3d_qpu_magic_waddr_is_tmu(enum v3d_qpu_waddr waddr)
539 return ((waddr >= V3D_QPU_WADDR_TMU &&
540 waddr <= V3D_QPU_WADDR_TMUAU) ||
541 (waddr >= V3D_QPU_WADDR_TMUC &&
542 waddr <= V3D_QPU_WADDR_TMUHSLOD));
554 v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr)
556 return (waddr == V3D_QPU_WADDR_TLB ||
557 waddr == V3D_QPU_WADDR_TLBU);
561 v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr)
563 return (waddr == V3D_QPU_WADDR_VPM ||
564 waddr == V3D_QPU_WADDR_VPMU);
568 v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr)
570 return (waddr == V3D_QPU_WADDR_SYNC ||
571 waddr == V3D_QPU_WADDR_SYNCB ||
572 waddr == V3D_QPU_WADDR_SYNCU);
576 v3d_qpu_magic_waddr_loads_unif(enum v3d_qpu_waddr waddr)
578 switch (waddr) {
632 v3d_qpu_magic_waddr_is_tlb(inst->alu.add.waddr)) {
637 v3d_qpu_magic_waddr_is_tlb(inst->alu.mul.waddr)) {
662 v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) {
667 v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) {
680 v3d_qpu_magic_waddr_is_tmu(inst->alu.add.waddr)) ||
682 v3d_qpu_magic_waddr_is_tmu(inst->alu.mul.waddr))));
707 v3d_qpu_magic_waddr_is_vpm(inst->alu.add.waddr)) {
712 v3d_qpu_magic_waddr_is_vpm(inst->alu.mul.waddr)) {
732 inst->alu.add.waddr == V3D_QPU_WADDR_R3) {
737 inst->alu.mul.waddr == V3D_QPU_WADDR_R3) {
756 (inst->alu.add.waddr == V3D_QPU_WADDR_R4 ||
757 v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))) {
762 (inst->alu.mul.waddr == V3D_QPU_WADDR_R4 ||
763 v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))) {
784 inst->alu.add.waddr == V3D_QPU_WADDR_R5) {
789 inst->alu.mul.waddr == V3D_QPU_WADDR_R5) {