Lines Matching refs:has
42 Intel graphics has several different tiling formats that we'll discuss in
54 on top of the tiling format. This has been removed starting with Broadwell
58 memory controller has a more effective address swizzling algorithm.
85 The `isl_tile_info` structure has two different sizes for a tile: a logical
87 the proper logical size, the bits-per-block of the underlying format has to be
110 If the surface is a stencil buffer (and thus has Tile Mode set to
117 stencil) has a logical size of 64el x 64el but a physical size of 128B
118 x 32rows. In memory, a W-tile has the same footprint as a Y-tile (128B
131 The simplest tiling format available on Intel graphics (which has been
231 While W-tiling has been required for stencil all the way back to Sandy Bridge,
238 If the surface is a stencil buffer (and thus has Tile Mode set to
320 pattern is practically free. For a format that has more than one byte per