Lines Matching refs:__u64
146 __u64 bo_size;
148 __u64 alignment;
150 __u64 domains;
152 __u64 domain_flags;
183 __u64 bo_info_ptr;
259 __u64 flags;
284 __u64 flags;
320 __u64 addr;
321 __u64 size;
363 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
365 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
378 __u64 flags;
380 __u64 tiling_info;
394 __u64 addr_ptr;
408 __u64 timeout;
428 __u64 handle;
430 __u64 timeout;
439 __u64 status;
452 __u64 seq_no;
457 __u64 fences;
460 __u64 timeout_ns;
483 __u64 value;
527 __u64 va_address;
529 __u64 offset_in_bo;
531 __u64 map_size;
560 __u64 chunk_data;
570 /** this points to __u64 * which point to cs chunks */
571 __u64 chunks;
575 __u64 handle;
616 __u64 va_start;
632 __u64 handle;
647 __u64 point;
849 __u64 return_pointer;
917 __u64 vram_size;
918 __u64 vram_cpu_accessible_size;
919 __u64 gtt_size;
924 __u64 total_heap_size;
927 __u64 usable_heap_size;
935 __u64 heap_usage;
941 __u64 max_allocation;
989 __u64 max_engine_clock;
990 __u64 max_memory_clock;
1001 __u64 ids_flags;
1003 __u64 virtual_address_offset;
1005 __u64 virtual_address_max;
1022 __u64 prim_buf_gpu_addr;
1024 __u64 pos_buf_gpu_addr;
1026 __u64 cntl_sb_buf_gpu_addr;
1028 __u64 param_buf_gpu_addr;
1051 __u64 high_va_offset;
1053 __u64 high_va_max;
1057 __u64 tcc_disabled_mask;
1065 __u64 capabilities_flags;