Cross Reference: /xsrc/external/mit/MesaLib/dist/src/amd/common/ac

Lines Matching defs:AddrSurfInfoIn
572                               bool compressed, ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
583    AddrSurfInfoIn->mipLevel = level;
584    AddrSurfInfoIn->width = u_minify(config->info.width, level);
585    AddrSurfInfoIn->height = u_minify(config->info.height, level);
590    if (config->info.levels == 1 && AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
591        AddrSurfInfoIn->bpp && util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) {
592       unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
594       AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
599    if (AddrSurfInfoIn->bpp == 96) {
601       assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED);
605       AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16);
609       AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
611       AddrSurfInfoIn->numSlices = 6;
613       AddrSurfInfoIn->numSlices = config->info.array_size;
619          AddrSurfInfoIn->basePitch = surf->u.legacy.zs.stencil_level[0].nblk_x;
621          AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
625          AddrSurfInfoIn->basePitch *= surf->blk_w;
628    ret = AddrComputeSurfaceInfo(addrlib, AddrSurfInfoIn, AddrSurfInfoOut);
661    if (AddrSurfInfoIn->flags.prt) {
676    if (!AddrSurfInfoIn->flags.depth && !AddrSurfInfoIn->flags.stencil)
680    if (AddrSurfInfoIn->flags.dccCompatible && (level == 0 || AddrDccOut->subLvlCompressible)) {
756    if (!is_stencil && AddrSurfInfoIn->flags.depth && surf_level->mode == RADEON_SURF_MODE_2D &&
964    ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
974    AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
995       AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
999          AddrSurfInfoIn.tileMode = ADDR_TM_PRT_TILED_THIN1;
1001          AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
1005          AddrSurfInfoIn.tileMode = ADDR_TM_PRT_2D_TILED_THIN1;
1007          AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
1019          AddrSurfInfoIn.format = ADDR_FMT_BC1;
1022          AddrSurfInfoIn.format = ADDR_FMT_BC3;
1028       AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
1031    AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
1032    AddrSurfInfoIn.tileIndex = -1;
1035       AddrDccIn.numSamples = AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
1040       AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
1042       AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
1044       AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
1046    AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1047    AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1048    AddrSurfInfoIn.flags.cube = config->is_cube;
1049    AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1050    AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
1051    AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
1052    AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0;
1057    AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
1058                                     !AddrSurfInfoIn.flags.fmask && config->info.samples <= 1 &&
1067    AddrSurfInfoIn.flags.dccCompatible =
1073    AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
1074    AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1095    if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
1100       AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
1103       AddrSurfInfoIn.flags.noStencil = 1;
1109        AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw &&
1119       AddrSurfInfoIn.flags.opt4Space = 0;
1120       AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
1122       /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
1131       assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
1134          if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
1136                AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
1138                AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
1141                AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
1143                AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
1145                AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
1147                AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
1151          if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
1152             AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
1154             AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
1174          r = gfx6_compute_level(addrlib, config, surf, false, level, compressed, &AddrSurfInfoIn,
1184             AddrSurfInfoIn.flags.tcCompatible = 0;
1188          if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
1189             AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
1190             AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
1204       AddrSurfInfoIn.tileIndex = stencil_tile_idx;
1205       AddrSurfInfoIn.bpp = 8;
1206       AddrSurfInfoIn.flags.depth = 0;
1207       AddrSurfInfoIn.flags.stencil = 1;
1208       AddrSurfInfoIn.flags.tcCompatible = 0;
1209       /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
1213          r = gfx6_compute_level(addrlib, config, surf, true, level, compressed, &AddrSurfInfoIn,
1242    if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color && info->has_graphics &&
1254       fin.numSlices = AddrSurfInfoIn.numSlices;
1255       fin.numSamples = AddrSurfInfoIn.numSamples;
1256       fin.numFrags = AddrSurfInfoIn.numFrags;
2037    ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
2040    AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT);
2049          AddrSurfInfoIn.format = ADDR_FMT_BC1;
2052          AddrSurfInfoIn.format = ADDR_FMT_BC3;
2061          AddrSurfInfoIn.format = ADDR_FMT_8;
2065          AddrSurfInfoIn.format = ADDR_FMT_16;
2069          AddrSurfInfoIn.format = ADDR_FMT_32;
2073          AddrSurfInfoIn.format = ADDR_FMT_32_32;
2077          AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
2081          AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
2086       AddrSurfInfoIn.bpp = surf->bpe * 8;
2090    AddrSurfInfoIn.flags.color = is_color_surface && !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
2091    AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
2092    AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
2094    AddrSurfInfoIn.flags.texture = is_color_surface || surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
2095    AddrSurfInfoIn.flags.opt4space = 1;
2096    AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0;
2098    AddrSurfInfoIn.numMipLevels = config->info.levels;
2099    AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples);
2100    AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
2103       AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
2109       AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
2111       AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
2113       AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
2115    AddrSurfInfoIn.width = config->info.width;
2116    AddrSurfInfoIn.height = config->info.height;
2119       AddrSurfInfoIn.numSlices = config->info.depth;
2121       AddrSurfInfoIn.numSlices = 6;
2123       AddrSurfInfoIn.numSlices = config->info.array_size;
2126    AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
2127    AddrSurfInfoIn.flags.metaRbUnaligned = 0;
2130       ac_modifier_fill_dcc_params(surf->modifier, surf, &AddrSurfInfoIn);
2131    } else if (!AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.stencil) {
2146       if (AddrSurfInfoIn.flags.display) {
2155             AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
2156             AddrSurfInfoIn.flags.metaRbUnaligned = 1;
2192          AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR;
2199             AddrSurfInfoIn.swizzleMode = surf->u.gfx9.swizzle_mode;
2203          r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
2204                                              &AddrSurfInfoIn.swizzleMode);
2219       AddrSurfInfoIn.swizzleMode = ac_modifier_gfx9_swizzle_mode(surf->modifier);
2222    surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
2231    if (AddrSurfInfoIn.flags.stencil)
2240       r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2247       AddrSurfInfoIn.flags.stencil = 1;
2248       AddrSurfInfoIn.bpp = 8;
2249       AddrSurfInfoIn.format = ADDR_FMT_8;
2251       if (!AddrSurfInfoIn.flags.depth) {
2252          r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
2253                                              &AddrSurfInfoIn.swizzleMode);
2257          AddrSurfInfoIn.flags.depth = 0;
2259       r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2287    assert(!AddrSurfInfoIn.flags.display || surf->is_displayable);
2292       if (AddrSurfInfoIn.flags.color)
2294       if (AddrSurfInfoIn.flags.display) {
2301        AddrSurfInfoIn.flags.color && !surf->is_linear &&
2311           AddrSurfInfoIn.flags.display && surf->bpe == 4) {
2316       if (!AddrSurfInfoIn.flags.display)