Cross Reference: /xsrc/external/mit/MesaLib/dist/src/amd/common/ac

Lines Matching refs:dcc
150    return (!surf->u.gfx9.color.dcc.independent_64B_blocks &&
151             surf->u.gfx9.color.dcc.independent_128B_blocks &&
152             surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) ||
154             surf->u.gfx9.color.dcc.independent_64B_blocks &&
155             surf->u.gfx9.color.dcc.independent_128B_blocks &&
156             surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
185    surf->u.gfx9.color.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
186    surf->u.gfx9.color.dcc.independent_128B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
187    surf->u.gfx9.color.dcc.max_compressed_block_size = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier);
235       if (!options->dcc)
1446       return surf->u.gfx9.color.dcc.independent_64B_blocks && !surf->u.gfx9.color.dcc.independent_128B_blocks &&
1447              surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B;
1452       return !surf->u.gfx9.color.dcc.independent_64B_blocks && surf->u.gfx9.color.dcc.independent_128B_blocks &&
1453              surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
1460       return surf->u.gfx9.color.dcc.independent_64B_blocks != surf->u.gfx9.color.dcc.independent_128B_blocks &&
1461              (!surf->u.gfx9.color.dcc.independent_64B_blocks ||
1462               surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B) &&
1463              (!surf->u.gfx9.color.dcc.independent_128B_blocks ||
1464               surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B);
1471    return surf->u.gfx9.color.dcc.independent_128B_blocks &&
1472           surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
1504       /* Non-dcc modifiers */
1536       assert(surf->u.gfx9.color.dcc.independent_64B_blocks &&
1537              surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
1542       if (info->chip_class == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks)
1546               (surf->u.gfx9.color.dcc.independent_64B_blocks &&
1547                surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B));
1555                                  ADDR2_COMPUTE_DCCINFO_OUTPUT *dcc,
1558    equation->meta_block_width = dcc->metaBlkWidth;
1559    equation->meta_block_height = dcc->metaBlkHeight;
1560    equation->meta_block_depth = dcc->metaBlkDepth;
1565          assert(dcc->equation.gfx10_bits[i] == 0);
1568          assert(dcc->equation.gfx10_bits[i] == 0);
1570       memcpy(equation->u.gfx10_bits, dcc->equation.gfx10_bits + 4,
1573       assert(dcc->equation.gfx9.num_bits <= ARRAY_SIZE(equation->u.gfx9.bit));
1575       equation->u.gfx9.num_bits = dcc->equation.gfx9.num_bits;
1576       equation->u.gfx9.num_pipe_bits = dcc->equation.gfx9.numPipeBits;
1579             equation->u.gfx9.bit[b].coord[c].dim = dcc->equation.gfx9.bit[b].coord[c].dim;
1580             equation->u.gfx9.bit[b].coord[c].ord = dcc->equation.gfx9.bit[b].coord[c].ord;
1836          surf->u.gfx9.color.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1837          surf->u.gfx9.color.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1911             assert(surf->u.gfx9.color.dcc.pipe_aligned || surf->u.gfx9.color.dcc.rb_aligned);
1924             surf->u.gfx9.color.dcc.display_equation_valid = true;
2136             surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
2137             surf->u.gfx9.color.dcc.independent_128B_blocks = 0;
2138             surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2140             surf->u.gfx9.color.dcc.independent_64B_blocks = 0;
2141             surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
2142             surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2167                surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
2168                surf->u.gfx9.color.dcc.independent_128B_blocks = 0;
2169                surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2179                surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
2180                surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
2181                surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2278           (!is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2279                                     surf->u.gfx9.color.dcc.pipe_aligned) ||
2281            (info->use_display_dcc_with_retile_blit && !surf->u.gfx9.color.dcc.display_equation_valid)))
2295          assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2296                                         surf->u.gfx9.color.dcc.pipe_aligned));
2307        is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2308                                surf->u.gfx9.color.dcc.pipe_aligned)) {
2430           surf->u.gfx9.color.dcc.display_equation_valid) {
2519       surf->u.gfx9.color.dcc.independent_64B_blocks =
2521       surf->u.gfx9.color.dcc.independent_128B_blocks =
2523       surf->u.gfx9.color.dcc.max_compressed_block_size =
2569          AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, surf->u.gfx9.color.dcc.independent_64B_blocks);
2571          AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, surf->u.gfx9.color.dcc.independent_128B_blocks);
2573                                          surf->u.gfx9.color.dcc.max_compressed_block_size);
2667          surf->u.gfx9.color.dcc.pipe_aligned = G_008F24_META_PIPE_ALIGNED(desc[5]);
2668          surf->u.gfx9.color.dcc.rb_aligned = G_008F24_META_RB_ALIGNED(desc[5]);
2671          if (!surf->u.gfx9.color.dcc.pipe_aligned && !surf->u.gfx9.color.dcc.rb_aligned)
2679          surf->u.gfx9.color.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]);