Cross Reference: /xsrc/external/mit/MesaLib/dist/src/amd/common/ac

Lines Matching refs:legacy
619          AddrSurfInfoIn->basePitch = surf->u.legacy.zs.stencil_level[0].nblk_x;
621          AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
633    surf_level = is_stencil ? &surf->u.legacy.zs.stencil_level[level] : &surf->u.legacy.level[level];
634    dcc_level = &surf->u.legacy.color.dcc_level[level];
657       surf->u.legacy.zs.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
659       surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
784    uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
797    tileb = MIN2(surf->u.legacy.tile_split, tileb);
847    surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
852       surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
853       surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
854       surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
855       surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
856       surf->u.legacy.num_banks = csio->pTileInfo->banks;
857       surf->u.legacy.macro_tile_index = csio->macroModeIndex;
859       surf->u.legacy.macro_tile_index = 0;
865        surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
928    unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width * 8);
929    unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8);
935    surf->u.legacy.color.cmask_slice_tile_max = (width * height) / (128 * 128);
936    if (surf->u.legacy.color.cmask_slice_tile_max)
937       surf->u.legacy.color.cmask_slice_tile_max -= 1;
1109        AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw &&
1110        surf->u.legacy.bankh && surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
1113       AddrTileInfoIn.banks = surf->u.legacy.num_banks;
1114       AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
1115       AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
1116       AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
1117       AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
1118       AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
1210       AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
1220             if (surf->u.legacy.zs.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
1221                surf->u.legacy.stencil_adjusted = true;
1223             surf->u.legacy.level[level].nblk_x = surf->u.legacy.zs.stencil_level[level].nblk_x;
1235                surf->u.legacy.stencil_tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
1269       surf->u.legacy.color.fmask.slice_tile_max = (fout.pitch * fout.height) / 64;
1270       if (surf->u.legacy.color.fmask.slice_tile_max)
1271          surf->u.legacy.color.fmask.slice_tile_max -= 1;
1273       surf->u.legacy.color.fmask.tiling_index = fout.tileIndex;
1274       surf->u.legacy.color.fmask.bankh = fout.pTileInfo->bankHeight;
1275       surf->u.legacy.color.fmask.pitch_in_pixels = fout.pitch;
1334    surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
2530       surf->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2531       surf->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2532       surf->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2533       surf->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
2534       surf->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2535       surf->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2576       if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D)
2578       else if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D)
2583       *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, surf->u.legacy.pipe_config);
2584       *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(surf->u.legacy.bankw));
2585       *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(surf->u.legacy.bankh));
2586       if (surf->u.legacy.tile_split)
2588             AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(surf->u.legacy.tile_split));
2589       *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(surf->u.legacy.mtilea));
2590       *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks) - 1);
2618       offset = (uint64_t)surf->u.legacy.level[0].offset_256B * 256;
2748          metadata[10 + i] = surf->u.legacy.level[i].offset_256B;
2814          if (surf->u.legacy.level[0].nblk_x != pitch && require_equal_pitch)
2817          surf->u.legacy.level[0].nblk_x = pitch;
2818          surf->u.legacy.level[0].slice_size_dw =
2819             ((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4;
2823          for (unsigned i = 0; i < ARRAY_SIZE(surf->u.legacy.level); ++i)
2824             surf->u.legacy.level[i].offset_256B += offset / 256;
2865          return (uint64_t)surf->u.legacy.level[0].offset_256B * 256 +
2866                 layer * (uint64_t)surf->u.legacy.level[0].slice_size_dw * 4;
2889          return surf->u.legacy.level[0].nblk_x * surf->bpe;
2975               surf->u.legacy.bankw, surf->u.legacy.bankh,
2976               surf->u.legacy.num_banks, surf->u.legacy.mtilea,
2977               surf->u.legacy.tile_split, surf->u.legacy.pipe_config,
2986                  1 << surf->fmask_alignment_log2, surf->u.legacy.color.fmask.pitch_in_pixels,
2987                  surf->u.legacy.color.fmask.bankh,
2988                  surf->u.legacy.color.fmask.slice_tile_max,
2989                  surf->u.legacy.color.fmask.tiling_index);
2996                  1 << surf->cmask_alignment_log2, surf->u.legacy.color.cmask_slice_tile_max);
3009                  surf->u.legacy.stencil_tile_split);