Lines Matching refs:surf
125 const struct radeon_surf *surf)
150 return (!surf->u.gfx9.color.dcc.independent_64B_blocks &&
151 surf->u.gfx9.color.dcc.independent_128B_blocks &&
152 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) ||
154 surf->u.gfx9.color.dcc.independent_64B_blocks &&
155 surf->u.gfx9.color.dcc.independent_128B_blocks &&
156 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
168 ac_modifier_fill_dcc_params(uint64_t modifier, struct radeon_surf *surf,
185 surf->u.gfx9.color.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
186 surf->u.gfx9.color.dcc.independent_128B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
187 surf->u.gfx9.color.dcc.max_compressed_block_size = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier);
571 struct radeon_surf *surf, bool is_stencil, unsigned level,
619 AddrSurfInfoIn->basePitch = surf->u.legacy.zs.stencil_level[0].nblk_x;
621 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
625 AddrSurfInfoIn->basePitch *= surf->blk_w;
633 surf_level = is_stencil ? &surf->u.legacy.zs.stencil_level[level] : &surf->u.legacy.level[level];
634 dcc_level = &surf->u.legacy.color.dcc_level[level];
635 surf_level->offset_256B = align64(surf->surf_size, AddrSurfInfoOut->baseAlign) / 256;
657 surf->u.legacy.zs.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
659 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
663 surf->prt_tile_width = AddrSurfInfoOut->pitchAlign;
664 surf->prt_tile_height = AddrSurfInfoOut->heightAlign;
666 if (surf_level->nblk_x >= surf->prt_tile_width &&
667 surf_level->nblk_y >= surf->prt_tile_height) {
669 surf->first_mip_tail_level = level + 1;
673 surf->surf_size = (uint64_t)surf_level->offset_256B * 256 + AddrSurfInfoOut->surfSize;
692 dcc_level->dcc_offset = surf->meta_size;
693 surf->num_meta_levels = level + 1;
694 surf->meta_size = dcc_level->dcc_offset + AddrDccOut->dccRamSize;
695 surf->meta_alignment_log2 = MAX2(surf->meta_alignment_log2, util_logbase2(AddrDccOut->dccRamBaseAlign));
718 surf->meta_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
743 if (surf->flags & RADEON_SURF_CONTIGUOUS_DCC_LAYERS &&
744 surf->meta_slice_size != dcc_level->dcc_slice_fast_clear_size) {
745 surf->meta_size = 0;
746 surf->num_meta_levels = 0;
757 level == 0 && !(surf->flags & RADEON_SURF_NO_HTILE)) {
771 surf->meta_size = AddrHtileOut->htileBytes;
772 surf->meta_slice_size = AddrHtileOut->sliceSize;
773 surf->meta_alignment_log2 = util_logbase2(AddrHtileOut->baseAlign);
774 surf->meta_pitch = AddrHtileOut->pitch;
775 surf->num_meta_levels = level + 1;
782 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf, const struct radeon_info *info)
784 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
787 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
789 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
792 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
796 tileb = 8 * 8 * surf->bpe;
797 tileb = MIN2(surf->u.legacy.tile_split, tileb);
806 static bool get_display_flag(const struct ac_surf_config *config, const struct radeon_surf *surf)
809 unsigned bpe = surf->bpe;
815 if (surf->modifier != DRM_FORMAT_MOD_INVALID)
818 if (!config->is_3d && !config->is_cube && !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
819 surf->flags & RADEON_SURF_SCANOUT && config->info.samples <= 1 && surf->blk_w <= 2 &&
820 surf->blk_h == 1) {
822 if (surf->blk_w == 2 && surf->blk_h == 1)
844 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *csio, struct radeon_surf *surf)
846 surf->surf_alignment_log2 = util_logbase2(csio->baseAlign);
847 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
848 gfx6_set_micro_tile_mode(surf, info);
852 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
853 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
854 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
855 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
856 surf->u.legacy.num_banks = csio->pTileInfo->banks;
857 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
859 surf->u.legacy.macro_tile_index = 0;
865 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
866 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
867 !get_display_flag(config, surf)) {
885 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
886 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
892 struct radeon_surf *surf)
898 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER || surf->is_linear ||
899 (config->info.samples >= 2 && !surf->fmask_size))
928 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width * 8);
929 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8);
935 surf->u.legacy.color.cmask_slice_tile_max = (width * height) / (128 * 128);
936 if (surf->u.legacy.color.cmask_slice_tile_max)
937 surf->u.legacy.color.cmask_slice_tile_max -= 1;
947 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align));
948 surf->cmask_slice_size = align(slice_bytes, base_align);
949 surf->cmask_size = surf->cmask_slice_size * num_layers;
953 * Fill in the tiling information in \p surf based on the given surface config.
955 * The following fields of \p surf must be initialized by the caller:
960 struct radeon_surf *surf)
982 compressed = surf->blk_w == 4 && surf->blk_h == 4;
989 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) && mode < RADEON_SURF_MODE_1D)
998 if (surf->flags & RADEON_SURF_PRT)
1004 if (surf->flags & RADEON_SURF_PRT)
1017 switch (surf->bpe) {
1028 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
1034 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
1039 if (surf->flags & RADEON_SURF_SCANOUT)
1041 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
1046 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1047 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1049 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1051 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
1052 AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0;
1059 !(surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE);
1069 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1073 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
1074 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1108 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
1109 AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw &&
1110 surf->u.legacy.bankh && surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
1113 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
1114 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
1115 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
1116 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
1117 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
1118 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
1130 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1135 if (surf->bpe == 2)
1140 if (surf->bpe == 1)
1142 else if (surf->bpe == 2)
1144 else if (surf->bpe == 4)
1157 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
1161 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1162 surf->num_meta_levels = 0;
1163 surf->surf_size = 0;
1164 surf->meta_size = 0;
1165 surf->meta_slice_size = 0;
1166 surf->meta_alignment_log2 = 0;
1169 (surf->flags & RADEON_SURF_SBUFFER) && !(surf->flags & RADEON_SURF_ZBUFFER);
1174 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed, &AddrSurfInfoIn,
1185 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
1196 r = gfx6_surface_settings(addrlib, info, config, &AddrSurfInfoOut, surf);
1203 if (surf->flags & RADEON_SURF_SBUFFER) {
1210 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
1213 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed, &AddrSurfInfoIn,
1220 if (surf->u.legacy.zs.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
1221 surf->u.legacy.stencil_adjusted = true;
1223 surf->u.legacy.level[level].nblk_x = surf->u.legacy.zs.stencil_level[level].nblk_x;
1228 r = gfx6_surface_settings(addrlib, info, config, &AddrSurfInfoOut, surf);
1235 surf->u.legacy.stencil_tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
1243 !(surf->flags & RADEON_SURF_NO_FMASK)) {
1264 surf->fmask_size = fout.fmaskBytes;
1265 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign);
1266 surf->fmask_slice_size = fout.sliceSize;
1267 surf->fmask_tile_swizzle = 0;
1269 surf->u.legacy.color.fmask.slice_tile_max = (fout.pitch * fout.height) / 64;
1270 if (surf->u.legacy.color.fmask.slice_tile_max)
1271 surf->u.legacy.color.fmask.slice_tile_max -= 1;
1273 surf->u.legacy.color.fmask.tiling_index = fout.tileIndex;
1274 surf->u.legacy.color.fmask.bankh = fout.pTileInfo->bankHeight;
1275 surf->u.legacy.color.fmask.pitch_in_pixels = fout.pitch;
1278 if (config->info.fmask_surf_index && !(surf->flags & RADEON_SURF_SHAREABLE)) {
1296 assert(xout.tileSwizzle <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1297 surf->fmask_tile_swizzle = xout.tileSwizzle;
1305 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->meta_size && config->info.levels > 1) {
1314 surf->meta_size = align64(surf->surf_size >> 8, (1 << surf->meta_alignment_log2) * 4);
1320 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_TC_COMPATIBLE_HTILE) &&
1321 surf->meta_size && config->info.levels > 1) {
1323 const unsigned total_pixels = surf->surf_size / surf->bpe;
1327 surf->meta_size = (total_pixels / htile_block_size) * htile_element_size;
1328 surf->meta_size = align(surf->meta_size, 1 << surf->meta_alignment_log2);
1329 } else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER && !surf->meta_size) {
1331 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
1334 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
1335 surf->is_displayable = surf->is_linear || surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
1336 surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
1343 if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER) {
1348 ac_compute_cmask(info, config, surf);
1354 struct radeon_surf *surf,
1395 if (surf->flags & RADEON_SURF_FORCE_MICRO_TILE_MODE) {
1398 if (surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1400 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_STANDARD)
1402 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_DEPTH)
1404 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER)
1442 const struct radeon_surf *surf)
1446 return surf->u.gfx9.color.dcc.independent_64B_blocks && !surf->u.gfx9.color.dcc.independent_128B_blocks &&
1447 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B;
1452 return !surf->u.gfx9.color.dcc.independent_64B_blocks && surf->u.gfx9.color.dcc.independent_128B_blocks &&
1453 surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
1460 return surf->u.gfx9.color.dcc.independent_64B_blocks != surf->u.gfx9.color.dcc.independent_128B_blocks &&
1461 (!surf->u.gfx9.color.dcc.independent_64B_blocks ||
1462 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B) &&
1463 (!surf->u.gfx9.color.dcc.independent_128B_blocks ||
1464 surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B);
1471 return surf->u.gfx9.color.dcc.independent_128B_blocks &&
1472 surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
1512 const struct radeon_surf *surf, bool rb_aligned,
1519 if (surf->bpe != 4)
1536 assert(surf->u.gfx9.color.dcc.independent_64B_blocks &&
1537 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
1542 if (info->chip_class == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks)
1546 (surf->u.gfx9.color.dcc.independent_64B_blocks &&
1547 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B));
1627 const struct ac_surf_config *config, struct radeon_surf *surf,
1642 surf->prt_tile_width = out.blockWidth;
1643 surf->prt_tile_height = out.blockHeight;
1645 for (surf->first_mip_tail_level = 0; surf->first_mip_tail_level < in->numMipLevels;
1646 ++surf->first_mip_tail_level) {
1647 if(mip_info[surf->first_mip_tail_level].pitch < out.blockWidth ||
1648 mip_info[surf->first_mip_tail_level].height < out.blockHeight)
1653 surf->u.gfx9.prt_level_offset[i] = mip_info[i].macroBlockOffset + mip_info[i].mipTailOffset;
1656 surf->u.gfx9.prt_level_pitch[i] = mip_info[i].pitch;
1658 surf->u.gfx9.prt_level_pitch[i] = out.mipChainPitch;
1663 surf->u.gfx9.zs.stencil_swizzle_mode = in->swizzleMode;
1664 surf->u.gfx9.zs.stencil_epitch =
1666 surf->surf_alignment_log2 = MAX2(surf->surf_alignment_log2, util_logbase2(out.baseAlign));
1667 surf->u.gfx9.zs.stencil_offset = align(surf->surf_size, out.baseAlign);
1668 surf->surf_size = surf->u.gfx9.zs.stencil_offset + out.surfSize;
1672 surf->u.gfx9.swizzle_mode = in->swizzleMode;
1673 surf->u.gfx9.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 : out.mipChainPitch - 1;
1679 surf->u.gfx9.color.fmask_swizzle_mode = surf->u.gfx9.swizzle_mode & ~0x3;
1680 surf->u.gfx9.color.fmask_epitch = surf->u.gfx9.epitch;
1683 surf->u.gfx9.surf_slice_size = out.sliceSize;
1684 surf->u.gfx9.surf_pitch = out.pitch;
1685 surf->u.gfx9.surf_height = out.height;
1686 surf->surf_size = out.surfSize;
1687 surf->surf_alignment_log2 = util_logbase2(out.baseAlign);
1689 if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch &&
1690 surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR) {
1692 surf->u.gfx9.surf_pitch = align(surf->u.gfx9.surf_pitch / surf->blk_w, 256 / surf->bpe);
1693 surf->u.gfx9.epitch =
1694 MAX2(surf->u.gfx9.epitch, surf->u.gfx9.surf_pitch * surf->blk_w - 1);
1695 /* The surface is really a surf->bpe bytes per pixel surface even if we
1696 * use it as a surf->bpe bytes per element one.
1700 surf->u.gfx9.surf_slice_size =
1701 MAX2(surf->u.gfx9.surf_slice_size,
1702 surf->u.gfx9.surf_pitch * out.height * surf->bpe * surf->blk_w);
1703 surf->surf_size = surf->u.gfx9.surf_slice_size * in->numSlices;
1708 surf->u.gfx9.offset[i] = mip_info[i].offset;
1709 surf->u.gfx9.pitch[i] = mip_info[i].pitch;
1713 surf->u.gfx9.base_mip_width = mip_info[0].pitch;
1714 surf->u.gfx9.base_mip_height = mip_info[0].height;
1719 if (surf->flags & RADEON_SURF_NO_HTILE)
1748 surf->meta_size = hout.htileBytes;
1749 surf->meta_slice_size = hout.sliceSize;
1750 surf->meta_alignment_log2 = util_logbase2(hout.baseAlign);
1751 surf->meta_pitch = hout.pitch;
1752 surf->num_meta_levels = in->numMipLevels;
1755 surf->u.gfx9.meta_levels[i].offset = meta_mip_info[i].offset;
1756 surf->u.gfx9.meta_levels[i].size = meta_mip_info[i].sliceSize;
1762 surf->num_meta_levels = i + 1;
1767 if (!surf->num_meta_levels)
1768 surf->meta_size = 0;
1771 ac_copy_htile_equation(info, &hout, &surf->u.gfx9.zs.htile_equation);
1780 !(surf->flags & RADEON_SURF_SHAREABLE) && !in->flags.display) {
1799 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1800 surf->tile_swizzle = xout.pipeBankXor;
1804 if (info->has_graphics && !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed &&
1807 is_dcc_supported_by_DCN(info, config, surf, !in->flags.metaRbUnaligned,
1809 (surf->modifier == DRM_FORMAT_MOD_INVALID ||
1810 ac_modifier_has_dcc(surf->modifier))) {
1836 surf->u.gfx9.color.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1837 surf->u.gfx9.color.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1838 surf->u.gfx9.color.dcc_block_width = dout.compressBlkWidth;
1839 surf->u.gfx9.color.dcc_block_height = dout.compressBlkHeight;
1840 surf->u.gfx9.color.dcc_block_depth = dout.compressBlkDepth;
1841 surf->u.gfx9.color.dcc_pitch_max = dout.pitch - 1;
1842 surf->u.gfx9.color.dcc_height = dout.height;
1843 surf->meta_size = dout.dccRamSize;
1844 surf->meta_slice_size = dout.dccRamSliceSize;
1845 surf->meta_alignment_log2 = util_logbase2(dout.dccRamBaseAlign);
1846 surf->num_meta_levels = in->numMipLevels;
1871 surf->u.gfx9.meta_levels[i].offset = meta_mip_info[i].offset;
1872 surf->u.gfx9.meta_levels[i].size = meta_mip_info[i].sliceSize;
1882 surf->num_meta_levels = i + 1;
1884 surf->num_meta_levels = i;
1889 if (!surf->num_meta_levels)
1890 surf->meta_size = 0;
1892 surf->u.gfx9.color.display_dcc_size = surf->meta_size;
1893 surf->u.gfx9.color.display_dcc_alignment_log2 = surf->meta_alignment_log2;
1894 surf->u.gfx9.color.display_dcc_pitch_max = surf->u.gfx9.color.dcc_pitch_max;
1895 surf->u.gfx9.color.display_dcc_height = surf->u.gfx9.color.dcc_height;
1898 ac_copy_dcc_equation(info, &dout, &surf->u.gfx9.color.dcc_equation);
1902 ac_modifier_has_dcc_retile(surf->modifier)) && surf->num_meta_levels) {
1910 assert(surf->tile_swizzle == 0);
1911 assert(surf->u.gfx9.color.dcc.pipe_aligned || surf->u.gfx9.color.dcc.rb_aligned);
1917 surf->u.gfx9.color.display_dcc_size = dout.dccRamSize;
1918 surf->u.gfx9.color.display_dcc_alignment_log2 = util_logbase2(dout.dccRamBaseAlign);
1919 surf->u.gfx9.color.display_dcc_pitch_max = dout.pitch - 1;
1920 surf->u.gfx9.color.display_dcc_height = dout.height;
1921 assert(surf->u.gfx9.color.display_dcc_size <= surf->meta_size);
1923 ac_copy_dcc_equation(info, &dout, &surf->u.gfx9.color.display_dcc_equation);
1924 surf->u.gfx9.color.dcc.display_equation_valid = true;
1929 if (in->numSamples > 1 && info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) {
1936 ret = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, in, true, &fin.swizzleMode);
1950 surf->u.gfx9.color.fmask_swizzle_mode = fin.swizzleMode;
1951 surf->u.gfx9.color.fmask_epitch = fout.pitch - 1;
1952 surf->fmask_size = fout.fmaskBytes;
1953 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign);
1954 surf->fmask_slice_size = fout.sliceSize;
1958 !(surf->flags & RADEON_SURF_SHAREABLE)) {
1978 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
1979 surf->fmask_tile_swizzle = xout.pipeBankXor;
1987 (surf->fmask_size && in->numSamples >= 2))) {
2009 cin.swizzleMode = surf->u.gfx9.color.fmask_swizzle_mode;
2017 surf->cmask_size = cout.cmaskBytes;
2018 surf->cmask_alignment_log2 = util_logbase2(cout.baseAlign);
2019 surf->cmask_slice_size = cout.sliceSize;
2020 surf->cmask_pitch = cout.pitch;
2021 surf->cmask_height = cout.height;
2022 surf->u.gfx9.color.cmask_level0.offset = meta_mip_info[0].offset;
2023 surf->u.gfx9.color.cmask_level0.size = meta_mip_info[0].sliceSize;
2025 ac_copy_cmask_equation(info, &cout, &surf->u.gfx9.color.cmask_equation);
2034 struct radeon_surf *surf)
2042 compressed = surf->blk_w == 4 && surf->blk_h == 4;
2047 switch (surf->bpe) {
2058 switch (surf->bpe) {
2060 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
2064 assert(surf->flags & RADEON_SURF_ZBUFFER || !(surf->flags & RADEON_SURF_SBUFFER));
2068 assert(surf->flags & RADEON_SURF_ZBUFFER || !(surf->flags & RADEON_SURF_SBUFFER));
2072 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
2076 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
2080 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
2086 AddrSurfInfoIn.bpp = surf->bpe * 8;
2089 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
2090 AddrSurfInfoIn.flags.color = is_color_surface && !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
2091 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
2092 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
2094 AddrSurfInfoIn.flags.texture = is_color_surface || surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
2096 AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0;
2102 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
2129 if (ac_modifier_has_dcc(surf->modifier)) {
2130 ac_modifier_fill_dcc_params(surf->modifier, surf, &AddrSurfInfoIn);
2134 if (!(surf->flags & RADEON_SURF_IMPORTED)) {
2136 surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
2137 surf->u.gfx9.color.dcc.independent_128B_blocks = 0;
2138 surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2140 surf->u.gfx9.color.dcc.independent_64B_blocks = 0;
2141 surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
2142 surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2161 if (!(surf->flags & RADEON_SURF_IMPORTED) &&
2167 surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
2168 surf->u.gfx9.color.dcc.independent_128B_blocks = 0;
2169 surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2179 surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
2180 surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
2181 surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2187 if (surf->modifier == DRM_FORMAT_MOD_INVALID) {
2191 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
2197 if (surf->flags & RADEON_SURF_IMPORTED ||
2198 (info->chip_class >= GFX10 && surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE)) {
2199 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.swizzle_mode;
2203 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
2216 assert(!ac_modifier_has_dcc(surf->modifier) ||
2217 !(surf->flags & RADEON_SURF_DISABLE_DCC));
2219 AddrSurfInfoIn.swizzleMode = ac_modifier_gfx9_swizzle_mode(surf->modifier);
2222 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
2223 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
2225 surf->num_meta_levels = 0;
2226 surf->surf_size = 0;
2227 surf->fmask_size = 0;
2228 surf->meta_size = 0;
2229 surf->meta_slice_size = 0;
2230 surf->u.gfx9.surf_offset = 0;
2232 surf->u.gfx9.zs.stencil_offset = 0;
2233 surf->cmask_size = 0;
2236 (surf->flags & RADEON_SURF_SBUFFER) && !(surf->flags & RADEON_SURF_ZBUFFER);
2240 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2246 if (surf->flags & RADEON_SURF_SBUFFER) {
2252 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
2259 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2264 surf->is_linear = surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR;
2270 r = Addr2IsValidDisplaySwizzleMode(addrlib->handle, surf->u.gfx9.swizzle_mode,
2271 surf->bpe * 8, &displayable);
2276 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
2277 surf->num_meta_levels &&
2278 (!is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2279 surf->u.gfx9.color.dcc.pipe_aligned) ||
2281 (info->use_display_dcc_with_retile_blit && !surf->u.gfx9.color.dcc.display_equation_valid)))
2284 surf->is_displayable = displayable;
2287 assert(!AddrSurfInfoIn.flags.display || surf->is_displayable);
2290 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->num_meta_levels) {
2291 assert(is_dcc_supported_by_L2(info, surf));
2293 assert(is_dcc_supported_by_CB(info, surf->u.gfx9.swizzle_mode));
2295 assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2296 surf->u.gfx9.color.dcc.pipe_aligned));
2301 AddrSurfInfoIn.flags.color && !surf->is_linear &&
2302 (1 << surf->surf_alignment_log2) >= 64 * 1024 && /* 64KB tiling */
2303 !(surf->flags & (RADEON_SURF_DISABLE_DCC | RADEON_SURF_FORCE_SWIZZLE_MODE |
2305 (surf->modifier == DRM_FORMAT_MOD_INVALID ||
2306 ac_modifier_has_dcc(surf->modifier)) &&
2307 is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2308 surf->u.gfx9.color.dcc.pipe_aligned)) {
2311 AddrSurfInfoIn.flags.display && surf->bpe == 4) {
2312 assert(surf->num_meta_levels);
2317 assert(surf->num_meta_levels);
2320 if (!surf->meta_size) {
2322 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
2325 switch (surf->u.gfx9.swizzle_mode) {
2333 surf->micro_tile_mode = RADEON_MICRO_MODE_STANDARD;
2344 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
2360 surf->micro_tile_mode = RADEON_MICRO_MODE_RENDER;
2370 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
2382 struct radeon_surf *surf)
2386 r = surf_config_sanity(config, surf->flags);
2391 r = gfx9_compute_surface(addrlib, info, config, mode, surf);
2393 r = gfx6_compute_surface(addrlib->handle, info, config, mode, surf);
2399 surf->total_size = surf->surf_size;
2400 surf->alignment_log2 = surf->surf_alignment_log2;
2403 surf->meta_offset = surf->display_dcc_offset = surf->fmask_offset = surf->cmask_offset = 0;
2405 if (surf->fmask_size) {
2407 surf->fmask_offset = align64(surf->total_size, 1 << surf->fmask_alignment_log2);
2408 surf->total_size = surf->fmask_offset + surf->fmask_size;
2409 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->fmask_alignment_log2);
2413 if (surf->cmask_size && config->info.samples >= 2) {
2414 surf->cmask_offset = align64(surf->total_size, 1 << surf->cmask_alignment_log2);
2415 surf->total_size = surf->cmask_offset + surf->cmask_size;
2416 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->cmask_alignment_log2);
2419 if (surf->is_displayable)
2420 surf->flags |= RADEON_SURF_SCANOUT;
2422 if (surf->meta_size &&
2424 (info->chip_class >= GFX9 || !get_display_flag(config, surf))) {
2429 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
2430 surf->u.gfx9.color.dcc.display_equation_valid) {
2432 surf->display_dcc_offset = align64(surf->total_size, 1 << surf->u.gfx9.color.display_dcc_alignment_log2);
2433 surf->total_size = surf->display_dcc_offset + surf->u.gfx9.color.display_dcc_size;
2436 surf->meta_offset = align64(surf->total_size, 1 << surf->meta_alignment_log2);
2437 surf->total_size = surf->meta_offset + surf->meta_size;
2438 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->meta_alignment_log2);
2445 void ac_surface_zero_dcc_fields(struct radeon_surf *surf)
2447 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
2450 surf->meta_offset = 0;
2451 surf->display_dcc_offset = 0;
2452 if (!surf->fmask_offset && !surf->cmask_offset) {
2453 surf->total_size = surf->surf_size;
2454 surf->alignment_log2 = surf->surf_alignment_log2;
2512 void ac_surface_set_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2518 surf->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2519 surf->u.gfx9.color.dcc.independent_64B_blocks =
2521 surf->u.gfx9.color.dcc.independent_128B_blocks =
2523 surf->u.gfx9.color.dcc.max_compressed_block_size =
2525 surf->u.gfx9.color.display_dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX);
2528 surf->u.gfx9.swizzle_mode > 0 ? RADEON_SURF_MODE_2D : RADEON_SURF_MODE_LINEAR_ALIGNED;
2530 surf->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2531 surf->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2532 surf->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2533 surf->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
2534 surf->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2535 surf->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2547 surf->flags |= RADEON_SURF_SCANOUT;
2549 surf->flags &= ~RADEON_SURF_SCANOUT;
2552 void ac_surface_get_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2560 if (surf->meta_offset) {
2561 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->meta_offset;
2565 *tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, surf->u.gfx9.swizzle_mode);
2567 *tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, surf->u.gfx9.color.display_dcc_pitch_max);
2569 AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, surf->u.gfx9.color.dcc.independent_64B_blocks);
2571 AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, surf->u.gfx9.color.dcc.independent_128B_blocks);
2573 surf->u.gfx9.color.dcc.max_compressed_block_size);
2574 *tiling_flags |= AMDGPU_TILING_SET(SCANOUT, (surf->flags & RADEON_SURF_SCANOUT) != 0);
2576 if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D)
2578 else if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D)
2583 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, surf->u.legacy.pipe_config);
2584 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(surf->u.legacy.bankw));
2585 *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(surf->u.legacy.bankh));
2586 if (surf->u.legacy.tile_split)
2588 AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(surf->u.legacy.tile_split));
2589 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(surf->u.legacy.mtilea));
2590 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks) - 1);
2592 if (surf->flags & RADEON_SURF_SCANOUT)
2605 bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2612 if (surf->modifier != DRM_FORMAT_MOD_INVALID)
2616 offset = surf->u.gfx9.surf_offset;
2618 offset = (uint64_t)surf->u.legacy.level[0].offset_256B * 256;
2625 ac_surface_zero_dcc_fields(surf);
2661 surf->meta_offset = (uint64_t)desc[7] << 8;
2665 surf->meta_offset =
2667 surf->u.gfx9.color.dcc.pipe_aligned = G_008F24_META_PIPE_ALIGNED(desc[5]);
2668 surf->u.gfx9.color.dcc.rb_aligned = G_008F24_META_RB_ALIGNED(desc[5]);
2671 if (!surf->u.gfx9.color.dcc.pipe_aligned && !surf->u.gfx9.color.dcc.rb_aligned)
2672 assert(surf->is_displayable);
2677 surf->meta_offset =
2679 surf->u.gfx9.color.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]);
2690 ac_surface_zero_dcc_fields(surf);
2696 void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2709 desc[7] = surf->meta_offset >> 8;
2712 desc[7] = surf->meta_offset >> 8;
2714 desc[5] |= S_008F24_META_DATA_ADDRESS(surf->meta_offset >> 40);
2719 desc[6] |= S_00A018_META_DATA_ADDRESS_LO(surf->meta_offset >> 8);
2720 desc[7] = surf->meta_offset >> 16;
2748 metadata[10 + i] = surf->u.legacy.level[i].offset_256B;
2754 static uint32_t ac_surface_get_gfx9_pitch_align(struct radeon_surf *surf)
2756 if (surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR)
2757 return 256 / surf->bpe;
2759 if (surf->u.gfx9.resource_type == RADEON_RESOURCE_3D)
2762 unsigned bpe_shift = util_logbase2(surf->bpe) / 2;
2763 switch(surf->u.gfx9.swizzle_mode & ~3) {
2779 bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf,
2788 bool require_equal_pitch = surf->surf_size != surf->total_size ||
2794 if (surf->u.gfx9.surf_pitch != pitch && require_equal_pitch)
2797 if ((ac_surface_get_gfx9_pitch_align(surf) - 1) & pitch)
2800 if (pitch != surf->u.gfx9.surf_pitch) {
2801 unsigned slices = surf->surf_size / surf->u.gfx9.surf_slice_size;
2803 surf->u.gfx9.surf_pitch = pitch;
2804 surf->u.gfx9.epitch = pitch - 1;
2805 surf->u.gfx9.surf_slice_size = (uint64_t)pitch * surf->u.gfx9.surf_height * surf->bpe;
2806 surf->total_size = surf->surf_size = surf->u.gfx9.surf_slice_size * slices;
2809 surf->u.gfx9.surf_offset = offset;
2810 if (surf->u.gfx9.zs.stencil_offset)
2811 surf->u.gfx9.zs.stencil_offset += offset;
2814 if (surf->u.legacy.level[0].nblk_x != pitch && require_equal_pitch)
2817 surf->u.legacy.level[0].nblk_x = pitch;
2818 surf->u.legacy.level[0].slice_size_dw =
2819 ((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4;
2823 for (unsigned i = 0; i < ARRAY_SIZE(surf->u.legacy.level); ++i)
2824 surf->u.legacy.level[i].offset_256B += offset / 256;
2828 if (offset & ((1 << surf->alignment_log2) - 1) ||
2829 offset >= UINT64_MAX - surf->total_size)
2832 if (surf->meta_offset)
2833 surf->meta_offset += offset;
2834 if (surf->fmask_offset)
2835 surf->fmask_offset += offset;
2836 if (surf->cmask_offset)
2837 surf->cmask_offset += offset;
2838 if (surf->display_dcc_offset)
2839 surf->display_dcc_offset += offset;
2843 unsigned ac_surface_get_nplanes(const struct radeon_surf *surf)
2845 if (surf->modifier == DRM_FORMAT_MOD_INVALID)
2847 else if (surf->display_dcc_offset)
2849 else if (surf->meta_offset)
2856 const struct radeon_surf *surf,
2862 return surf->u.gfx9.surf_offset +
2863 layer * surf->u.gfx9.surf_slice_size;
2865 return (uint64_t)surf->u.legacy.level[0].offset_256B * 256 +
2866 layer * (uint64_t)surf->u.legacy.level[0].slice_size_dw * 4;
2870 return surf->display_dcc_offset ?
2871 surf->display_dcc_offset : surf->meta_offset;
2874 return surf->meta_offset;
2881 const struct radeon_surf *surf,
2887 return surf->u.gfx9.surf_pitch * surf->bpe;
2889 return surf->u.legacy.level[0].nblk_x * surf->bpe;
2892 return 1 + (surf->display_dcc_offset ?
2893 surf->u.gfx9.color.display_dcc_pitch_max : surf->u.gfx9.color.dcc_pitch_max);
2895 return surf->u.gfx9.color.dcc_pitch_max + 1;
2901 uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf,
2906 return surf->surf_size;
2908 return surf->display_dcc_offset ?
2909 surf->u.gfx9.color.display_dcc_size : surf->meta_size;
2911 return surf->meta_size;
2918 const struct radeon_surf *surf)
2925 surf->surf_size, surf->u.gfx9.surf_slice_size,
2926 1 << surf->surf_alignment_log2, surf->u.gfx9.swizzle_mode,
2927 surf->u.gfx9.epitch, surf->u.gfx9.surf_pitch,
2928 surf->blk_w, surf->blk_h, surf->bpe, surf->flags);
2930 if (surf->fmask_offset)
2934 surf->fmask_offset, surf->fmask_size,
2935 1 << surf->fmask_alignment_log2, surf->u.gfx9.color.fmask_swizzle_mode,
2936 surf->u.gfx9.color.fmask_epitch);
2938 if (surf->cmask_offset)
2942 surf->cmask_offset, surf->cmask_size,
2943 1 << surf->cmask_alignment_log2);
2945 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER && surf->meta_offset)
2948 surf->meta_offset, surf->meta_size,
2949 1 << surf->meta_alignment_log2);
2951 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->meta_offset)
2955 surf->meta_offset, surf->meta_size, 1 << surf->meta_alignment_log2,
2956 surf->u.gfx9.color.display_dcc_pitch_max, surf->num_meta_levels);
2958 if (surf->has_stencil)
2961 surf->u.gfx9.zs.stencil_offset,
2962 surf->u.gfx9.zs.stencil_swizzle_mode,
2963 surf->u.gfx9.zs.stencil_epitch);
2968 surf->surf_size, 1 << surf->surf_alignment_log2, surf->blk_w,
2969 surf->blk_h, surf->bpe, surf->flags);
2974 surf->surf_size, 1 << surf->surf_alignment_log2,
2975 surf->u.legacy.bankw, surf->u.legacy.bankh,
2976 surf->u.legacy.num_banks, surf->u.legacy.mtilea,
2977 surf->u.legacy.tile_split, surf->u.legacy.pipe_config,
2978 (surf->flags & RADEON_SURF_SCANOUT) != 0);
2980 if (surf->fmask_offset)
2985 surf->fmask_offset, surf->fmask_size,
2986 1 << surf->fmask_alignment_log2, surf->u.legacy.color.fmask.pitch_in_pixels,
2987 surf->u.legacy.color.fmask.bankh,
2988 surf->u.legacy.color.fmask.slice_tile_max,
2989 surf->u.legacy.color.fmask.tiling_index);
2991 if (surf->cmask_offset)
2995 surf->cmask_offset, surf->cmask_size,
2996 1 << surf->cmask_alignment_log2, surf->u.legacy.color.cmask_slice_tile_max);
2998 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER && surf->meta_offset)
3000 surf->meta_offset, surf->meta_size,
3001 1 << surf->meta_alignment_log2);
3003 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->meta_offset)
3005 surf->meta_offset, surf->meta_size, 1 << surf->meta_alignment_log2);
3007 if (surf->has_stencil)
3009 surf->u.legacy.stencil_tile_split);