Lines Matching refs:SMEM
59 ## SMEM stores
62 the offset for SMEM stores must be in m0 if IMM == 0.
64 The RDNA ISA doesn't mention SMEM stores at all, but they seem to be supported
68 ## SMEM atomics
70 RDNA ISA: same as the SMEM stores, the ISA pretends they don't exist, but they
176 ## SMEM corrupts VCCZ on SI/CI
180 After issuing a SMEM instructions, we need to wait for the SMEM instructions to
202 ### SMEM store followed by a load with the same address
208 SMEM stores, so it's not surprising that they didn't notice it.
214 Then, a SALU/SMEM instruction writes the same SGPR.
222 An SMEM instruction reads an SGPR. Then, a VALU instruction writes that same SGPR.