Lines Matching refs:but
49 All versions of the ISA document are vague about it, but after some trial and
61 The Vega ISA references doesn't say this (or doesn't make it clear), but
64 The RDNA ISA doesn't mention SMEM stores at all, but they seem to be supported
70 RDNA ISA: same as the SMEM stores, the ISA pretends they don't exist, but they
95 VEGA ISA doc says the encoding should be `110010` but `110101` works.
99 RDNA ISA doc says that `0x140` should be added to the opcode, but that doesn't
104 The NV bit was removed in RDNA, but some parts of the doc still mention it.
106 RDNA ISA doc 13.8.1 says that SADDR should be set to 0x7f when ADDR is used, but
114 mentions `V_MAC_LEGACY_F32` but this instruction is not really there on VEGA.
119 use the `m0` register for address clamping like older GPUs, but this is not the case.
145 The `s_dcache_wb` is not mentioned in the RDNA ISA doc, but it is needed in order
151 on what sort of addressing should be used, but it says that it
198 documented anywhere but AMD confirmed it.
207 This is not mentioned by LLVM among the other GFX10 bugs, but LLVM doesn't use