Lines Matching defs:enum_ref
11592 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
11593 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
11594 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
11595 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
11596 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
11597 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
11648 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
11649 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
11662 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
11663 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
11665 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
11666 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
11674 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
11675 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
11679 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"},
11705 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
11706 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
11755 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
11759 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
11770 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"},
11771 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"},
11772 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"},
11773 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"},
11774 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"},
11775 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"},
11776 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"},
11777 {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"},
11869 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11892 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
12477 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
12527 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
12528 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
12529 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
12695 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
12697 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
12698 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
12722 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"},
12785 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
12786 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
12787 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
12795 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
12800 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
12812 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
12821 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
12855 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"},
12856 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"},
12857 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"},
12858 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"},
12859 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"},
12860 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"},
12861 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"},
12871 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
12879 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
12889 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
12897 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
12926 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
12927 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
12928 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
12929 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
12930 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
12931 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
12936 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
12938 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12949 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
12952 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12981 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
12982 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
12983 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
12984 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
12989 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
12990 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
12991 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
12992 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
13484 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"}
13549 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
13552 {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
13553 {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
13560 {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"}
13601 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
13616 {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
13743 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
13744 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
13745 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
13746 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
13747 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
13748 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
13749 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
13750 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
13751 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
13752 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
13753 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
13754 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
13755 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
13756 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
13757 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
13762 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
13763 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
13764 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
13939 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
13940 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
13941 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
13968 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
13969 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
14011 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
14247 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
14248 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
14249 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
14250 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
14327 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
14328 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
14329 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
14330 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
14331 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
14332 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
14333 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
14334 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
14339 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"}
14357 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14371 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14388 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14404 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14417 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14432 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14449 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14458 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14471 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14486 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14498 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
14508 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14526 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14569 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
14570 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
14571 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
14572 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"},
14573 {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"}
14604 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
14642 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
14643 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
14644 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
14645 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
14646 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
14704 {"bits": [0, 11], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
14705 {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
14813 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14862 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
14905 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
14917 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
14918 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
14919 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
14920 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
14921 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
14922 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
14940 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
14941 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
14942 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
14943 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
14944 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
14945 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
14946 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
14947 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
14999 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
15000 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
15001 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
15002 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
15011 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
15012 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
15047 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
15064 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
15111 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
15113 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
15137 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
15138 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
15139 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
15140 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
15167 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
15202 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
15212 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
15213 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
15214 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
15215 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
15216 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
15274 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
15275 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
15276 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
15281 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
15282 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
15283 {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"},
15284 {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"},