Lines Matching refs:name
5 {"name": "ARRAY_LINEAR_GENERAL", "value": 0},
6 {"name": "ARRAY_LINEAR_ALIGNED", "value": 1},
7 {"name": "ARRAY_1D_TILED_THIN1", "value": 2},
8 {"name": "ARRAY_1D_TILED_THICK", "value": 3},
9 {"name": "ARRAY_2D_TILED_THIN1", "value": 4},
10 {"name": "ARRAY_PRT_TILED_THIN1", "value": 5},
11 {"name": "ARRAY_PRT_2D_TILED_THIN1", "value": 6},
12 {"name": "ARRAY_2D_TILED_THICK", "value": 7},
13 {"name": "ARRAY_2D_TILED_XTHICK", "value": 8},
14 {"name": "ARRAY_PRT_TILED_THICK", "value": 9},
15 {"name": "ARRAY_PRT_2D_TILED_THICK", "value": 10},
16 {"name": "ARRAY_PRT_3D_TILED_THIN1", "value": 11},
17 {"name": "ARRAY_3D_TILED_THIN1", "value": 12},
18 {"name": "ARRAY_3D_TILED_THICK", "value": 13},
19 {"name": "ARRAY_3D_TILED_XTHICK", "value": 14},
20 {"name": "ARRAY_PRT_3D_TILED_THICK", "value": 15}
25 {"name": "ADDR_SURF_BANK_HEIGHT_1", "value": 0},
26 {"name": "ADDR_SURF_BANK_HEIGHT_2", "value": 1},
27 {"name": "ADDR_SURF_BANK_HEIGHT_4", "value": 2},
28 {"name": "ADDR_SURF_BANK_HEIGHT_8", "value": 3}
33 {"name": "ADDR_SURF_BANK_WIDTH_1", "value": 0},
34 {"name": "ADDR_SURF_BANK_WIDTH_2", "value": 1},
35 {"name": "ADDR_SURF_BANK_WIDTH_4", "value": 2},
36 {"name": "ADDR_SURF_BANK_WIDTH_8", "value": 3}
41 {"name": "BIN_MAP_MODE_NONE", "value": 0},
42 {"name": "BIN_MAP_MODE_RTA_INDEX", "value": 1},
43 {"name": "BIN_MAP_MODE_POPS", "value": 2}
48 {"name": "BIN_SIZE_32_PIXELS", "value": 0},
49 {"name": "BIN_SIZE_64_PIXELS", "value": 1},
50 {"name": "BIN_SIZE_128_PIXELS", "value": 2},
51 {"name": "BIN_SIZE_256_PIXELS", "value": 3},
52 {"name": "BIN_SIZE_512_PIXELS", "value": 4}
57 {"name": "BINNING_ALLOWED", "value": 0},
58 {"name": "FORCE_BINNING_ON", "value": 1},
59 {"name": "DISABLE_BINNING_USE_NEW_SC", "value": 2},
60 {"name": "DISABLE_BINNING_USE_LEGACY_SC", "value": 3}
65 {"name": "BLEND_ZERO", "value": 0},
66 {"name": "BLEND_ONE", "value": 1},
67 {"name": "BLEND_SRC_COLOR", "value": 2},
68 {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},
69 {"name": "BLEND_SRC_ALPHA", "value": 4},
70 {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},
71 {"name": "BLEND_DST_ALPHA", "value": 6},
72 {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},
73 {"name": "BLEND_DST_COLOR", "value": 8},
74 {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},
75 {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},
76 {"name": "BLEND_BOTH_SRC_ALPHA", "value": 11},
77 {"name": "BLEND_BOTH_INV_SRC_ALPHA", "value": 12},
78 {"name": "BLEND_CONSTANT_COLOR", "value": 13},
79 {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 14},
80 {"name": "BLEND_SRC1_COLOR", "value": 15},
81 {"name": "BLEND_INV_SRC1_COLOR", "value": 16},
82 {"name": "BLEND_SRC1_ALPHA", "value": 17},
83 {"name": "BLEND_INV_SRC1_ALPHA", "value": 18},
84 {"name": "BLEND_CONSTANT_ALPHA", "value": 19},
85 {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 20}
90 {"name": "FORCE_OPT_AUTO", "value": 0},
91 {"name": "FORCE_OPT_DISABLE", "value": 1},
92 {"name": "FORCE_OPT_ENABLE_IF_SRC_A_0", "value": 2},
93 {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},
94 {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},
95 {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},
96 {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},
97 {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}
102 {"name": "CB_DISABLE", "value": 0},
103 {"name": "CB_NORMAL", "value": 1},
104 {"name": "CB_ELIMINATE_FAST_CLEAR", "value": 2},
105 {"name": "CB_RESOLVE", "value": 3},
106 {"name": "CB_DECOMPRESS", "value": 4},
107 {"name": "CB_FMASK_DECOMPRESS", "value": 5},
108 {"name": "CB_DCC_DECOMPRESS", "value": 6},
109 {"name": "CB_RESERVED", "value": 7}
114 {"name": "CB_PERF_CLEAR_FILTER_SEL_NONCLEAR", "value": 0},
115 {"name": "CB_PERF_CLEAR_FILTER_SEL_CLEAR", "value": 1}
120 {"name": "CB_PERF_OP_FILTER_SEL_WRITE_ONLY", "value": 0},
121 {"name": "CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION", "value": 1},
122 {"name": "CB_PERF_OP_FILTER_SEL_RESOLVE", "value": 2},
123 {"name": "CB_PERF_OP_FILTER_SEL_DECOMPRESS", "value": 3},
124 {"name": "CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS", "value": 4},
125 {"name": "CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR", "value": 5}
130 {"name": "MAX_BLOCK_SIZE_64B", "value": 0},
131 {"name": "MAX_BLOCK_SIZE_128B", "value": 1},
132 {"name": "MAX_BLOCK_SIZE_256B", "value": 2}
137 {"name": "MIN_BLOCK_SIZE_32B", "value": 0},
138 {"name": "MIN_BLOCK_SIZE_64B", "value": 1}
143 {"name": "OUT", "value": 1},
144 {"name": "IN_0", "value": 2},
145 {"name": "IN_1", "value": 4},
146 {"name": "IN_10", "value": 8},
147 {"name": "IN_2", "value": 16},
148 {"name": "IN_20", "value": 32},
149 {"name": "IN_21", "value": 64},
150 {"name": "IN_210", "value": 128},
151 {"name": "IN_3", "value": 256},
152 {"name": "IN_30", "value": 512},
153 {"name": "IN_31", "value": 1024},
154 {"name": "IN_310", "value": 2048},
155 {"name": "IN_32", "value": 4096},
156 {"name": "IN_320", "value": 8192},
157 {"name": "IN_321", "value": 16384},
158 {"name": "IN_3210", "value": 32768}
163 {"name": "CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT", "value": 0},
164 {"name": "CP_PERFMON_ENABLE_MODE_RESERVED_1", "value": 1},
165 {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},
166 {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE", "value": 3}
171 {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
172 {"name": "CP_PERFMON_STATE_START_COUNTING", "value": 1},
173 {"name": "CP_PERFMON_STATE_STOP_COUNTING", "value": 2},
174 {"name": "CP_PERFMON_STATE_RESERVED_3", "value": 3},
175 {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
176 {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
181 {"name": "CMASK_ADDR_TILED", "value": 0},
182 {"name": "CMASK_ADDR_LINEAR", "value": 1},
183 {"name": "CMASK_ADDR_COMPATIBLE", "value": 2}
188 {"name": "COLOR_INVALID", "value": 0},
189 {"name": "COLOR_8", "value": 1},
190 {"name": "COLOR_16", "value": 2},
191 {"name": "COLOR_8_8", "value": 3},
192 {"name": "COLOR_32", "value": 4},
193 {"name": "COLOR_16_16", "value": 5},
194 {"name": "COLOR_10_11_11", "value": 6},
195 {"name": "COLOR_11_11_10", "value": 7},
196 {"name": "COLOR_10_10_10_2", "value": 8},
197 {"name": "COLOR_2_10_10_10", "value": 9},
198 {"name": "COLOR_8_8_8_8", "value": 10},
199 {"name": "COLOR_32_32", "value": 11},
200 {"name": "COLOR_16_16_16_16", "value": 12},
201 {"name": "COLOR_RESERVED_13", "value": 13},
202 {"name": "COLOR_32_32_32_32", "value": 14},
203 {"name": "COLOR_RESERVED_15", "value": 15},
204 {"name": "COLOR_5_6_5", "value": 16},
205 {"name": "COLOR_1_5_5_5", "value": 17},
206 {"name": "COLOR_5_5_5_1", "value": 18},
207 {"name": "COLOR_4_4_4_4", "value": 19},
208 {"name": "COLOR_8_24", "value": 20},
209 {"name": "COLOR_24_8", "value": 21},
210 {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
211 {"name": "COLOR_RESERVED_23", "value": 23},
212 {"name": "COLOR_RESERVED_24", "value": 24},
213 {"name": "COLOR_RESERVED_25", "value": 25},
214 {"name": "COLOR_RESERVED_26", "value": 26},
215 {"name": "COLOR_RESERVED_27", "value": 27},
216 {"name": "COLOR_RESERVED_28", "value": 28},
217 {"name": "COLOR_RESERVED_29", "value": 29},
218 {"name": "COLOR_RESERVED_30", "value": 30},
219 {"name": "COLOR_2_10_10_10_6E4", "value": 31}
224 {"name": "COMB_DST_PLUS_SRC", "value": 0},
225 {"name": "COMB_SRC_MINUS_DST", "value": 1},
226 {"name": "COMB_MIN_DST_SRC", "value": 2},
227 {"name": "COMB_MAX_DST_SRC", "value": 3},
228 {"name": "COMB_DST_MINUS_SRC", "value": 4}
233 {"name": "FRAG_NEVER", "value": 0},
234 {"name": "FRAG_LESS", "value": 1},
235 {"name": "FRAG_EQUAL", "value": 2},
236 {"name": "FRAG_LEQUAL", "value": 3},
237 {"name": "FRAG_GREATER", "value": 4},
238 {"name": "FRAG_NOTEQUAL", "value": 5},
239 {"name": "FRAG_GEQUAL", "value": 6},
240 {"name": "FRAG_ALWAYS", "value": 7}
245 {"name": "EXPORT_ANY_Z", "value": 0},
246 {"name": "EXPORT_LESS_THAN_Z", "value": 1},
247 {"name": "EXPORT_GREATER_THAN_Z", "value": 2},
248 {"name": "EXPORT_RESERVED", "value": 3}
253 {"name": "INPUT_COVERAGE", "value": 0},
254 {"name": "INPUT_INNER_COVERAGE", "value": 1},
255 {"name": "INPUT_DEPTH_COVERAGE", "value": 2},
256 {"name": "RAW", "value": 3}
261 {"name": "AUTO", "value": 0},
262 {"name": "FORCE_ON", "value": 1},
263 {"name": "FORCE_OFF", "value": 2},
264 {"name": "RESERVED", "value": 3}
269 {"name": "FAULT_ZERO", "value": 0},
270 {"name": "FAULT_ONE", "value": 1},
271 {"name": "FAULT_FAIL", "value": 2},
272 {"name": "FAULT_PASS", "value": 3}
277 {"name": "PSLC_AUTO", "value": 0},
278 {"name": "PSLC_ON_HANG_ONLY", "value": 1},
279 {"name": "PSLC_ASAP", "value": 2},
280 {"name": "PSLC_COUNTDOWN", "value": 3}
285 {"name": "INVALID", "value": 1},
286 {"name": "INPUT_DENORMAL", "value": 2},
287 {"name": "DIVIDE_BY_ZERO", "value": 4},
288 {"name": "OVERFLOW", "value": 8},
289 {"name": "UNDERFLOW", "value": 16},
290 {"name": "INEXACT", "value": 32},
291 {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
292 {"name": "ADDRESS_WATCH", "value": 128},
293 {"name": "MEMORY_VIOLATION", "value": 256}
298 {"name": "FP_32_DENORMS", "value": 48},
299 {"name": "FP_64_DENORMS", "value": 192},
300 {"name": "FP_ALL_DENORMS", "value": 240}
305 {"name": "FORCE_OFF", "value": 0},
306 {"name": "FORCE_ENABLE", "value": 1},
307 {"name": "FORCE_DISABLE", "value": 2},
308 {"name": "FORCE_RESERVED", "value": 3}
313 {"name": "ADDR_SURF_MACRO_ASPECT_1", "value": 0},
314 {"name": "ADDR_SURF_MACRO_ASPECT_2", "value": 1},
315 {"name": "ADDR_SURF_MACRO_ASPECT_4", "value": 2},
316 {"name": "ADDR_SURF_MACRO_ASPECT_8", "value": 3}
321 {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0},
322 {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
323 {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
324 {"name": "ADDR_SURF_ROTATED_MICRO_TILING", "value": 3},
325 {"name": "ADDR_SURF_THICK_MICRO_TILING", "value": 4}
330 {"name": "ADDR_SURF_2_BANK", "value": 0},
331 {"name": "ADDR_SURF_4_BANK", "value": 1},
332 {"name": "ADDR_SURF_8_BANK", "value": 2},
333 {"name": "ADDR_SURF_16_BANK", "value": 3}
338 {"name": "X_DRAW_POINTS", "value": 0},
339 {"name": "X_DRAW_LINES", "value": 1},
340 {"name": "X_DRAW_TRIANGLES", "value": 2}
345 {"name": "X_DISABLE_POLY_MODE", "value": 0},
346 {"name": "X_DUAL_MODE", "value": 1}
351 {"name": "X_TRUNCATE", "value": 0},
352 {"name": "X_ROUND", "value": 1},
353 {"name": "X_ROUND_TO_EVEN", "value": 2},
354 {"name": "X_ROUND_TO_ODD", "value": 3}
359 {"name": "ADDR_SURF_P2", "value": 0},
360 {"name": "ADDR_SURF_P2_RESERVED0", "value": 1},
361 {"name": "ADDR_SURF_P2_RESERVED1", "value": 2},
362 {"name": "ADDR_SURF_P2_RESERVED2", "value": 3},
363 {"name": "ADDR_SURF_P4_8x16", "value": 4},
364 {"name": "ADDR_SURF_P4_16x16", "value": 5},
365 {"name": "ADDR_SURF_P4_16x32", "value": 6},
366 {"name": "ADDR_SURF_P4_32x32", "value": 7},
367 {"name": "ADDR_SURF_P8_16x16_8x16", "value": 8},
368 {"name": "ADDR_SURF_P8_16x32_8x16", "value": 9},
369 {"name": "ADDR_SURF_P8_32x32_8x16", "value": 10},
370 {"name": "ADDR_SURF_P8_16x32_16x16", "value": 11},
371 {"name": "ADDR_SURF_P8_32x32_16x16", "value": 12},
372 {"name": "ADDR_SURF_P8_32x32_16x32", "value": 13},
373 {"name": "ADDR_SURF_P8_32x64_32x32", "value": 14},
374 {"name": "ADDR_SURF_P8_RESERVED0", "value": 15},
375 {"name": "ADDR_SURF_P16_32x32_8x16", "value": 16},
376 {"name": "ADDR_SURF_P16_32x32_16x16", "value": 17},
377 {"name": "ADDR_SURF_P16", "value": 18}
382 {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
383 {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
384 {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
385 {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
390 {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
391 {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
392 {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
393 {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
398 {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
399 {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
400 {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
401 {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
406 {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
407 {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
408 {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
409 {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
414 {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
415 {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
416 {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
417 {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
418 {"name": "X_16_8_FIXED_POINT_1", "value": 4},
419 {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
420 {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
421 {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
426 {"name": "ROP3_CLEAR", "value": 0},
427 {"name": "X_0X05", "value": 5},
428 {"name": "X_0X0A", "value": 10},
429 {"name": "X_0X0F", "value": 15},
430 {"name": "ROP3_NOR", "value": 17},
431 {"name": "ROP3_AND_INVERTED", "value": 34},
432 {"name": "ROP3_COPY_INVERTED", "value": 51},
433 {"name": "ROP3_AND_REVERSE", "value": 68},
434 {"name": "X_0X50", "value": 80},
435 {"name": "ROP3_INVERT", "value": 85},
436 {"name": "X_0X5A", "value": 90},
437 {"name": "X_0X5F", "value": 95},
438 {"name": "ROP3_XOR", "value": 102},
439 {"name": "ROP3_NAND", "value": 119},
440 {"name": "ROP3_AND", "value": 136},
441 {"name": "ROP3_EQUIVALENT", "value": 153},
442 {"name": "X_0XA0", "value": 160},
443 {"name": "X_0XA5", "value": 165},
444 {"name": "ROP3_NO_OP", "value": 170},
445 {"name": "X_0XAF", "value": 175},
446 {"name": "ROP3_OR_INVERTED", "value": 187},
447 {"name": "ROP3_COPY", "value": 204},
448 {"name": "ROP3_OR_REVERSE", "value": 221},
449 {"name": "ROP3_OR", "value": 238},
450 {"name": "X_0XF0", "value": 240},
451 {"name": "X_0XF5", "value": 245},
452 {"name": "X_0XFA", "value": 250},
453 {"name": "ROP3_SET", "value": 255}
458 {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
459 {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
460 {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
461 {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
466 {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
467 {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
472 {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
473 {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
474 {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
475 {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
480 {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
481 {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
486 {"name": "CACHE_LRU_RD", "value": 0},
487 {"name": "CACHE_NOA", "value": 1},
488 {"name": "UNCACHED_RD", "value": 2},
489 {"name": "RESERVED_RDPOLICY", "value": 3}
494 {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
495 {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
496 {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
497 {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
498 {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
503 {"name": "SPI_SHADER_ZERO", "value": 0},
504 {"name": "SPI_SHADER_32_R", "value": 1},
505 {"name": "SPI_SHADER_32_GR", "value": 2},
506 {"name": "SPI_SHADER_32_AR", "value": 3},
507 {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
508 {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
509 {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
510 {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
511 {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
512 {"name": "SPI_SHADER_32_ABGR", "value": 9}
517 {"name": "SPI_SHADER_NONE", "value": 0},
518 {"name": "SPI_SHADER_1COMP", "value": 1},
519 {"name": "SPI_SHADER_2COMP", "value": 2},
520 {"name": "SPI_SHADER_4COMPRESS", "value": 3},
521 {"name": "SPI_SHADER_4COMP", "value": 4}
526 {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
527 {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
528 {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
529 {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
530 {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
531 {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
536 {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
537 {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
538 {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
539 {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
540 {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
541 {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
542 {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
543 {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
548 {"name": "EXACT", "value": 0},
549 {"name": "11BIT_FORMAT", "value": 1},
550 {"name": "10BIT_FORMAT", "value": 3},
551 {"name": "8BIT_FORMAT", "value": 6},
552 {"name": "6BIT_FORMAT", "value": 11},
553 {"name": "5BIT_FORMAT", "value": 13},
554 {"name": "4BIT_FORMAT", "value": 15}
559 {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
560 {"name": "SX_RT_EXPORT_32_R", "value": 1},
561 {"name": "SX_RT_EXPORT_32_A", "value": 2},
562 {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
563 {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
564 {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
565 {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
566 {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
567 {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
568 {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
569 {"name": "SX_RT_EXPORT_16_16_AR", "value": 10}
574 {"name": "OPT_COMB_NONE", "value": 0},
575 {"name": "OPT_COMB_ADD", "value": 1},
576 {"name": "OPT_COMB_SUBTRACT", "value": 2},
577 {"name": "OPT_COMB_MIN", "value": 3},
578 {"name": "OPT_COMB_MAX", "value": 4},
579 {"name": "OPT_COMB_REVSUBTRACT", "value": 5},
580 {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},
581 {"name": "OPT_COMB_SAFE_ADD", "value": 7}
586 {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
587 {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
588 {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
589 {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
594 {"name": "SC_HALF_LSB", "value": 0},
595 {"name": "SC_LSB_ONE_SIDED", "value": 1},
596 {"name": "SC_LSB_TWO_SIDED", "value": 2}
601 {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
602 {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
603 {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
604 {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
609 {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
610 {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
611 {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
612 {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
617 {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
618 {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
619 {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
620 {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
625 {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},
626 {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},
627 {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},
628 {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}
633 {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},
634 {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
635 {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},
636 {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}
641 {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},
642 {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},
643 {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},
644 {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}
649 {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
650 {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
651 {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
652 {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
657 {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
658 {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
659 {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
660 {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
665 {"name": "STENCIL_INVALID", "value": 0},
666 {"name": "STENCIL_8", "value": 1}
671 {"name": "STENCIL_KEEP", "value": 0},
672 {"name": "STENCIL_ZERO", "value": 1},
673 {"name": "STENCIL_ONES", "value": 2},
674 {"name": "STENCIL_REPLACE_TEST", "value": 3},
675 {"name": "STENCIL_REPLACE_OP", "value": 4},
676 {"name": "STENCIL_ADD_CLAMP", "value": 5},
677 {"name": "STENCIL_SUB_CLAMP", "value": 6},
678 {"name": "STENCIL_INVERT", "value": 7},
679 {"name": "STENCIL_ADD_WRAP", "value": 8},
680 {"name": "STENCIL_SUB_WRAP", "value": 9},
681 {"name": "STENCIL_AND", "value": 10},
682 {"name": "STENCIL_OR", "value": 11},
683 {"name": "STENCIL_XOR", "value": 12},
684 {"name": "STENCIL_NAND", "value": 13},
685 {"name": "STENCIL_NOR", "value": 14},
686 {"name": "STENCIL_XNOR", "value": 15}
691 {"name": "ENDIAN_NONE", "value": 0},
692 {"name": "ENDIAN_8IN16", "value": 1},
693 {"name": "ENDIAN_8IN32", "value": 2},
694 {"name": "ENDIAN_8IN64", "value": 3}
699 {"name": "NUMBER_UNORM", "value": 0},
700 {"name": "NUMBER_SNORM", "value": 1},
701 {"name": "NUMBER_USCALED", "value": 2},
702 {"name": "NUMBER_SSCALED", "value": 3},
703 {"name": "NUMBER_UINT", "value": 4},
704 {"name": "NUMBER_SINT", "value": 5},
705 {"name": "NUMBER_SRGB", "value": 6},
706 {"name": "NUMBER_FLOAT", "value": 7}
711 {"name": "SWAP_STD", "value": 0},
712 {"name": "SWAP_ALT", "value": 1},
713 {"name": "SWAP_STD_REV", "value": 2},
714 {"name": "SWAP_ALT_REV", "value": 3}
719 {"name": "REG_INCLUDE_SQDEC", "value": 1},
720 {"name": "REG_INCLUDE_SHDEC", "value": 2},
721 {"name": "REG_INCLUDE_GFXUDEC", "value": 4},
722 {"name": "REG_INCLUDE_COMP", "value": 8},
723 {"name": "REG_INCLUDE_CONTEXT", "value": 16},
724 {"name": "REG_INCLUDE_CONFIG", "value": 32},
725 {"name": "REG_INCLUDE_OTHER", "value": 64},
726 {"name": "REG_INCLUDE_READS", "value": 128}
731 {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1},
732 {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2},
733 {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4},
734 {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8},
735 {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16},
736 {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32},
737 {"name": "TOKEN_EXCLUDE_REG", "value": 64},
738 {"name": "TOKEN_EXCLUDE_EVENT", "value": 128},
739 {"name": "TOKEN_EXCLUDE_INST", "value": 256},
740 {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512},
741 {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024},
742 {"name": "TOKEN_EXCLUDE_PERF", "value": 2048}
747 {"name": "ADDR_SURF_TILE_SPLIT_64B", "value": 0},
748 {"name": "ADDR_SURF_TILE_SPLIT_128B", "value": 1},
749 {"name": "ADDR_SURF_TILE_SPLIT_256B", "value": 2},
750 {"name": "ADDR_SURF_TILE_SPLIT_512B", "value": 3},
751 {"name": "ADDR_SURF_TILE_SPLIT_1KB", "value": 4},
752 {"name": "ADDR_SURF_TILE_SPLIT_2KB", "value": 5},
753 {"name": "ADDR_SURF_TILE_SPLIT_4KB", "value": 6}
758 {"name": "PRE_CLAMP_TF1", "value": 0},
759 {"name": "POST_CLAMP_TF1", "value": 1},
760 {"name": "DISABLE_TF1", "value": 2}
765 {"name": "PRE_CLAMP_TF0", "value": 0},
766 {"name": "POST_CLAMP_TF0", "value": 1},
767 {"name": "DISABLE_TF0", "value": 2}
772 {"name": "NO_DIST", "value": 0},
773 {"name": "PATCHES", "value": 1},
774 {"name": "DONUTS", "value": 2},
775 {"name": "TRAPEZOIDS", "value": 3}
780 {"name": "DI_MAJOR_MODE_0", "value": 0},
781 {"name": "DI_MAJOR_MODE_1", "value": 1}
786 {"name": "DI_PT_NONE", "value": 0},
787 {"name": "DI_PT_POINTLIST", "value": 1},
788 {"name": "DI_PT_LINELIST", "value": 2},
789 {"name": "DI_PT_LINESTRIP", "value": 3},
790 {"name": "DI_PT_TRILIST", "value": 4},
791 {"name": "DI_PT_TRIFAN", "value": 5},
792 {"name": "DI_PT_TRISTRIP", "value": 6},
793 {"name": "DI_PT_2D_RECTANGLE", "value": 7},
794 {"name": "DI_PT_UNUSED_1", "value": 8},
795 {"name": "DI_PT_PATCH", "value": 9},
796 {"name": "DI_PT_LINELIST_ADJ", "value": 10},
797 {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
798 {"name": "DI_PT_TRILIST_ADJ", "value": 12},
799 {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
800 {"name": "DI_PT_UNUSED_3", "value": 14},
801 {"name": "DI_PT_UNUSED_4", "value": 15},
802 {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
803 {"name": "DI_PT_RECTLIST", "value": 17},
804 {"name": "DI_PT_LINELOOP", "value": 18},
805 {"name": "DI_PT_QUADLIST", "value": 19},
806 {"name": "DI_PT_QUADSTRIP", "value": 20},
807 {"name": "DI_PT_POLYGON", "value": 21}
812 {"name": "DI_SRC_SEL_DMA", "value": 0},
813 {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
814 {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
815 {"name": "DI_SRC_SEL_RESERVED", "value": 3}
820 {"name": "VGT_DMA_BUF_MEM", "value": 0},
821 {"name": "VGT_DMA_BUF_RING", "value": 1},
822 {"name": "VGT_DMA_BUF_SETUP", "value": 2},
823 {"name": "VGT_DMA_PTR_UPDATE", "value": 3}
828 {"name": "VGT_DMA_SWAP_NONE", "value": 0},
829 {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
830 {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
831 {"name": "VGT_DMA_SWAP_WORD", "value": 3}
836 {"name": "Reserved_0x00", "value": 0},
837 {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
838 {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
839 {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
840 {"name": "CACHE_FLUSH_TS", "value": 4},
841 {"name": "CONTEXT_DONE", "value": 5},
842 {"name": "CACHE_FLUSH", "value": 6},
843 {"name": "CS_PARTIAL_FLUSH", "value": 7},
844 {"name": "VGT_STREAMOUT_SYNC", "value": 8},
845 {"name": "SET_FE_ID", "value": 9},
846 {"name": "VGT_STREAMOUT_RESET", "value": 10},
847 {"name": "END_OF_PIPE_INCR_DE", "value": 11},
848 {"name": "END_OF_PIPE_IB_END", "value": 12},
849 {"name": "RST_PIX_CNT", "value": 13},
850 {"name": "BREAK_BATCH", "value": 14},
851 {"name": "VS_PARTIAL_FLUSH", "value": 15},
852 {"name": "PS_PARTIAL_FLUSH", "value": 16},
853 {"name": "FLUSH_HS_OUTPUT", "value": 17},
854 {"name": "FLUSH_DFSM", "value": 18},
855 {"name": "RESET_TO_LOWEST_VGT", "value": 19},
856 {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
857 {"name": "ZPASS_DONE", "value": 21},
858 {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
859 {"name": "PERFCOUNTER_START", "value": 23},
860 {"name": "PERFCOUNTER_STOP", "value": 24},
861 {"name": "PIPELINESTAT_START", "value": 25},
862 {"name": "PIPELINESTAT_STOP", "value": 26},
863 {"name": "PERFCOUNTER_SAMPLE", "value": 27},
864 {"name": "FLUSH_ES_OUTPUT", "value": 28},
865 {"name": "BIN_CONF_OVERRIDE_CHECK", "value": 29},
866 {"name": "SAMPLE_PIPELINESTAT", "value": 30},
867 {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
868 {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
869 {"name": "RESET_VTX_CNT", "value": 33},
870 {"name": "BLOCK_CONTEXT_DONE", "value": 34},
871 {"name": "CS_CONTEXT_DONE", "value": 35},
872 {"name": "VGT_FLUSH", "value": 36},
873 {"name": "TGID_ROLLOVER", "value": 37},
874 {"name": "SQ_NON_EVENT", "value": 38},
875 {"name": "SC_SEND_DB_VPZ", "value": 39},
876 {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
877 {"name": "FLUSH_SX_TS", "value": 41},
878 {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
879 {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
880 {"name": "FLUSH_AND_INV_DB_META", "value": 44},
881 {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
882 {"name": "FLUSH_AND_INV_CB_META", "value": 46},
883 {"name": "CS_DONE", "value": 47},
884 {"name": "PS_DONE", "value": 48},
885 {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
886 {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
887 {"name": "THREAD_TRACE_START", "value": 51},
888 {"name": "THREAD_TRACE_STOP", "value": 52},
889 {"name": "THREAD_TRACE_MARKER", "value": 53},
890 {"name": "THREAD_TRACE_DRAW", "value": 54},
891 {"name": "THREAD_TRACE_FINISH", "value": 55},
892 {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
893 {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
894 {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
895 {"name": "CONTEXT_SUSPEND", "value": 59},
896 {"name": "OFFCHIP_HS_DEALLOC", "value": 60},
897 {"name": "ENABLE_NGG_PIPELINE", "value": 61},
898 {"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
899 {"name": "DRAW_DONE", "value": 63}
904 {"name": "GS_CUT_1024", "value": 0},
905 {"name": "GS_CUT_512", "value": 1},
906 {"name": "GS_CUT_256", "value": 2},
907 {"name": "GS_CUT_128", "value": 3}
912 {"name": "GS_OFF", "value": 0},
913 {"name": "GS_SCENARIO_A", "value": 1},
914 {"name": "GS_SCENARIO_B", "value": 2},
915 {"name": "GS_SCENARIO_G", "value": 3},
916 {"name": "GS_SCENARIO_C", "value": 4},
917 {"name": "SPRITE_EN", "value": 5}
922 {"name": "POINTLIST", "value": 0},
923 {"name": "LINESTRIP", "value": 1},
924 {"name": "TRISTRIP", "value": 2},
925 {"name": "RECTLIST", "value": 3}
930 {"name": "X_8K_DWORDS", "value": 0},
931 {"name": "X_4K_DWORDS", "value": 1},
932 {"name": "X_2K_DWORDS", "value": 2},
933 {"name": "X_1K_DWORDS", "value": 3}
938 {"name": "VGT_INDEX_16", "value": 0},
939 {"name": "VGT_INDEX_32", "value": 1},
940 {"name": "VGT_INDEX_8", "value": 2}
945 {"name": "VGT_POLICY_LRU", "value": 0},
946 {"name": "VGT_POLICY_STREAM", "value": 1},
947 {"name": "VGT_POLICY_BYPASS", "value": 2}
952 {"name": "ES_STAGE_OFF", "value": 0},
953 {"name": "ES_STAGE_DS", "value": 1},
954 {"name": "ES_STAGE_REAL", "value": 2},
955 {"name": "RESERVED_ES", "value": 3}
960 {"name": "GS_STAGE_OFF", "value": 0},
961 {"name": "GS_STAGE_ON", "value": 1}
966 {"name": "HS_STAGE_OFF", "value": 0},
967 {"name": "HS_STAGE_ON", "value": 1}
972 {"name": "LS_STAGE_OFF", "value": 0},
973 {"name": "LS_STAGE_ON", "value": 1},
974 {"name": "CS_STAGE_ON", "value": 2},
975 {"name": "RESERVED_LS", "value": 3}
980 {"name": "VS_STAGE_REAL", "value": 0},
981 {"name": "VS_STAGE_DS", "value": 1},
982 {"name": "VS_STAGE_COPY_SHADER", "value": 2},
983 {"name": "RESERVED_VS", "value": 3}
988 {"name": "PART_INTEGER", "value": 0},
989 {"name": "PART_POW2", "value": 1},
990 {"name": "PART_FRAC_ODD", "value": 2},
991 {"name": "PART_FRAC_EVEN", "value": 3}
996 {"name": "OUTPUT_POINT", "value": 0},
997 {"name": "OUTPUT_LINE", "value": 1},
998 {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
999 {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
1004 {"name": "TESS_ISOLINE", "value": 0},
1005 {"name": "TESS_TRIANGLE", "value": 1},
1006 {"name": "TESS_QUAD", "value": 2}
1011 {"name": "CACHE_LRU_WR", "value": 0},
1012 {"name": "CACHE_STREAM", "value": 1},
1013 {"name": "CACHE_BYPASS", "value": 2},
1014 {"name": "UNCACHED_WR", "value": 3}
1019 {"name": "Z_INVALID", "value": 0},
1020 {"name": "Z_16", "value": 1},
1021 {"name": "Z_24", "value": 2},
1022 {"name": "Z_32_FLOAT", "value": 3}
1027 {"name": "FORCE_SUMM_OFF", "value": 0},
1028 {"name": "FORCE_SUMM_MINZ", "value": 1},
1029 {"name": "FORCE_SUMM_MAXZ", "value": 2},
1030 {"name": "FORCE_SUMM_BOTH", "value": 3}
1035 {"name": "LATE_Z", "value": 0},
1036 {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
1037 {"name": "RE_Z", "value": 2},
1038 {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
1046 "name": "SQ_WAVE_MODE",
1052 "name": "SQ_WAVE_STATUS",
1058 "name": "SQ_WAVE_TRAPSTS",
1064 "name": "SQ_WAVE_HW_ID_LEGACY",
1070 "name": "SQ_WAVE_GPR_ALLOC",
1076 "name": "SQ_WAVE_LDS_ALLOC",
1082 "name": "SQ_WAVE_IB_STS",
1088 "name": "SQ_WAVE_PC_LO"
1093 "name": "SQ_WAVE_PC_HI",
1099 "name": "SQ_WAVE_INST_DW0"
1104 "name": "SQ_WAVE_IB_DBG1",
1110 "name": "SQ_WAVE_FLUSH_IB"
1115 "name": "SQ_WAVE_HW_ID1",
1121 "name": "SQ_WAVE_HW_ID2",
1127 "name": "SQ_WAVE_POPS_PACKER",
1133 "name": "SQ_WAVE_SCHED_MODE",
1139 "name": "SQ_WAVE_VGPR_OFFSET",
1145 "name": "SQ_WAVE_IB_STS2",
1151 "name": "SQ_WAVE_TTMP0"
1156 "name": "SQ_WAVE_TTMP1"
1161 "name": "SQ_WAVE_TTMP2"
1166 "name": "SQ_WAVE_TTMP3"
1171 "name": "SQ_WAVE_TTMP4"
1176 "name": "SQ_WAVE_TTMP5"
1181 "name": "SQ_WAVE_TTMP6"
1186 "name": "SQ_WAVE_TTMP7"
1191 "name": "SQ_WAVE_TTMP8"
1196 "name": "SQ_WAVE_TTMP9"
1201 "name": "SQ_WAVE_TTMP10"
1206 "name": "SQ_WAVE_TTMP11"
1211 "name": "SQ_WAVE_TTMP12"
1216 "name": "SQ_WAVE_TTMP13"
1221 "name": "SQ_WAVE_TTMP14"
1226 "name": "SQ_WAVE_TTMP15"
1231 "name": "SQ_WAVE_M0"
1236 "name": "SQ_WAVE_EXEC_LO"
1241 "name": "SQ_WAVE_EXEC_HI"
1246 "name": "SQ_WAVE_FLAT_SCRATCH_LO"
1251 "name": "SQ_WAVE_FLAT_SCRATCH_HI"
1256 "name": "SQ_WAVE_FLAT_XNACK_MASK"
1261 "name": "GRBM_STATUS2",
1267 "name": "GRBM_STATUS",
1273 "name": "GRBM_STATUS_SE0",
1279 "name": "GRBM_STATUS_SE1",
1285 "name": "GRBM_STATUS3",
1291 "name": "GRBM_STATUS_SE2",
1297 "name": "GRBM_STATUS_SE3",
1303 "name": "CP_CPC_STATUS",
1309 "name": "CP_CPC_BUSY_STAT",
1315 "name": "CP_CPC_STALLED_STAT1",
1321 "name": "CP_CPF_STATUS",
1327 "name": "CP_CPF_BUSY_STAT",
1333 "name": "CP_CPF_STALLED_STAT1",
1339 "name": "CP_CPC_BUSY_STAT2",
1345 "name": "CP_CPC_GRBM_FREE_COUNT",
1351 "name": "CP_CPC_SCRATCH_INDEX",
1357 "name": "CP_CPC_SCRATCH_DATA"
1362 "name": "CP_CPF_GRBM_FREE_COUNT",
1368 "name": "CP_CPF_BUSY_STAT2",
1374 "name": "CP_CPC_HALT_HYST_COUNT",
1380 "name": "SQ_THREAD_TRACE_BUF0_BASE"
1385 "name": "SQ_THREAD_TRACE_BUF0_SIZE",
1391 "name": "SQ_THREAD_TRACE_BUF1_BASE"
1396 "name": "SQ_THREAD_TRACE_BUF1_SIZE",
1402 "name": "SQ_THREAD_TRACE_WPTR",
1408 "name": "SQ_THREAD_TRACE_MASK",
1414 "name": "SQ_THREAD_TRACE_TOKEN_MASK",
1420 "name": "SQ_THREAD_TRACE_CTRL",
1426 "name": "SQ_THREAD_TRACE_STATUS",
1432 "name": "SQ_THREAD_TRACE_DROPPED_CNTR"
1437 "name": "SQ_THREAD_TRACE_GFX_DRAW_CNTR"
1442 "name": "SQ_THREAD_TRACE_GFX_MARKER_CNTR"
1447 "name": "SQ_THREAD_TRACE_HP3D_DRAW_CNTR"
1452 "name": "SQ_THREAD_TRACE_HP3D_MARKER_CNTR"
1457 "name": "SPI_CONFIG_CNTL",
1463 "name": "GB_ADDR_CONFIG",
1469 "name": "GB_TILE_MODE0",
1475 "name": "GB_TILE_MODE1",
1481 "name": "GB_TILE_MODE2",
1487 "name": "GB_TILE_MODE3",
1493 "name": "GB_TILE_MODE4",
1499 "name": "GB_TILE_MODE5",
1505 "name": "GB_TILE_MODE6",
1511 "name": "GB_TILE_MODE7",
1517 "name": "GB_TILE_MODE8",
1523 "name": "GB_TILE_MODE9",
1529 "name": "GB_TILE_MODE10",
1535 "name": "GB_TILE_MODE11",
1541 "name": "GB_TILE_MODE12",
1547 "name": "GB_TILE_MODE13",
1553 "name": "GB_TILE_MODE14",
1559 "name": "GB_TILE_MODE15",
1565 "name": "GB_TILE_MODE16",
1571 "name": "GB_TILE_MODE17",
1577 "name": "GB_TILE_MODE18",
1583 "name": "GB_TILE_MODE19",
1589 "name": "GB_TILE_MODE20",
1595 "name": "GB_TILE_MODE21",
1601 "name": "GB_TILE_MODE22",
1607 "name": "GB_TILE_MODE23",
1613 "name": "GB_TILE_MODE24",
1619 "name": "GB_TILE_MODE25",
1625 "name": "GB_TILE_MODE26",
1631 "name": "GB_TILE_MODE27",
1637 "name": "GB_TILE_MODE28",
1643 "name": "GB_TILE_MODE29",
1649 "name": "GB_TILE_MODE30",
1655 "name": "GB_TILE_MODE31",
1661 "name": "GB_MACROTILE_MODE0",
1667 "name": "GB_MACROTILE_MODE1",
1673 "name": "GB_MACROTILE_MODE2",
1679 "name": "GB_MACROTILE_MODE3",
1685 "name": "GB_MACROTILE_MODE4",
1691 "name": "GB_MACROTILE_MODE5",
1697 "name": "GB_MACROTILE_MODE6",
1703 "name": "GB_MACROTILE_MODE7",
1709 "name": "GB_MACROTILE_MODE8",
1715 "name": "GB_MACROTILE_MODE9",
1721 "name": "GB_MACROTILE_MODE10",
1727 "name": "GB_MACROTILE_MODE11",
1733 "name": "GB_MACROTILE_MODE12",
1739 "name": "GB_MACROTILE_MODE13",
1745 "name": "GB_MACROTILE_MODE14",
1751 "name": "GB_MACROTILE_MODE15",
1757 "name": "SPI_SHADER_PGM_RSRC4_PS",
1763 "name": "SPI_SHADER_PGM_CHKSUM_PS"
1768 "name": "SPI_SHADER_PGM_RSRC3_PS",
1774 "name": "SPI_SHADER_PGM_LO_PS"
1779 "name": "SPI_SHADER_PGM_HI_PS",
1785 "name": "SPI_SHADER_PGM_RSRC1_PS",
1791 "name": "SPI_SHADER_PGM_RSRC2_PS",
1797 "name": "SPI_SHADER_USER_DATA_PS_0"
1802 "name": "SPI_SHADER_USER_DATA_PS_1"
1807 "name": "SPI_SHADER_USER_DATA_PS_2"
1812 "name": "SPI_SHADER_USER_DATA_PS_3"
1817 "name": "SPI_SHADER_USER_DATA_PS_4"
1822 "name": "SPI_SHADER_USER_DATA_PS_5"
1827 "name": "SPI_SHADER_USER_DATA_PS_6"
1832 "name": "SPI_SHADER_USER_DATA_PS_7"
1837 "name": "SPI_SHADER_USER_DATA_PS_8"
1842 "name": "SPI_SHADER_USER_DATA_PS_9"
1847 "name": "SPI_SHADER_USER_DATA_PS_10"
1852 "name": "SPI_SHADER_USER_DATA_PS_11"
1857 "name": "SPI_SHADER_USER_DATA_PS_12"
1862 "name": "SPI_SHADER_USER_DATA_PS_13"
1867 "name": "SPI_SHADER_USER_DATA_PS_14"
1872 "name": "SPI_SHADER_USER_DATA_PS_15"
1877 "name": "SPI_SHADER_USER_DATA_PS_16"
1882 "name": "SPI_SHADER_USER_DATA_PS_17"
1887 "name": "SPI_SHADER_USER_DATA_PS_18"
1892 "name": "SPI_SHADER_USER_DATA_PS_19"
1897 "name": "SPI_SHADER_USER_DATA_PS_20"
1902 "name": "SPI_SHADER_USER_DATA_PS_21"
1907 "name": "SPI_SHADER_USER_DATA_PS_22"
1912 "name": "SPI_SHADER_USER_DATA_PS_23"
1917 "name": "SPI_SHADER_USER_DATA_PS_24"
1922 "name": "SPI_SHADER_USER_DATA_PS_25"
1927 "name": "SPI_SHADER_USER_DATA_PS_26"
1932 "name": "SPI_SHADER_USER_DATA_PS_27"
1937 "name": "SPI_SHADER_USER_DATA_PS_28"
1942 "name": "SPI_SHADER_USER_DATA_PS_29"
1947 "name": "SPI_SHADER_USER_DATA_PS_30"
1952 "name": "SPI_SHADER_USER_DATA_PS_31"
1957 "name": "SPI_SHADER_REQ_CTRL_PS",
1963 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS",
1969 "name": "SPI_SHADER_USER_ACCUM_PS_0",
1975 "name": "SPI_SHADER_USER_ACCUM_PS_1",
1981 "name": "SPI_SHADER_USER_ACCUM_PS_2",
1987 "name": "SPI_SHADER_USER_ACCUM_PS_3",
1993 "name": "SPI_SHADER_PGM_RSRC4_VS",
1999 "name": "SPI_SHADER_PGM_CHKSUM_VS"
2004 "name": "SPI_SHADER_PGM_RSRC3_VS",
2010 "name": "SPI_SHADER_LATE_ALLOC_VS",
2016 "name": "SPI_SHADER_PGM_LO_VS"
2021 "name": "SPI_SHADER_PGM_HI_VS",
2027 "name": "SPI_SHADER_PGM_RSRC1_VS",
2033 "name": "SPI_SHADER_PGM_RSRC2_VS",
2039 "name": "SPI_SHADER_USER_DATA_VS_0"
2044 "name": "SPI_SHADER_USER_DATA_VS_1"
2049 "name": "SPI_SHADER_USER_DATA_VS_2"
2054 "name": "SPI_SHADER_USER_DATA_VS_3"
2059 "name": "SPI_SHADER_USER_DATA_VS_4"
2064 "name": "SPI_SHADER_USER_DATA_VS_5"
2069 "name": "SPI_SHADER_USER_DATA_VS_6"
2074 "name": "SPI_SHADER_USER_DATA_VS_7"
2079 "name": "SPI_SHADER_USER_DATA_VS_8"
2084 "name": "SPI_SHADER_USER_DATA_VS_9"
2089 "name": "SPI_SHADER_USER_DATA_VS_10"
2094 "name": "SPI_SHADER_USER_DATA_VS_11"
2099 "name": "SPI_SHADER_USER_DATA_VS_12"
2104 "name": "SPI_SHADER_USER_DATA_VS_13"
2109 "name": "SPI_SHADER_USER_DATA_VS_14"
2114 "name": "SPI_SHADER_USER_DATA_VS_15"
2119 "name": "SPI_SHADER_USER_DATA_VS_16"
2124 "name": "SPI_SHADER_USER_DATA_VS_17"
2129 "name": "SPI_SHADER_USER_DATA_VS_18"
2134 "name": "SPI_SHADER_USER_DATA_VS_19"
2139 "name": "SPI_SHADER_USER_DATA_VS_20"
2144 "name": "SPI_SHADER_USER_DATA_VS_21"
2149 "name": "SPI_SHADER_USER_DATA_VS_22"
2154 "name": "SPI_SHADER_USER_DATA_VS_23"
2159 "name": "SPI_SHADER_USER_DATA_VS_24"
2164 "name": "SPI_SHADER_USER_DATA_VS_25"
2169 "name": "SPI_SHADER_USER_DATA_VS_26"
2174 "name": "SPI_SHADER_USER_DATA_VS_27"
2179 "name": "SPI_SHADER_USER_DATA_VS_28"
2184 "name": "SPI_SHADER_USER_DATA_VS_29"
2189 "name": "SPI_SHADER_USER_DATA_VS_30"
2194 "name": "SPI_SHADER_USER_DATA_VS_31"
2199 "name": "SPI_SHADER_REQ_CTRL_VS",
2205 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_VS",
2211 "name": "SPI_SHADER_USER_ACCUM_VS_0",
2217 "name": "SPI_SHADER_USER_ACCUM_VS_1",
2223 "name": "SPI_SHADER_USER_ACCUM_VS_2",
2229 "name": "SPI_SHADER_USER_ACCUM_VS_3",
2235 "name": "SPI_SHADER_PGM_RSRC2_GS_VS",
2241 "name": "SPI_SHADER_PGM_RSRC2_ES_VS",
2247 "name": "SPI_SHADER_PGM_RSRC2_LS_VS",
2253 "name": "SPI_SHADER_PGM_CHKSUM_GS"
2258 "name": "SPI_SHADER_PGM_RSRC4_GS",
2264 "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS"
2269 "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS"
2274 "name": "SPI_SHADER_PGM_LO_ES_GS"
2279 "name": "SPI_SHADER_PGM_HI_ES_GS",
2285 "name": "SPI_SHADER_PGM_RSRC3_GS",
2291 "name": "SPI_SHADER_PGM_LO_GS"
2296 "name": "SPI_SHADER_PGM_HI_GS",
2302 "name": "SPI_SHADER_PGM_RSRC1_GS",
2308 "name": "SPI_SHADER_PGM_RSRC2_GS",
2314 "name": "SPI_SHADER_USER_DATA_GS_0"
2319 "name": "SPI_SHADER_USER_DATA_GS_1"
2324 "name": "SPI_SHADER_USER_DATA_GS_2"
2329 "name": "SPI_SHADER_USER_DATA_GS_3"
2334 "name": "SPI_SHADER_USER_DATA_GS_4"
2339 "name": "SPI_SHADER_USER_DATA_GS_5"
2344 "name": "SPI_SHADER_USER_DATA_GS_6"
2349 "name": "SPI_SHADER_USER_DATA_GS_7"
2354 "name": "SPI_SHADER_USER_DATA_GS_8"
2359 "name": "SPI_SHADER_USER_DATA_GS_9"
2364 "name": "SPI_SHADER_USER_DATA_GS_10"
2369 "name": "SPI_SHADER_USER_DATA_GS_11"
2374 "name": "SPI_SHADER_USER_DATA_GS_12"
2379 "name": "SPI_SHADER_USER_DATA_GS_13"
2384 "name": "SPI_SHADER_USER_DATA_GS_14"
2389 "name": "SPI_SHADER_USER_DATA_GS_15"
2394 "name": "SPI_SHADER_USER_DATA_GS_16"
2399 "name": "SPI_SHADER_USER_DATA_GS_17"
2404 "name": "SPI_SHADER_USER_DATA_GS_18"
2409 "name": "SPI_SHADER_USER_DATA_GS_19"
2414 "name": "SPI_SHADER_USER_DATA_GS_20"
2419 "name": "SPI_SHADER_USER_DATA_GS_21"
2424 "name": "SPI_SHADER_USER_DATA_GS_22"
2429 "name": "SPI_SHADER_USER_DATA_GS_23"
2434 "name": "SPI_SHADER_USER_DATA_GS_24"
2439 "name": "SPI_SHADER_USER_DATA_GS_25"
2444 "name": "SPI_SHADER_USER_DATA_GS_26"
2449 "name": "SPI_SHADER_USER_DATA_GS_27"
2454 "name": "SPI_SHADER_USER_DATA_GS_28"
2459 "name": "SPI_SHADER_USER_DATA_GS_29"
2464 "name": "SPI_SHADER_USER_DATA_GS_30"
2469 "name": "SPI_SHADER_USER_DATA_GS_31"
2474 "name": "SPI_SHADER_REQ_CTRL_ESGS",
2480 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS",
2486 "name": "SPI_SHADER_USER_ACCUM_ESGS_0",
2492 "name": "SPI_SHADER_USER_ACCUM_ESGS_1",
2498 "name": "SPI_SHADER_USER_ACCUM_ESGS_2",
2504 "name": "SPI_SHADER_USER_ACCUM_ESGS_3",
2510 "name": "SPI_SHADER_PGM_RSRC2_ES_GS",
2516 "name": "SPI_SHADER_PGM_RSRC3_ES",
2522 "name": "SPI_SHADER_PGM_LO_ES"
2527 "name": "SPI_SHADER_PGM_HI_ES",
2533 "name": "SPI_SHADER_PGM_RSRC1_ES",
2539 "name": "SPI_SHADER_PGM_RSRC2_ES",
2545 "name": "SPI_SHADER_USER_DATA_ES_0"
2550 "name": "SPI_SHADER_USER_DATA_ES_1"
2555 "name": "SPI_SHADER_USER_DATA_ES_2"
2560 "name": "SPI_SHADER_USER_DATA_ES_3"
2565 "name": "SPI_SHADER_USER_DATA_ES_4"
2570 "name": "SPI_SHADER_USER_DATA_ES_5"
2575 "name": "SPI_SHADER_USER_DATA_ES_6"
2580 "name": "SPI_SHADER_USER_DATA_ES_7"
2585 "name": "SPI_SHADER_USER_DATA_ES_8"
2590 "name": "SPI_SHADER_USER_DATA_ES_9"
2595 "name": "SPI_SHADER_USER_DATA_ES_10"
2600 "name": "SPI_SHADER_USER_DATA_ES_11"
2605 "name": "SPI_SHADER_USER_DATA_ES_12"
2610 "name": "SPI_SHADER_USER_DATA_ES_13"
2615 "name": "SPI_SHADER_USER_DATA_ES_14"
2620 "name": "SPI_SHADER_USER_DATA_ES_15"
2625 "name": "SPI_SHADER_PGM_RSRC2_LS_ES",
2631 "name": "SPI_SHADER_PGM_CHKSUM_HS"
2636 "name": "SPI_SHADER_PGM_RSRC4_HS",
2642 "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS"
2647 "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS"
2652 "name": "SPI_SHADER_PGM_LO_LS_HS"
2657 "name": "SPI_SHADER_PGM_HI_LS_HS",
2663 "name": "SPI_SHADER_PGM_RSRC3_HS",
2669 "name": "SPI_SHADER_PGM_LO_HS"
2674 "name": "SPI_SHADER_PGM_HI_HS",
2680 "name": "SPI_SHADER_PGM_RSRC1_HS",
2686 "name": "SPI_SHADER_PGM_RSRC2_HS",
2692 "name": "SPI_SHADER_USER_DATA_HS_0"
2697 "name": "SPI_SHADER_USER_DATA_HS_1"
2702 "name": "SPI_SHADER_USER_DATA_HS_2"
2707 "name": "SPI_SHADER_USER_DATA_HS_3"
2712 "name": "SPI_SHADER_USER_DATA_HS_4"
2717 "name": "SPI_SHADER_USER_DATA_HS_5"
2722 "name": "SPI_SHADER_USER_DATA_HS_6"
2727 "name": "SPI_SHADER_USER_DATA_HS_7"
2732 "name": "SPI_SHADER_USER_DATA_HS_8"
2737 "name": "SPI_SHADER_USER_DATA_HS_9"
2742 "name": "SPI_SHADER_USER_DATA_HS_10"
2747 "name": "SPI_SHADER_USER_DATA_HS_11"
2752 "name": "SPI_SHADER_USER_DATA_HS_12"
2757 "name": "SPI_SHADER_USER_DATA_HS_13"
2762 "name": "SPI_SHADER_USER_DATA_HS_14"
2767 "name": "SPI_SHADER_USER_DATA_HS_15"
2772 "name": "SPI_SHADER_USER_DATA_HS_16"
2777 "name": "SPI_SHADER_USER_DATA_HS_17"
2782 "name": "SPI_SHADER_USER_DATA_HS_18"
2787 "name": "SPI_SHADER_USER_DATA_HS_19"
2792 "name": "SPI_SHADER_USER_DATA_HS_20"
2797 "name": "SPI_SHADER_USER_DATA_HS_21"
2802 "name": "SPI_SHADER_USER_DATA_HS_22"
2807 "name": "SPI_SHADER_USER_DATA_HS_23"
2812 "name": "SPI_SHADER_USER_DATA_HS_24"
2817 "name": "SPI_SHADER_USER_DATA_HS_25"
2822 "name": "SPI_SHADER_USER_DATA_HS_26"
2827 "name": "SPI_SHADER_USER_DATA_HS_27"
2832 "name": "SPI_SHADER_USER_DATA_HS_28"
2837 "name": "SPI_SHADER_USER_DATA_HS_29"
2842 "name": "SPI_SHADER_USER_DATA_HS_30"
2847 "name": "SPI_SHADER_USER_DATA_HS_31"
2852 "name": "SPI_SHADER_REQ_CTRL_LSHS",
2858 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS",
2864 "name": "SPI_SHADER_USER_ACCUM_LSHS_0",
2870 "name": "SPI_SHADER_USER_ACCUM_LSHS_1",
2876 "name": "SPI_SHADER_USER_ACCUM_LSHS_2",
2882 "name": "SPI_SHADER_USER_ACCUM_LSHS_3",
2888 "name": "SPI_SHADER_PGM_RSRC2_LS_HS",
2894 "name": "SPI_SHADER_PGM_RSRC3_LS",
2900 "name": "SPI_SHADER_PGM_LO_LS"
2905 "name": "SPI_SHADER_PGM_HI_LS",
2911 "name": "SPI_SHADER_PGM_RSRC1_LS",
2917 "name": "SPI_SHADER_PGM_RSRC2_LS",
2923 "name": "SPI_SHADER_USER_DATA_LS_0"
2928 "name": "SPI_SHADER_USER_DATA_LS_1"
2933 "name": "SPI_SHADER_USER_DATA_LS_2"
2938 "name": "SPI_SHADER_USER_DATA_LS_3"
2943 "name": "SPI_SHADER_USER_DATA_LS_4"
2948 "name": "SPI_SHADER_USER_DATA_LS_5"
2953 "name": "SPI_SHADER_USER_DATA_LS_6"
2958 "name": "SPI_SHADER_USER_DATA_LS_7"
2963 "name": "SPI_SHADER_USER_DATA_LS_8"
2968 "name": "SPI_SHADER_USER_DATA_LS_9"
2973 "name": "SPI_SHADER_USER_DATA_LS_10"
2978 "name": "SPI_SHADER_USER_DATA_LS_11"
2983 "name": "SPI_SHADER_USER_DATA_LS_12"
2988 "name": "SPI_SHADER_USER_DATA_LS_13"
2993 "name": "SPI_SHADER_USER_DATA_LS_14"
2998 "name": "SPI_SHADER_USER_DATA_LS_15"
3003 "name": "COMPUTE_DISPATCH_INITIATOR",
3009 "name": "COMPUTE_DIM_X"
3014 "name": "COMPUTE_DIM_Y"
3019 "name": "COMPUTE_DIM_Z"
3024 "name": "COMPUTE_START_X"
3029 "name": "COMPUTE_START_Y"
3034 "name": "COMPUTE_START_Z"
3039 "name": "COMPUTE_NUM_THREAD_X",
3045 "name": "COMPUTE_NUM_THREAD_Y",
3051 "name": "COMPUTE_NUM_THREAD_Z",
3057 "name": "COMPUTE_PIPELINESTAT_ENABLE",
3063 "name": "COMPUTE_PERFCOUNT_ENABLE",
3069 "name": "COMPUTE_PGM_LO"
3074 "name": "COMPUTE_PGM_HI",
3080 "name": "COMPUTE_DISPATCH_PKT_ADDR_LO"
3085 "name": "COMPUTE_DISPATCH_PKT_ADDR_HI",
3091 "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO"
3096 "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI",
3102 "name": "COMPUTE_PGM_RSRC1",
3108 "name": "COMPUTE_PGM_RSRC2",
3114 "name": "COMPUTE_VMID",
3120 "name": "COMPUTE_RESOURCE_LIMITS",
3126 "name": "COMPUTE_DESTINATION_EN_SE0"
3131 "name": "COMPUTE_DESTINATION_EN_SE1"
3136 "name": "COMPUTE_TMPRING_SIZE",
3142 "name": "COMPUTE_DESTINATION_EN_SE2"
3147 "name": "COMPUTE_DESTINATION_EN_SE3"
3152 "name": "COMPUTE_RESTART_X"
3157 "name": "COMPUTE_RESTART_Y"
3162 "name": "COMPUTE_RESTART_Z"
3167 "name": "COMPUTE_THREAD_TRACE_ENABLE",
3173 "name": "COMPUTE_MISC_RESERVED",
3179 "name": "COMPUTE_DISPATCH_ID"
3184 "name": "COMPUTE_THREADGROUP_ID"
3189 "name": "COMPUTE_REQ_CTRL",
3195 "name": "COMPUTE_USER_ACCUM_0",
3201 "name": "COMPUTE_USER_ACCUM_1",
3207 "name": "COMPUTE_USER_ACCUM_2",
3213 "name": "COMPUTE_USER_ACCUM_3",
3219 "name": "COMPUTE_PGM_RSRC3",
3225 "name": "COMPUTE_DDID_INDEX",
3231 "name": "COMPUTE_SHADER_CHKSUM"
3236 "name": "COMPUTE_RELAUNCH",
3242 "name": "COMPUTE_WAVE_RESTORE_ADDR_LO"
3247 "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
3253 "name": "COMPUTE_RELAUNCH2",
3259 "name": "COMPUTE_USER_DATA_0"
3264 "name": "COMPUTE_USER_DATA_1"
3269 "name": "COMPUTE_USER_DATA_2"
3274 "name": "COMPUTE_USER_DATA_3"
3279 "name": "COMPUTE_USER_DATA_4"
3284 "name": "COMPUTE_USER_DATA_5"
3289 "name": "COMPUTE_USER_DATA_6"
3294 "name": "COMPUTE_USER_DATA_7"
3299 "name": "COMPUTE_USER_DATA_8"
3304 "name": "COMPUTE_USER_DATA_9"
3309 "name": "COMPUTE_USER_DATA_10"
3314 "name": "COMPUTE_USER_DATA_11"
3319 "name": "COMPUTE_USER_DATA_12"
3324 "name": "COMPUTE_USER_DATA_13"
3329 "name": "COMPUTE_USER_DATA_14"
3334 "name": "COMPUTE_USER_DATA_15"
3339 "name": "COMPUTE_DISPATCH_TUNNEL",
3345 "name": "COMPUTE_DISPATCH_END"
3350 "name": "COMPUTE_NOWHERE"
3355 "name": "DB_RENDER_CONTROL",
3361 "name": "DB_COUNT_CONTROL",
3367 "name": "DB_DEPTH_VIEW",
3373 "name": "DB_RENDER_OVERRIDE",
3379 "name": "DB_RENDER_OVERRIDE2",
3385 "name": "DB_HTILE_DATA_BASE"
3390 "name": "DB_DEPTH_SIZE_XY",
3396 "name": "DB_DEPTH_BOUNDS_MIN"
3401 "name": "DB_DEPTH_BOUNDS_MAX"
3406 "name": "DB_STENCIL_CLEAR",
3412 "name": "DB_DEPTH_CLEAR"
3417 "name": "PA_SC_SCREEN_SCISSOR_TL",
3423 "name": "PA_SC_SCREEN_SCISSOR_BR",
3429 "name": "DB_DFSM_CONTROL",
3435 "name": "DB_RESERVED_REG_2",
3441 "name": "DB_Z_INFO",
3447 "name": "DB_STENCIL_INFO",
3453 "name": "DB_Z_READ_BASE"
3458 "name": "DB_STENCIL_READ_BASE"
3463 "name": "DB_Z_WRITE_BASE"
3468 "name": "DB_STENCIL_WRITE_BASE"
3473 "name": "DB_RESERVED_REG_1",
3479 "name": "DB_RESERVED_REG_3",
3485 "name": "DB_Z_READ_BASE_HI",
3491 "name": "DB_STENCIL_READ_BASE_HI",
3497 "name": "DB_Z_WRITE_BASE_HI",
3503 "name": "DB_STENCIL_WRITE_BASE_HI",
3509 "name": "DB_HTILE_DATA_BASE_HI",
3515 "name": "DB_RMI_L2_CACHE_CONTROL",
3521 "name": "TA_BC_BASE_ADDR"
3526 "name": "TA_BC_BASE_ADDR_HI",
3532 "name": "COHER_DEST_BASE_HI_0",
3538 "name": "COHER_DEST_BASE_HI_1",
3544 "name": "COHER_DEST_BASE_HI_2",
3550 "name": "COHER_DEST_BASE_HI_3",
3556 "name": "COHER_DEST_BASE_2"
3561 "name": "COHER_DEST_BASE_3"
3566 "name": "PA_SC_WINDOW_OFFSET",
3572 "name": "PA_SC_WINDOW_SCISSOR_TL",
3578 "name": "PA_SC_WINDOW_SCISSOR_BR",
3584 "name": "PA_SC_CLIPRECT_RULE",
3590 "name": "PA_SC_CLIPRECT_0_TL",
3596 "name": "PA_SC_CLIPRECT_0_BR",
3602 "name": "PA_SC_CLIPRECT_1_TL",
3608 "name": "PA_SC_CLIPRECT_1_BR",
3614 "name": "PA_SC_CLIPRECT_2_TL",
3620 "name": "PA_SC_CLIPRECT_2_BR",
3626 "name": "PA_SC_CLIPRECT_3_TL",
3632 "name": "PA_SC_CLIPRECT_3_BR",
3638 "name": "PA_SC_EDGERULE",
3644 "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3650 "name": "CB_TARGET_MASK",
3656 "name": "CB_SHADER_MASK",
3662 "name": "PA_SC_GENERIC_SCISSOR_TL",
3668 "name": "PA_SC_GENERIC_SCISSOR_BR",
3674 "name": "COHER_DEST_BASE_0"
3679 "name": "COHER_DEST_BASE_1"
3684 "name": "PA_SC_VPORT_SCISSOR_0_TL",
3690 "name": "PA_SC_VPORT_SCISSOR_0_BR",
3696 "name": "PA_SC_VPORT_SCISSOR_1_TL",
3702 "name": "PA_SC_VPORT_SCISSOR_1_BR",
3708 "name": "PA_SC_VPORT_SCISSOR_2_TL",
3714 "name": "PA_SC_VPORT_SCISSOR_2_BR",
3720 "name": "PA_SC_VPORT_SCISSOR_3_TL",
3726 "name": "PA_SC_VPORT_SCISSOR_3_BR",
3732 "name": "PA_SC_VPORT_SCISSOR_4_TL",
3738 "name": "PA_SC_VPORT_SCISSOR_4_BR",
3744 "name": "PA_SC_VPORT_SCISSOR_5_TL",
3750 "name": "PA_SC_VPORT_SCISSOR_5_BR",
3756 "name": "PA_SC_VPORT_SCISSOR_6_TL",
3762 "name": "PA_SC_VPORT_SCISSOR_6_BR",
3768 "name": "PA_SC_VPORT_SCISSOR_7_TL",
3774 "name": "PA_SC_VPORT_SCISSOR_7_BR",
3780 "name": "PA_SC_VPORT_SCISSOR_8_TL",
3786 "name": "PA_SC_VPORT_SCISSOR_8_BR",
3792 "name": "PA_SC_VPORT_SCISSOR_9_TL",
3798 "name": "PA_SC_VPORT_SCISSOR_9_BR",
3804 "name": "PA_SC_VPORT_SCISSOR_10_TL",
3810 "name": "PA_SC_VPORT_SCISSOR_10_BR",
3816 "name": "PA_SC_VPORT_SCISSOR_11_TL",
3822 "name": "PA_SC_VPORT_SCISSOR_11_BR",
3828 "name": "PA_SC_VPORT_SCISSOR_12_TL",
3834 "name": "PA_SC_VPORT_SCISSOR_12_BR",
3840 "name": "PA_SC_VPORT_SCISSOR_13_TL",
3846 "name": "PA_SC_VPORT_SCISSOR_13_BR",
3852 "name": "PA_SC_VPORT_SCISSOR_14_TL",
3858 "name": "PA_SC_VPORT_SCISSOR_14_BR",
3864 "name": "PA_SC_VPORT_SCISSOR_15_TL",
3870 "name": "PA_SC_VPORT_SCISSOR_15_BR",
3876 "name": "PA_SC_VPORT_ZMIN_0"
3881 "name": "PA_SC_VPORT_ZMAX_0"
3886 "name": "PA_SC_VPORT_ZMIN_1"
3891 "name": "PA_SC_VPORT_ZMAX_1"
3896 "name": "PA_SC_VPORT_ZMIN_2"
3901 "name": "PA_SC_VPORT_ZMAX_2"
3906 "name": "PA_SC_VPORT_ZMIN_3"
3911 "name": "PA_SC_VPORT_ZMAX_3"
3916 "name": "PA_SC_VPORT_ZMIN_4"
3921 "name": "PA_SC_VPORT_ZMAX_4"
3926 "name": "PA_SC_VPORT_ZMIN_5"
3931 "name": "PA_SC_VPORT_ZMAX_5"
3936 "name": "PA_SC_VPORT_ZMIN_6"
3941 "name": "PA_SC_VPORT_ZMAX_6"
3946 "name": "PA_SC_VPORT_ZMIN_7"
3951 "name": "PA_SC_VPORT_ZMAX_7"
3956 "name": "PA_SC_VPORT_ZMIN_8"
3961 "name": "PA_SC_VPORT_ZMAX_8"
3966 "name": "PA_SC_VPORT_ZMIN_9"
3971 "name": "PA_SC_VPORT_ZMAX_9"
3976 "name": "PA_SC_VPORT_ZMIN_10"
3981 "name": "PA_SC_VPORT_ZMAX_10"
3986 "name": "PA_SC_VPORT_ZMIN_11"
3991 "name": "PA_SC_VPORT_ZMAX_11"
3996 "name": "PA_SC_VPORT_ZMIN_12"
4001 "name": "PA_SC_VPORT_ZMAX_12"
4006 "name": "PA_SC_VPORT_ZMIN_13"
4011 "name": "PA_SC_VPORT_ZMAX_13"
4016 "name": "PA_SC_VPORT_ZMIN_14"
4021 "name": "PA_SC_VPORT_ZMAX_14"
4026 "name": "PA_SC_VPORT_ZMIN_15"
4031 "name": "PA_SC_VPORT_ZMAX_15"
4036 "name": "PA_SC_RASTER_CONFIG",
4042 "name": "PA_SC_RASTER_CONFIG_1",
4048 "name": "PA_SC_SCREEN_EXTENT_CONTROL",
4054 "name": "PA_SC_TILE_STEERING_OVERRIDE",
4060 "name": "CP_PERFMON_CNTX_CNTL",
4066 "name": "CP_PIPEID",
4072 "name": "CP_VMID",
4078 "name": "PA_SC_RIGHT_VERT_GRID",
4084 "name": "PA_SC_LEFT_VERT_GRID",
4090 "name": "PA_SC_HORIZ_GRID",
4096 "name": "VGT_MAX_VTX_INDX"
4101 "name": "VGT_MIN_VTX_INDX"
4106 "name": "VGT_INDX_OFFSET"
4111 "name": "VGT_MULTI_PRIM_IB_RESET_INDX"
4116 "name": "CB_RMI_GL2_CACHE_CONTROL",
4122 "name": "CB_BLEND_RED"
4127 "name": "CB_BLEND_GREEN"
4132 "name": "CB_BLEND_BLUE"
4137 "name": "CB_BLEND_ALPHA"
4142 "name": "CB_DCC_CONTROL",
4148 "name": "CB_COVERAGE_OUT_CONTROL",
4154 "name": "DB_STENCIL_CONTROL",
4160 "name": "DB_STENCILREFMASK",
4166 "name": "DB_STENCILREFMASK_BF",
4172 "name": "PA_CL_VPORT_XSCALE"
4177 "name": "PA_CL_VPORT_XOFFSET"
4182 "name": "PA_CL_VPORT_YSCALE"
4187 "name": "PA_CL_VPORT_YOFFSET"
4192 "name": "PA_CL_VPORT_ZSCALE"
4197 "name": "PA_CL_VPORT_ZOFFSET"
4202 "name": "PA_CL_VPORT_XSCALE_1"
4207 "name": "PA_CL_VPORT_XOFFSET_1"
4212 "name": "PA_CL_VPORT_YSCALE_1"
4217 "name": "PA_CL_VPORT_YOFFSET_1"
4222 "name": "PA_CL_VPORT_ZSCALE_1"
4227 "name": "PA_CL_VPORT_ZOFFSET_1"
4232 "name": "PA_CL_VPORT_XSCALE_2"
4237 "name": "PA_CL_VPORT_XOFFSET_2"
4242 "name": "PA_CL_VPORT_YSCALE_2"
4247 "name": "PA_CL_VPORT_YOFFSET_2"
4252 "name": "PA_CL_VPORT_ZSCALE_2"
4257 "name": "PA_CL_VPORT_ZOFFSET_2"
4262 "name": "PA_CL_VPORT_XSCALE_3"
4267 "name": "PA_CL_VPORT_XOFFSET_3"
4272 "name": "PA_CL_VPORT_YSCALE_3"
4277 "name": "PA_CL_VPORT_YOFFSET_3"
4282 "name": "PA_CL_VPORT_ZSCALE_3"
4287 "name": "PA_CL_VPORT_ZOFFSET_3"
4292 "name": "PA_CL_VPORT_XSCALE_4"
4297 "name": "PA_CL_VPORT_XOFFSET_4"
4302 "name": "PA_CL_VPORT_YSCALE_4"
4307 "name": "PA_CL_VPORT_YOFFSET_4"
4312 "name": "PA_CL_VPORT_ZSCALE_4"
4317 "name": "PA_CL_VPORT_ZOFFSET_4"
4322 "name": "PA_CL_VPORT_XSCALE_5"
4327 "name": "PA_CL_VPORT_XOFFSET_5"
4332 "name": "PA_CL_VPORT_YSCALE_5"
4337 "name": "PA_CL_VPORT_YOFFSET_5"
4342 "name": "PA_CL_VPORT_ZSCALE_5"
4347 "name": "PA_CL_VPORT_ZOFFSET_5"
4352 "name": "PA_CL_VPORT_XSCALE_6"
4357 "name": "PA_CL_VPORT_XOFFSET_6"
4362 "name": "PA_CL_VPORT_YSCALE_6"
4367 "name": "PA_CL_VPORT_YOFFSET_6"
4372 "name": "PA_CL_VPORT_ZSCALE_6"
4377 "name": "PA_CL_VPORT_ZOFFSET_6"
4382 "name": "PA_CL_VPORT_XSCALE_7"
4387 "name": "PA_CL_VPORT_XOFFSET_7"
4392 "name": "PA_CL_VPORT_YSCALE_7"
4397 "name": "PA_CL_VPORT_YOFFSET_7"
4402 "name": "PA_CL_VPORT_ZSCALE_7"
4407 "name": "PA_CL_VPORT_ZOFFSET_7"
4412 "name": "PA_CL_VPORT_XSCALE_8"
4417 "name": "PA_CL_VPORT_XOFFSET_8"
4422 "name": "PA_CL_VPORT_YSCALE_8"
4427 "name": "PA_CL_VPORT_YOFFSET_8"
4432 "name": "PA_CL_VPORT_ZSCALE_8"
4437 "name": "PA_CL_VPORT_ZOFFSET_8"
4442 "name": "PA_CL_VPORT_XSCALE_9"
4447 "name": "PA_CL_VPORT_XOFFSET_9"
4452 "name": "PA_CL_VPORT_YSCALE_9"
4457 "name": "PA_CL_VPORT_YOFFSET_9"
4462 "name": "PA_CL_VPORT_ZSCALE_9"
4467 "name": "PA_CL_VPORT_ZOFFSET_9"
4472 "name": "PA_CL_VPORT_XSCALE_10"
4477 "name": "PA_CL_VPORT_XOFFSET_10"
4482 "name": "PA_CL_VPORT_YSCALE_10"
4487 "name": "PA_CL_VPORT_YOFFSET_10"
4492 "name": "PA_CL_VPORT_ZSCALE_10"
4497 "name": "PA_CL_VPORT_ZOFFSET_10"
4502 "name": "PA_CL_VPORT_XSCALE_11"
4507 "name": "PA_CL_VPORT_XOFFSET_11"
4512 "name": "PA_CL_VPORT_YSCALE_11"
4517 "name": "PA_CL_VPORT_YOFFSET_11"
4522 "name": "PA_CL_VPORT_ZSCALE_11"
4527 "name": "PA_CL_VPORT_ZOFFSET_11"
4532 "name": "PA_CL_VPORT_XSCALE_12"
4537 "name": "PA_CL_VPORT_XOFFSET_12"
4542 "name": "PA_CL_VPORT_YSCALE_12"
4547 "name": "PA_CL_VPORT_YOFFSET_12"
4552 "name": "PA_CL_VPORT_ZSCALE_12"
4557 "name": "PA_CL_VPORT_ZOFFSET_12"
4562 "name": "PA_CL_VPORT_XSCALE_13"
4567 "name": "PA_CL_VPORT_XOFFSET_13"
4572 "name": "PA_CL_VPORT_YSCALE_13"
4577 "name": "PA_CL_VPORT_YOFFSET_13"
4582 "name": "PA_CL_VPORT_ZSCALE_13"
4587 "name": "PA_CL_VPORT_ZOFFSET_13"
4592 "name": "PA_CL_VPORT_XSCALE_14"
4597 "name": "PA_CL_VPORT_XOFFSET_14"
4602 "name": "PA_CL_VPORT_YSCALE_14"
4607 "name": "PA_CL_VPORT_YOFFSET_14"
4612 "name": "PA_CL_VPORT_ZSCALE_14"
4617 "name": "PA_CL_VPORT_ZOFFSET_14"
4622 "name": "PA_CL_VPORT_XSCALE_15"
4627 "name": "PA_CL_VPORT_XOFFSET_15"
4632 "name": "PA_CL_VPORT_YSCALE_15"
4637 "name": "PA_CL_VPORT_YOFFSET_15"
4642 "name": "PA_CL_VPORT_ZSCALE_15"
4647 "name": "PA_CL_VPORT_ZOFFSET_15"
4652 "name": "PA_CL_UCP_0_X"
4657 "name": "PA_CL_UCP_0_Y"
4662 "name": "PA_CL_UCP_0_Z"
4667 "name": "PA_CL_UCP_0_W"
4672 "name": "PA_CL_UCP_1_X"
4677 "name": "PA_CL_UCP_1_Y"
4682 "name": "PA_CL_UCP_1_Z"
4687 "name": "PA_CL_UCP_1_W"
4692 "name": "PA_CL_UCP_2_X"
4697 "name": "PA_CL_UCP_2_Y"
4702 "name": "PA_CL_UCP_2_Z"
4707 "name": "PA_CL_UCP_2_W"
4712 "name": "PA_CL_UCP_3_X"
4717 "name": "PA_CL_UCP_3_Y"
4722 "name": "PA_CL_UCP_3_Z"
4727 "name": "PA_CL_UCP_3_W"
4732 "name": "PA_CL_UCP_4_X"
4737 "name": "PA_CL_UCP_4_Y"
4742 "name": "PA_CL_UCP_4_Z"
4747 "name": "PA_CL_UCP_4_W"
4752 "name": "PA_CL_UCP_5_X"
4757 "name": "PA_CL_UCP_5_Y"
4762 "name": "PA_CL_UCP_5_Z"
4767 "name": "PA_CL_UCP_5_W"
4772 "name": "PA_CL_PROG_NEAR_CLIP_Z"
4777 "name": "SPI_PS_INPUT_CNTL_0",
4783 "name": "SPI_PS_INPUT_CNTL_1",
4789 "name": "SPI_PS_INPUT_CNTL_2",
4795 "name": "SPI_PS_INPUT_CNTL_3",
4801 "name": "SPI_PS_INPUT_CNTL_4",
4807 "name": "SPI_PS_INPUT_CNTL_5",
4813 "name": "SPI_PS_INPUT_CNTL_6",
4819 "name": "SPI_PS_INPUT_CNTL_7",
4825 "name": "SPI_PS_INPUT_CNTL_8",
4831 "name": "SPI_PS_INPUT_CNTL_9",
4837 "name": "SPI_PS_INPUT_CNTL_10",
4843 "name": "SPI_PS_INPUT_CNTL_11",
4849 "name": "SPI_PS_INPUT_CNTL_12",
4855 "name": "SPI_PS_INPUT_CNTL_13",
4861 "name": "SPI_PS_INPUT_CNTL_14",
4867 "name": "SPI_PS_INPUT_CNTL_15",
4873 "name": "SPI_PS_INPUT_CNTL_16",
4879 "name": "SPI_PS_INPUT_CNTL_17",
4885 "name": "SPI_PS_INPUT_CNTL_18",
4891 "name": "SPI_PS_INPUT_CNTL_19",
4897 "name": "SPI_PS_INPUT_CNTL_20",
4903 "name": "SPI_PS_INPUT_CNTL_21",
4909 "name": "SPI_PS_INPUT_CNTL_22",
4915 "name": "SPI_PS_INPUT_CNTL_23",
4921 "name": "SPI_PS_INPUT_CNTL_24",
4927 "name": "SPI_PS_INPUT_CNTL_25",
4933 "name": "SPI_PS_INPUT_CNTL_26",
4939 "name": "SPI_PS_INPUT_CNTL_27",
4945 "name": "SPI_PS_INPUT_CNTL_28",
4951 "name": "SPI_PS_INPUT_CNTL_29",
4957 "name": "SPI_PS_INPUT_CNTL_30",
4963 "name": "SPI_PS_INPUT_CNTL_31",
4969 "name": "SPI_VS_OUT_CONFIG",
4975 "name": "SPI_PS_INPUT_ENA",
4981 "name": "SPI_PS_INPUT_ADDR",
4987 "name": "SPI_INTERP_CONTROL_0",
4993 "name": "SPI_PS_IN_CONTROL",
4999 "name": "SPI_BARYC_CNTL",
5005 "name": "SPI_TMPRING_SIZE",
5011 "name": "SPI_SHADER_IDX_FORMAT",
5017 "name": "SPI_SHADER_POS_FORMAT",
5023 "name": "SPI_SHADER_Z_FORMAT",
5029 "name": "SPI_SHADER_COL_FORMAT",
5035 "name": "SX_PS_DOWNCONVERT",
5041 "name": "SX_BLEND_OPT_EPSILON",
5047 "name": "SX_BLEND_OPT_CONTROL",
5053 "name": "SX_MRT0_BLEND_OPT",
5059 "name": "SX_MRT1_BLEND_OPT",
5065 "name": "SX_MRT2_BLEND_OPT",
5071 "name": "SX_MRT3_BLEND_OPT",
5077 "name": "SX_MRT4_BLEND_OPT",
5083 "name": "SX_MRT5_BLEND_OPT",
5089 "name": "SX_MRT6_BLEND_OPT",
5095 "name": "SX_MRT7_BLEND_OPT",
5101 "name": "CB_BLEND0_CONTROL",
5107 "name": "CB_BLEND1_CONTROL",
5113 "name": "CB_BLEND2_CONTROL",
5119 "name": "CB_BLEND3_CONTROL",
5125 "name": "CB_BLEND4_CONTROL",
5131 "name": "CB_BLEND5_CONTROL",
5137 "name": "CB_BLEND6_CONTROL",
5143 "name": "CB_BLEND7_CONTROL",
5149 "name": "CS_COPY_STATE",
5155 "name": "GFX_COPY_STATE",
5161 "name": "PA_CL_POINT_X_RAD"
5166 "name": "PA_CL_POINT_Y_RAD"
5171 "name": "PA_CL_POINT_SIZE"
5176 "name": "PA_CL_POINT_CULL_RAD"
5181 "name": "VGT_DMA_BASE_HI",
5187 "name": "VGT_DMA_BASE"
5192 "name": "VGT_DRAW_INITIATOR",
5198 "name": "VGT_IMMED_DATA"
5203 "name": "VGT_EVENT_ADDRESS_REG",
5209 "name": "GE_MAX_OUTPUT_PER_SUBGROUP",
5215 "name": "DB_DEPTH_CONTROL",
5221 "name": "DB_EQAA",
5227 "name": "CB_COLOR_CONTROL",
5233 "name": "DB_SHADER_CONTROL",
5239 "name": "PA_CL_CLIP_CNTL",
5245 "name": "PA_SU_SC_MODE_CNTL",
5251 "name": "PA_CL_VTE_CNTL",
5257 "name": "PA_CL_VS_OUT_CNTL",
5263 "name": "PA_CL_NANINF_CNTL",
5269 "name": "PA_SU_LINE_STIPPLE_CNTL",
5275 "name": "PA_SU_LINE_STIPPLE_SCALE"
5280 "name": "PA_SU_PRIM_FILTER_CNTL",
5286 "name": "PA_SU_SMALL_PRIM_FILTER_CNTL",
5292 "name": "PA_CL_OBJPRIM_ID_CNTL",
5298 "name": "PA_CL_NGG_CNTL",
5304 "name": "PA_SU_OVER_RASTERIZATION_CNTL",
5310 "name": "PA_STEREO_CNTL",
5316 "name": "PA_STATE_STEREO_X"
5321 "name": "PA_SU_POINT_SIZE",
5327 "name": "PA_SU_POINT_MINMAX",
5333 "name": "PA_SU_LINE_CNTL",
5339 "name": "PA_SC_LINE_STIPPLE",
5345 "name": "VGT_OUTPUT_PATH_CNTL",
5351 "name": "VGT_HOS_CNTL",
5357 "name": "VGT_HOS_MAX_TESS_LEVEL"
5362 "name": "VGT_HOS_MIN_TESS_LEVEL"
5367 "name": "VGT_HOS_REUSE_DEPTH",
5373 "name": "VGT_GROUP_PRIM_TYPE",
5379 "name": "VGT_GROUP_FIRST_DECR",
5385 "name": "VGT_GROUP_DECR",
5391 "name": "VGT_GROUP_VECT_0_CNTL",
5397 "name": "VGT_GROUP_VECT_1_CNTL",
5403 "name": "VGT_GROUP_VECT_0_FMT_CNTL",
5409 "name": "VGT_GROUP_VECT_1_FMT_CNTL",
5415 "name": "VGT_GS_MODE",
5421 "name": "VGT_GS_ONCHIP_CNTL",
5427 "name": "PA_SC_MODE_CNTL_0",
5433 "name": "PA_SC_MODE_CNTL_1",
5439 "name": "VGT_ENHANCE"
5444 "name": "VGT_GS_PER_ES",
5450 "name": "VGT_ES_PER_GS",
5456 "name": "VGT_GS_PER_VS",
5462 "name": "VGT_GSVS_RING_OFFSET_1",
5468 "name": "VGT_GSVS_RING_OFFSET_2",
5474 "name": "VGT_GSVS_RING_OFFSET_3",
5480 "name": "VGT_GS_OUT_PRIM_TYPE",
5486 "name": "IA_ENHANCE"
5491 "name": "VGT_DMA_SIZE"
5496 "name": "VGT_DMA_MAX_SIZE"
5501 "name": "VGT_DMA_INDEX_TYPE",
5507 "name": "WD_ENHANCE"
5512 "name": "VGT_PRIMITIVEID_EN",
5518 "name": "VGT_DMA_NUM_INSTANCES"
5523 "name": "VGT_PRIMITIVEID_RESET"
5528 "name": "VGT_EVENT_INITIATOR",
5534 "name": "VGT_MULTI_PRIM_IB_RESET_EN",
5540 "name": "VGT_DRAW_PAYLOAD_CNTL",
5546 "name": "VGT_INSTANCE_STEP_RATE_0"
5551 "name": "VGT_INSTANCE_STEP_RATE_1"
5556 "name": "IA_MULTI_VGT_PARAM",
5562 "name": "VGT_ESGS_RING_ITEMSIZE",
5568 "name": "VGT_GSVS_RING_ITEMSIZE",
5574 "name": "VGT_REUSE_OFF",
5580 "name": "VGT_VTX_CNT_EN",
5586 "name": "DB_HTILE_SURFACE",
5592 "name": "DB_SRESULTS_COMPARE_STATE0",
5598 "name": "DB_SRESULTS_COMPARE_STATE1",
5604 "name": "DB_PRELOAD_CONTROL",
5610 "name": "VGT_STRMOUT_BUFFER_SIZE_0"
5615 "name": "VGT_STRMOUT_VTX_STRIDE_0",
5621 "name": "VGT_STRMOUT_BUFFER_OFFSET_0"
5626 "name": "VGT_STRMOUT_BUFFER_SIZE_1"
5631 "name": "VGT_STRMOUT_VTX_STRIDE_1",
5637 "name": "VGT_STRMOUT_BUFFER_OFFSET_1"
5642 "name": "VGT_STRMOUT_BUFFER_SIZE_2"
5647 "name": "VGT_STRMOUT_VTX_STRIDE_2",
5653 "name": "VGT_STRMOUT_BUFFER_OFFSET_2"
5658 "name": "VGT_STRMOUT_BUFFER_SIZE_3"
5663 "name": "VGT_STRMOUT_VTX_STRIDE_3",
5669 "name": "VGT_STRMOUT_BUFFER_OFFSET_3"
5674 "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET"
5679 "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE"
5684 "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
5690 "name": "VGT_GS_MAX_VERT_OUT",
5696 "name": "GE_NGG_SUBGRP_CNTL",
5702 "name": "VGT_TESS_DISTRIBUTION",
5708 "name": "VGT_SHADER_STAGES_EN",
5714 "name": "VGT_LS_HS_CONFIG",
5720 "name": "VGT_GS_VERT_ITEMSIZE",
5726 "name": "VGT_GS_VERT_ITEMSIZE_1",
5732 "name": "VGT_GS_VERT_ITEMSIZE_2",
5738 "name": "VGT_GS_VERT_ITEMSIZE_3",
5744 "name": "VGT_TF_PARAM",
5750 "name": "DB_ALPHA_TO_MASK",
5756 "name": "VGT_DISPATCH_DRAW_INDEX"
5761 "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
5767 "name": "PA_SU_POLY_OFFSET_CLAMP"
5772 "name": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5777 "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5782 "name": "PA_SU_POLY_OFFSET_BACK_SCALE"
5787 "name": "PA_SU_POLY_OFFSET_BACK_OFFSET"
5792 "name": "VGT_GS_INSTANCE_CNT",
5798 "name": "VGT_STRMOUT_CONFIG",
5804 "name": "VGT_STRMOUT_BUFFER_CONFIG",
5810 "name": "VGT_DMA_EVENT_INITIATOR",
5816 "name": "PA_SC_CENTROID_PRIORITY_0",
5822 "name": "PA_SC_CENTROID_PRIORITY_1",
5828 "name": "PA_SC_LINE_CNTL",
5834 "name": "PA_SC_AA_CONFIG",
5840 "name": "PA_SU_VTX_CNTL",
5846 "name": "PA_CL_GB_VERT_CLIP_ADJ"
5851 "name": "PA_CL_GB_VERT_DISC_ADJ"
5856 "name": "PA_CL_GB_HORZ_CLIP_ADJ"
5861 "name": "PA_CL_GB_HORZ_DISC_ADJ"
5866 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
5872 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
5878 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
5884 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
5890 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
5896 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
5902 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
5908 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
5914 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
5920 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
5926 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
5932 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
5938 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
5944 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
5950 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
5956 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
5962 "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
5968 "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
5974 "name": "PA_SC_SHADER_CONTROL",
5980 "name": "PA_SC_BINNER_CNTL_0",
5986 "name": "PA_SC_BINNER_CNTL_1",
5992 "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL",
5998 "name": "PA_SC_NGG_MODE_CNTL",
6004 "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
6010 "name": "VGT_OUT_DEALLOC_CNTL",
6016 "name": "CB_COLOR0_BASE"
6021 "name": "CB_COLOR0_PITCH",
6027 "name": "CB_COLOR0_SLICE",
6033 "name": "CB_COLOR0_VIEW",
6039 "name": "CB_COLOR0_INFO",
6045 "name": "CB_COLOR0_ATTRIB",
6051 "name": "CB_COLOR0_DCC_CONTROL",
6057 "name": "CB_COLOR0_CMASK"
6062 "name": "CB_COLOR0_CMASK_SLICE",
6068 "name": "CB_COLOR0_FMASK"
6073 "name": "CB_COLOR0_FMASK_SLICE",
6079 "name": "CB_COLOR0_CLEAR_WORD0"
6084 "name": "CB_COLOR0_CLEAR_WORD1"
6089 "name": "CB_COLOR0_DCC_BASE"
6094 "name": "CB_COLOR1_BASE"
6099 "name": "CB_COLOR1_PITCH",
6105 "name": "CB_COLOR1_SLICE",
6111 "name": "CB_COLOR1_VIEW",
6117 "name": "CB_COLOR1_INFO",
6123 "name": "CB_COLOR1_ATTRIB",
6129 "name": "CB_COLOR1_DCC_CONTROL",
6135 "name": "CB_COLOR1_CMASK"
6140 "name": "CB_COLOR1_CMASK_SLICE",
6146 "name": "CB_COLOR1_FMASK"
6151 "name": "CB_COLOR1_FMASK_SLICE",
6157 "name": "CB_COLOR1_CLEAR_WORD0"
6162 "name": "CB_COLOR1_CLEAR_WORD1"
6167 "name": "CB_COLOR1_DCC_BASE"
6172 "name": "CB_COLOR2_BASE"
6177 "name": "CB_COLOR2_PITCH",
6183 "name": "CB_COLOR2_SLICE",
6189 "name": "CB_COLOR2_VIEW",
6195 "name": "CB_COLOR2_INFO",
6201 "name": "CB_COLOR2_ATTRIB",
6207 "name": "CB_COLOR2_DCC_CONTROL",
6213 "name": "CB_COLOR2_CMASK"
6218 "name": "CB_COLOR2_CMASK_SLICE",
6224 "name": "CB_COLOR2_FMASK"
6229 "name": "CB_COLOR2_FMASK_SLICE",
6235 "name": "CB_COLOR2_CLEAR_WORD0"
6240 "name": "CB_COLOR2_CLEAR_WORD1"
6245 "name": "CB_COLOR2_DCC_BASE"
6250 "name": "CB_COLOR3_BASE"
6255 "name": "CB_COLOR3_PITCH",
6261 "name": "CB_COLOR3_SLICE",
6267 "name": "CB_COLOR3_VIEW",
6273 "name": "CB_COLOR3_INFO",
6279 "name": "CB_COLOR3_ATTRIB",
6285 "name": "CB_COLOR3_DCC_CONTROL",
6291 "name": "CB_COLOR3_CMASK"
6296 "name": "CB_COLOR3_CMASK_SLICE",
6302 "name": "CB_COLOR3_FMASK"
6307 "name": "CB_COLOR3_FMASK_SLICE",
6313 "name": "CB_COLOR3_CLEAR_WORD0"
6318 "name": "CB_COLOR3_CLEAR_WORD1"
6323 "name": "CB_COLOR3_DCC_BASE"
6328 "name": "CB_COLOR4_BASE"
6333 "name": "CB_COLOR4_PITCH",
6339 "name": "CB_COLOR4_SLICE",
6345 "name": "CB_COLOR4_VIEW",
6351 "name": "CB_COLOR4_INFO",
6357 "name": "CB_COLOR4_ATTRIB",
6363 "name": "CB_COLOR4_DCC_CONTROL",
6369 "name": "CB_COLOR4_CMASK"
6374 "name": "CB_COLOR4_CMASK_SLICE",
6380 "name": "CB_COLOR4_FMASK"
6385 "name": "CB_COLOR4_FMASK_SLICE",
6391 "name": "CB_COLOR4_CLEAR_WORD0"
6396 "name": "CB_COLOR4_CLEAR_WORD1"
6401 "name": "CB_COLOR4_DCC_BASE"
6406 "name": "CB_COLOR5_BASE"
6411 "name": "CB_COLOR5_PITCH",
6417 "name": "CB_COLOR5_SLICE",
6423 "name": "CB_COLOR5_VIEW",
6429 "name": "CB_COLOR5_INFO",
6435 "name": "CB_COLOR5_ATTRIB",
6441 "name": "CB_COLOR5_DCC_CONTROL",
6447 "name": "CB_COLOR5_CMASK"
6452 "name": "CB_COLOR5_CMASK_SLICE",
6458 "name": "CB_COLOR5_FMASK"
6463 "name": "CB_COLOR5_FMASK_SLICE",
6469 "name": "CB_COLOR5_CLEAR_WORD0"
6474 "name": "CB_COLOR5_CLEAR_WORD1"
6479 "name": "CB_COLOR5_DCC_BASE"
6484 "name": "CB_COLOR6_BASE"
6489 "name": "CB_COLOR6_PITCH",
6495 "name": "CB_COLOR6_SLICE",
6501 "name": "CB_COLOR6_VIEW",
6507 "name": "CB_COLOR6_INFO",
6513 "name": "CB_COLOR6_ATTRIB",
6519 "name": "CB_COLOR6_DCC_CONTROL",
6525 "name": "CB_COLOR6_CMASK"
6530 "name": "CB_COLOR6_CMASK_SLICE",
6536 "name": "CB_COLOR6_FMASK"
6541 "name": "CB_COLOR6_FMASK_SLICE",
6547 "name": "CB_COLOR6_CLEAR_WORD0"
6552 "name": "CB_COLOR6_CLEAR_WORD1"
6557 "name": "CB_COLOR6_DCC_BASE"
6562 "name": "CB_COLOR7_BASE"
6567 "name": "CB_COLOR7_PITCH",
6573 "name": "CB_COLOR7_SLICE",
6579 "name": "CB_COLOR7_VIEW",
6585 "name": "CB_COLOR7_INFO",
6591 "name": "CB_COLOR7_ATTRIB",
6597 "name": "CB_COLOR7_DCC_CONTROL",
6603 "name": "CB_COLOR7_CMASK"
6608 "name": "CB_COLOR7_CMASK_SLICE",
6614 "name": "CB_COLOR7_FMASK"
6619 "name": "CB_COLOR7_FMASK_SLICE",
6625 "name": "CB_COLOR7_CLEAR_WORD0"
6630 "name": "CB_COLOR7_CLEAR_WORD1"
6635 "name": "CB_COLOR7_DCC_BASE"
6640 "name": "CB_COLOR0_BASE_EXT",
6646 "name": "CB_COLOR1_BASE_EXT",
6652 "name": "CB_COLOR2_BASE_EXT",
6658 "name": "CB_COLOR3_BASE_EXT",
6664 "name": "CB_COLOR4_BASE_EXT",
6670 "name": "CB_COLOR5_BASE_EXT",
6676 "name": "CB_COLOR6_BASE_EXT",
6682 "name": "CB_COLOR7_BASE_EXT",
6688 "name": "CB_COLOR0_CMASK_BASE_EXT",
6694 "name": "CB_COLOR1_CMASK_BASE_EXT",
6700 "name": "CB_COLOR2_CMASK_BASE_EXT",
6706 "name": "CB_COLOR3_CMASK_BASE_EXT",
6712 "name": "CB_COLOR4_CMASK_BASE_EXT",
6718 "name": "CB_COLOR5_CMASK_BASE_EXT",
6724 "name": "CB_COLOR6_CMASK_BASE_EXT",
6730 "name": "CB_COLOR7_CMASK_BASE_EXT",
6736 "name": "CB_COLOR0_FMASK_BASE_EXT",
6742 "name": "CB_COLOR1_FMASK_BASE_EXT",
6748 "name": "CB_COLOR2_FMASK_BASE_EXT",
6754 "name": "CB_COLOR3_FMASK_BASE_EXT",
6760 "name": "CB_COLOR4_FMASK_BASE_EXT",
6766 "name": "CB_COLOR5_FMASK_BASE_EXT",
6772 "name": "CB_COLOR6_FMASK_BASE_EXT",
6778 "name": "CB_COLOR7_FMASK_BASE_EXT",
6784 "name": "CB_COLOR0_DCC_BASE_EXT",
6790 "name": "CB_COLOR1_DCC_BASE_EXT",
6796 "name": "CB_COLOR2_DCC_BASE_EXT",
6802 "name": "CB_COLOR3_DCC_BASE_EXT",
6808 "name": "CB_COLOR4_DCC_BASE_EXT",
6814 "name": "CB_COLOR5_DCC_BASE_EXT",
6820 "name": "CB_COLOR6_DCC_BASE_EXT",
6826 "name": "CB_COLOR7_DCC_BASE_EXT",
6832 "name": "CB_COLOR0_ATTRIB2",
6838 "name": "CB_COLOR1_ATTRIB2",
6844 "name": "CB_COLOR2_ATTRIB2",
6850 "name": "CB_COLOR3_ATTRIB2",
6856 "name": "CB_COLOR4_ATTRIB2",
6862 "name": "CB_COLOR5_ATTRIB2",
6868 "name": "CB_COLOR6_ATTRIB2",
6874 "name": "CB_COLOR7_ATTRIB2",
6880 "name": "CB_COLOR0_ATTRIB3",
6886 "name": "CB_COLOR1_ATTRIB3",
6892 "name": "CB_COLOR2_ATTRIB3",
6898 "name": "CB_COLOR3_ATTRIB3",
6904 "name": "CB_COLOR4_ATTRIB3",
6910 "name": "CB_COLOR5_ATTRIB3",
6916 "name": "CB_COLOR6_ATTRIB3",
6922 "name": "CB_COLOR7_ATTRIB3",
6928 "name": "CP_EOP_DONE_ADDR_LO",
6934 "name": "CP_EOP_DONE_ADDR_HI",
6940 "name": "CP_EOP_DONE_DATA_LO"
6945 "name": "CP_EOP_DONE_DATA_HI"
6950 "name": "CP_EOP_LAST_FENCE_LO"
6955 "name": "CP_EOP_LAST_FENCE_HI"
6960 "name": "CP_STREAM_OUT_ADDR_LO",
6966 "name": "CP_STREAM_OUT_ADDR_HI",
6972 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
6977 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
6982 "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
6987 "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
6992 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
6997 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
7002 "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
7007 "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
7012 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
7017 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
7022 "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
7027 "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
7032 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
7037 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
7042 "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
7047 "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
7052 "name": "CP_PIPE_STATS_ADDR_LO",
7058 "name": "CP_PIPE_STATS_ADDR_HI",
7064 "name": "CP_VGT_IAVERT_COUNT_LO"
7069 "name": "CP_VGT_IAVERT_COUNT_HI"
7074 "name": "CP_VGT_IAPRIM_COUNT_LO"
7079 "name": "CP_VGT_IAPRIM_COUNT_HI"
7084 "name": "CP_VGT_GSPRIM_COUNT_LO"
7089 "name": "CP_VGT_GSPRIM_COUNT_HI"
7094 "name": "CP_VGT_VSINVOC_COUNT_LO"
7099 "name": "CP_VGT_VSINVOC_COUNT_HI"
7104 "name": "CP_VGT_GSINVOC_COUNT_LO"
7109 "name": "CP_VGT_GSINVOC_COUNT_HI"
7114 "name": "CP_VGT_HSINVOC_COUNT_LO"
7119 "name": "CP_VGT_HSINVOC_COUNT_HI"
7124 "name": "CP_VGT_DSINVOC_COUNT_LO"
7129 "name": "CP_VGT_DSINVOC_COUNT_HI"
7134 "name": "CP_PA_CINVOC_COUNT_LO"
7139 "name": "CP_PA_CINVOC_COUNT_HI"
7144 "name": "CP_PA_CPRIM_COUNT_LO"
7149 "name": "CP_PA_CPRIM_COUNT_HI"
7154 "name": "CP_SC_PSINVOC_COUNT0_LO"
7159 "name": "CP_SC_PSINVOC_COUNT0_HI"
7164 "name": "CP_SC_PSINVOC_COUNT1_LO"
7169 "name": "CP_SC_PSINVOC_COUNT1_HI"
7174 "name": "CP_VGT_CSINVOC_COUNT_LO"
7179 "name": "CP_VGT_CSINVOC_COUNT_HI"
7184 "name": "CP_EOP_DONE_DOORBELL",
7190 "name": "CP_STREAM_OUT_DOORBELL",
7196 "name": "CP_SEM_DOORBELL",
7202 "name": "CP_PIPE_STATS_CONTROL",
7208 "name": "CP_STREAM_OUT_CONTROL",
7214 "name": "CP_STRMOUT_CNTL",
7220 "name": "SCRATCH_REG0"
7225 "name": "SCRATCH_REG1"
7230 "name": "SCRATCH_REG2"
7235 "name": "SCRATCH_REG3"
7240 "name": "SCRATCH_REG4"
7245 "name": "SCRATCH_REG5"
7250 "name": "SCRATCH_REG6"
7255 "name": "SCRATCH_REG7"
7260 "name": "CP_PIPE_STATS_DOORBELL",
7266 "name": "CP_APPEND_DDID_CNT",
7272 "name": "CP_APPEND_DATA_HI"
7277 "name": "CP_APPEND_LAST_CS_FENCE_HI"
7282 "name": "CP_APPEND_LAST_PS_FENCE_HI"
7287 "name": "SCRATCH_UMSK",
7293 "name": "SCRATCH_ADDR"
7298 "name": "CP_PFP_ATOMIC_PREOP_LO"
7303 "name": "CP_PFP_ATOMIC_PREOP_HI"
7308 "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
7313 "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
7318 "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
7323 "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
7328 "name": "CP_APPEND_ADDR_LO",
7334 "name": "CP_APPEND_ADDR_HI",
7340 "name": "CP_APPEND_DATA"
7345 "name": "CP_APPEND_LAST_CS_FENCE"
7350 "name": "CP_APPEND_LAST_PS_FENCE"
7355 "name": "CP_ATOMIC_PREOP_LO"
7360 "name": "CP_ATOMIC_PREOP_HI"
7365 "name": "CP_GDS_ATOMIC0_PREOP_LO"
7370 "name": "CP_GDS_ATOMIC0_PREOP_HI"
7375 "name": "CP_GDS_ATOMIC1_PREOP_LO"
7380 "name": "CP_GDS_ATOMIC1_PREOP_HI"
7385 "name": "CP_ME_MC_WADDR_LO",
7391 "name": "CP_ME_MC_WADDR_HI",
7397 "name": "CP_ME_MC_WDATA_LO"
7402 "name": "CP_ME_MC_WDATA_HI"
7407 "name": "CP_ME_MC_RADDR_LO",
7413 "name": "CP_ME_MC_RADDR_HI",
7419 "name": "CP_SEM_WAIT_TIMER"
7424 "name": "CP_SIG_SEM_ADDR_LO",
7430 "name": "CP_SIG_SEM_ADDR_HI",
7436 "name": "CP_WAIT_REG_MEM_TIMEOUT"
7441 "name": "CP_WAIT_SEM_ADDR_LO",
7447 "name": "CP_WAIT_SEM_ADDR_HI",
7453 "name": "CP_DMA_PFP_CONTROL",
7459 "name": "CP_DMA_ME_CONTROL",
7465 "name": "CP_COHER_BASE_HI",
7471 "name": "CP_COHER_START_DELAY",
7477 "name": "CP_COHER_CNTL",
7483 "name": "CP_COHER_SIZE"
7488 "name": "CP_COHER_BASE"
7493 "name": "CP_COHER_STATUS",
7499 "name": "CP_DMA_ME_SRC_ADDR"
7504 "name": "CP_DMA_ME_SRC_ADDR_HI",
7510 "name": "CP_DMA_ME_DST_ADDR"
7515 "name": "CP_DMA_ME_DST_ADDR_HI",
7521 "name": "CP_DMA_ME_COMMAND",
7527 "name": "CP_DMA_PFP_SRC_ADDR"
7532 "name": "CP_DMA_PFP_SRC_ADDR_HI",
7538 "name": "CP_DMA_PFP_DST_ADDR"
7543 "name": "CP_DMA_PFP_DST_ADDR_HI",
7549 "name": "CP_DMA_PFP_COMMAND",
7555 "name": "CP_DMA_CNTL",
7561 "name": "CP_DMA_READ_TAGS",
7567 "name": "CP_COHER_SIZE_HI",
7573 "name": "CP_PFP_IB_CONTROL",
7579 "name": "CP_PFP_LOAD_CONTROL",
7585 "name": "CP_SCRATCH_INDEX",
7591 "name": "CP_SCRATCH_DATA"
7596 "name": "CP_RB_OFFSET",
7602 "name": "CP_IB1_OFFSET",
7608 "name": "CP_IB2_OFFSET",
7614 "name": "CP_IB1_PREAMBLE_BEGIN",
7620 "name": "CP_IB1_PREAMBLE_END",
7626 "name": "CP_IB2_PREAMBLE_BEGIN",
7632 "name": "CP_IB2_PREAMBLE_END",
7638 "name": "CP_CE_IB1_OFFSET",
7644 "name": "CP_CE_IB2_OFFSET",
7650 "name": "CP_CE_COUNTER"
7655 "name": "CP_DMA_ME_CMD_ADDR_LO",
7661 "name": "CP_DMA_ME_CMD_ADDR_HI",
7667 "name": "CP_DMA_PFP_CMD_ADDR_LO",
7673 "name": "CP_DMA_PFP_CMD_ADDR_HI",
7679 "name": "CP_APPEND_CMD_ADDR_LO",
7685 "name": "CP_APPEND_CMD_ADDR_HI",
7691 "name": "CP_CE_INIT_CMD_BUFSZ",
7697 "name": "CP_CE_IB1_CMD_BUFSZ",
7703 "name": "CP_CE_IB2_CMD_BUFSZ",
7709 "name": "CP_IB1_CMD_BUFSZ",
7715 "name": "CP_IB2_CMD_BUFSZ",
7721 "name": "CP_ST_CMD_BUFSZ",
7727 "name": "CP_CE_INIT_BASE_LO",
7733 "name": "CP_CE_INIT_BASE_HI",
7739 "name": "CP_CE_INIT_BUFSZ",
7745 "name": "CP_CE_IB1_BASE_LO",
7751 "name": "CP_CE_IB1_BASE_HI",
7757 "name": "CP_CE_IB1_BUFSZ",
7763 "name": "CP_CE_IB2_BASE_LO",
7769 "name": "CP_CE_IB2_BASE_HI",
7775 "name": "CP_CE_IB2_BUFSZ",
7781 "name": "CP_IB1_BASE_LO",
7787 "name": "CP_IB1_BASE_HI",
7793 "name": "CP_IB1_BUFSZ",
7799 "name": "CP_IB2_BASE_LO",
7805 "name": "CP_IB2_BASE_HI",
7811 "name": "CP_IB2_BUFSZ",
7817 "name": "CP_ST_BASE_LO",
7823 "name": "CP_ST_BASE_HI",
7829 "name": "CP_ST_BUFSZ",
7835 "name": "CP_EOP_DONE_EVENT_CNTL",
7841 "name": "CP_EOP_DONE_DATA_CNTL",
7847 "name": "CP_EOP_DONE_CNTX_ID"
7852 "name": "CP_DB_BASE_LO",
7858 "name": "CP_DB_BASE_HI",
7864 "name": "CP_DB_BUFSZ",
7870 "name": "CP_DB_CMD_BUFSZ",
7876 "name": "CP_CE_DB_BASE_LO",
7882 "name": "CP_CE_DB_BASE_HI",
7888 "name": "CP_CE_DB_BUFSZ",
7894 "name": "CP_CE_DB_CMD_BUFSZ",
7900 "name": "CP_PFP_COMPLETION_STATUS",
7906 "name": "CP_CE_COMPLETION_STATUS",
7912 "name": "CP_PRED_NOT_VISIBLE",
7918 "name": "CP_PFP_METADATA_BASE_ADDR"
7923 "name": "CP_PFP_METADATA_BASE_ADDR_HI",
7929 "name": "CP_CE_METADATA_BASE_ADDR"
7934 "name": "CP_CE_METADATA_BASE_ADDR_HI",
7940 "name": "CP_DRAW_INDX_INDR_ADDR"
7945 "name": "CP_DRAW_INDX_INDR_ADDR_HI",
7951 "name": "CP_DISPATCH_INDR_ADDR"
7956 "name": "CP_DISPATCH_INDR_ADDR_HI",
7962 "name": "CP_INDEX_BASE_ADDR"
7967 "name": "CP_INDEX_BASE_ADDR_HI",
7973 "name": "CP_INDEX_TYPE",
7979 "name": "CP_GDS_BKUP_ADDR"
7984 "name": "CP_GDS_BKUP_ADDR_HI",
7990 "name": "CP_SAMPLE_STATUS",
7996 "name": "CP_ME_COHER_CNTL",
8002 "name": "CP_ME_COHER_SIZE"
8007 "name": "CP_ME_COHER_SIZE_HI",
8013 "name": "CP_ME_COHER_BASE"
8018 "name": "CP_ME_COHER_BASE_HI",
8024 "name": "CP_ME_COHER_STATUS",
8030 "name": "RLC_GPM_PERF_COUNT_0",
8036 "name": "RLC_GPM_PERF_COUNT_1",
8042 "name": "GRBM_GFX_INDEX",
8048 "name": "VGT_ESGS_RING_SIZE_UMD"
8053 "name": "VGT_GSVS_RING_SIZE_UMD"
8058 "name": "VGT_PRIMITIVE_TYPE",
8064 "name": "VGT_INDEX_TYPE",
8070 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0"
8075 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1"
8080 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2"
8085 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3"
8090 "name": "GE_MIN_VTX_INDX"
8095 "name": "GE_INDX_OFFSET"
8100 "name": "GE_MULTI_PRIM_IB_RESET_EN",
8106 "name": "VGT_NUM_INDICES"
8111 "name": "VGT_NUM_INSTANCES"
8116 "name": "VGT_TF_RING_SIZE_UMD",
8122 "name": "VGT_HS_OFFCHIP_PARAM_UMD",
8128 "name": "VGT_TF_MEMORY_BASE_UMD"
8133 "name": "GE_DMA_FIRST_INDEX"
8138 "name": "WD_POS_BUF_BASE"
8143 "name": "WD_POS_BUF_BASE_HI",
8149 "name": "WD_CNTL_SB_BUF_BASE"
8154 "name": "WD_CNTL_SB_BUF_BASE_HI",
8160 "name": "WD_INDEX_BUF_BASE"
8165 "name": "WD_INDEX_BUF_BASE_HI",
8171 "name": "IA_MULTI_VGT_PARAM_PIPED",
8177 "name": "GE_MAX_VTX_INDX"
8182 "name": "VGT_INSTANCE_BASE_ID"
8187 "name": "GE_CNTL",
8193 "name": "GE_USER_VGPR1"
8198 "name": "GE_USER_VGPR2"
8203 "name": "GE_USER_VGPR3"
8208 "name": "GE_STEREO_CNTL",
8214 "name": "GE_PC_ALLOC",
8220 "name": "VGT_TF_MEMORY_BASE_HI_UMD",
8226 "name": "GE_USER_VGPR_EN",
8232 "name": "PA_SU_LINE_STIPPLE_VALUE",
8238 "name": "PA_SC_LINE_STIPPLE_STATE",
8244 "name": "PA_SC_SCREEN_EXTENT_MIN_0",
8250 "name": "PA_SC_SCREEN_EXTENT_MAX_0",
8256 "name": "PA_SC_SCREEN_EXTENT_MIN_1",
8262 "name": "PA_SC_SCREEN_EXTENT_MAX_1",
8268 "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
8274 "name": "PA_SC_P3D_TRAP_SCREEN_H",
8280 "name": "PA_SC_P3D_TRAP_SCREEN_V",
8286 "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
8292 "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
8298 "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
8304 "name": "PA_SC_HP3D_TRAP_SCREEN_H",
8310 "name": "PA_SC_HP3D_TRAP_SCREEN_V",
8316 "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
8322 "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
8328 "name": "PA_SC_TRAP_SCREEN_HV_EN",
8334 "name": "PA_SC_TRAP_SCREEN_H",
8340 "name": "PA_SC_TRAP_SCREEN_V",
8346 "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
8352 "name": "PA_SC_TRAP_SCREEN_COUNT",
8358 "name": "SQ_THREAD_TRACE_USERDATA_0"
8363 "name": "SQ_THREAD_TRACE_USERDATA_1"
8368 "name": "SQ_THREAD_TRACE_USERDATA_2"
8373 "name": "SQ_THREAD_TRACE_USERDATA_3"
8378 "name": "SQ_THREAD_TRACE_USERDATA_4"
8383 "name": "SQ_THREAD_TRACE_USERDATA_5"
8388 "name": "SQ_THREAD_TRACE_USERDATA_6"
8393 "name": "SQ_THREAD_TRACE_USERDATA_7"
8398 "name": "SQC_CACHES",
8404 "name": "SQC_WRITEBACK",
8410 "name": "TA_CS_BC_BASE_ADDR"
8415 "name": "TA_CS_BC_BASE_ADDR_HI",
8421 "name": "DB_OCCLUSION_COUNT0_LOW"
8426 "name": "DB_OCCLUSION_COUNT0_HI",
8432 "name": "DB_OCCLUSION_COUNT1_LOW"
8437 "name": "DB_OCCLUSION_COUNT1_HI",
8443 "name": "DB_OCCLUSION_COUNT2_LOW"
8448 "name": "DB_OCCLUSION_COUNT2_HI",
8454 "name": "DB_OCCLUSION_COUNT3_LOW"
8459 "name": "DB_OCCLUSION_COUNT3_HI",
8465 "name": "DB_ZPASS_COUNT_LOW"
8470 "name": "DB_ZPASS_COUNT_HI",
8476 "name": "GDS_RD_ADDR"
8481 "name": "GDS_RD_DATA"
8486 "name": "GDS_RD_BURST_ADDR"
8491 "name": "GDS_RD_BURST_COUNT"
8496 "name": "GDS_RD_BURST_DATA"
8501 "name": "GDS_WR_ADDR"
8506 "name": "GDS_WR_DATA"
8511 "name": "GDS_WR_BURST_ADDR"
8516 "name": "GDS_WR_BURST_DATA"
8521 "name": "GDS_WRITE_COMPLETE"
8526 "name": "GDS_ATOM_CNTL",
8532 "name": "GDS_ATOM_COMPLETE",
8538 "name": "GDS_ATOM_BASE",
8544 "name": "GDS_ATOM_SIZE",
8550 "name": "GDS_ATOM_OFFSET0",
8556 "name": "GDS_ATOM_OFFSET1",
8562 "name": "GDS_ATOM_DST"
8567 "name": "GDS_ATOM_OP",
8573 "name": "GDS_ATOM_SRC0"
8578 "name": "GDS_ATOM_SRC0_U"
8583 "name": "GDS_ATOM_SRC1"
8588 "name": "GDS_ATOM_SRC1_U"
8593 "name": "GDS_ATOM_READ0"
8598 "name": "GDS_ATOM_READ0_U"
8603 "name": "GDS_ATOM_READ1"
8608 "name": "GDS_ATOM_READ1_U"
8613 "name": "GDS_GWS_RESOURCE_CNTL",
8619 "name": "GDS_GWS_RESOURCE",
8625 "name": "GDS_GWS_RESOURCE_CNT",
8631 "name": "GDS_OA_CNTL",
8637 "name": "GDS_OA_COUNTER"
8642 "name": "GDS_OA_ADDRESS",
8648 "name": "GDS_OA_INCDEC",
8654 "name": "GDS_OA_RING_SIZE"
8659 "name": "SPI_CONFIG_CNTL_REMAP"
8664 "name": "SPI_CONFIG_CNTL_1_REMAP"
8669 "name": "SPI_CONFIG_CNTL_2_REMAP"
8674 "name": "SPI_WAVE_LIMIT_CNTL_REMAP"
8679 "name": "CPG_PERFCOUNTER1_LO"
8684 "name": "CPG_PERFCOUNTER1_HI"
8689 "name": "CPG_PERFCOUNTER0_LO"
8694 "name": "CPG_PERFCOUNTER0_HI"
8699 "name": "CPC_PERFCOUNTER1_LO"
8704 "name": "CPC_PERFCOUNTER1_HI"
8709 "name": "CPC_PERFCOUNTER0_LO"
8714 "name": "CPC_PERFCOUNTER0_HI"
8719 "name": "CPF_PERFCOUNTER1_LO"
8724 "name": "CPF_PERFCOUNTER1_HI"
8729 "name": "CPF_PERFCOUNTER0_LO"
8734 "name": "CPF_PERFCOUNTER0_HI"
8739 "name": "CPF_LATENCY_STATS_DATA"
8744 "name": "CPG_LATENCY_STATS_DATA"
8749 "name": "CPC_LATENCY_STATS_DATA"
8754 "name": "GRBM_PERFCOUNTER0_LO"
8759 "name": "GRBM_PERFCOUNTER0_HI"
8764 "name": "GRBM_PERFCOUNTER1_LO"
8769 "name": "GRBM_PERFCOUNTER1_HI"
8774 "name": "GRBM_SE0_PERFCOUNTER_LO"
8779 "name": "GRBM_SE0_PERFCOUNTER_HI"
8784 "name": "GRBM_SE1_PERFCOUNTER_LO"
8789 "name": "GRBM_SE1_PERFCOUNTER_HI"
8794 "name": "GRBM_SE2_PERFCOUNTER_LO"
8799 "name": "GRBM_SE2_PERFCOUNTER_HI"
8804 "name": "GRBM_SE3_PERFCOUNTER_LO"
8809 "name": "GRBM_SE3_PERFCOUNTER_HI"
8814 "name": "GE_PERFCOUNTER0_LO"
8819 "name": "GE_PERFCOUNTER0_HI"
8824 "name": "GE_PERFCOUNTER1_LO"
8829 "name": "GE_PERFCOUNTER1_HI"
8834 "name": "GE_PERFCOUNTER2_LO"
8839 "name": "GE_PERFCOUNTER2_HI"
8844 "name": "GE_PERFCOUNTER3_LO"
8849 "name": "GE_PERFCOUNTER3_HI"
8854 "name": "GE_PERFCOUNTER4_LO"
8859 "name": "GE_PERFCOUNTER4_HI"
8864 "name": "GE_PERFCOUNTER5_LO"
8869 "name": "GE_PERFCOUNTER5_HI"
8874 "name": "GE_PERFCOUNTER6_LO"
8879 "name": "GE_PERFCOUNTER6_HI"
8884 "name": "GE_PERFCOUNTER7_LO"
8889 "name": "GE_PERFCOUNTER7_HI"
8894 "name": "GE_PERFCOUNTER8_LO"
8899 "name": "GE_PERFCOUNTER8_HI"
8904 "name": "GE_PERFCOUNTER9_LO"
8909 "name": "GE_PERFCOUNTER9_HI"
8914 "name": "GE_PERFCOUNTER10_LO"
8919 "name": "GE_PERFCOUNTER10_HI"
8924 "name": "GE_PERFCOUNTER11_LO"
8929 "name": "GE_PERFCOUNTER11_HI"
8934 "name": "PA_SU_PERFCOUNTER0_LO"
8939 "name": "PA_SU_PERFCOUNTER0_HI",
8945 "name": "PA_SU_PERFCOUNTER1_LO"
8950 "name": "PA_SU_PERFCOUNTER1_HI",
8956 "name": "PA_SU_PERFCOUNTER2_LO"
8961 "name": "PA_SU_PERFCOUNTER2_HI",
8967 "name": "PA_SU_PERFCOUNTER3_LO"
8972 "name": "PA_SU_PERFCOUNTER3_HI",
8978 "name": "PA_SC_PERFCOUNTER0_LO"
8983 "name": "PA_SC_PERFCOUNTER0_HI"
8988 "name": "PA_SC_PERFCOUNTER1_LO"
8993 "name": "PA_SC_PERFCOUNTER1_HI"
8998 "name": "PA_SC_PERFCOUNTER2_LO"
9003 "name": "PA_SC_PERFCOUNTER2_HI"
9008 "name": "PA_SC_PERFCOUNTER3_LO"
9013 "name": "PA_SC_PERFCOUNTER3_HI"
9018 "name": "PA_SC_PERFCOUNTER4_LO"
9023 "name": "PA_SC_PERFCOUNTER4_HI"
9028 "name": "PA_SC_PERFCOUNTER5_LO"
9033 "name": "PA_SC_PERFCOUNTER5_HI"
9038 "name": "PA_SC_PERFCOUNTER6_LO"
9043 "name": "PA_SC_PERFCOUNTER6_HI"
9048 "name": "PA_SC_PERFCOUNTER7_LO"
9053 "name": "PA_SC_PERFCOUNTER7_HI"
9058 "name": "SPI_PERFCOUNTER0_HI"
9063 "name": "SPI_PERFCOUNTER0_LO"
9068 "name": "SPI_PERFCOUNTER1_HI"
9073 "name": "SPI_PERFCOUNTER1_LO"
9078 "name": "SPI_PERFCOUNTER2_HI"
9083 "name": "SPI_PERFCOUNTER2_LO"
9088 "name": "SPI_PERFCOUNTER3_HI"
9093 "name": "SPI_PERFCOUNTER3_LO"
9098 "name": "SPI_PERFCOUNTER4_HI"
9103 "name": "SPI_PERFCOUNTER4_LO"
9108 "name": "SPI_PERFCOUNTER5_HI"
9113 "name": "SPI_PERFCOUNTER5_LO"
9118 "name": "SQ_PERFCOUNTER0_LO"
9123 "name": "SQ_PERFCOUNTER0_HI"
9128 "name": "SQ_PERFCOUNTER1_LO"
9133 "name": "SQ_PERFCOUNTER1_HI"
9138 "name": "SQ_PERFCOUNTER2_LO"
9143 "name": "SQ_PERFCOUNTER2_HI"
9148 "name": "SQ_PERFCOUNTER3_LO"
9153 "name": "SQ_PERFCOUNTER3_HI"
9158 "name": "SQ_PERFCOUNTER4_LO"
9163 "name": "SQ_PERFCOUNTER4_HI"
9168 "name": "SQ_PERFCOUNTER5_LO"
9173 "name": "SQ_PERFCOUNTER5_HI"
9178 "name": "SQ_PERFCOUNTER6_LO"
9183 "name": "SQ_PERFCOUNTER6_HI"
9188 "name": "SQ_PERFCOUNTER7_LO"
9193 "name": "SQ_PERFCOUNTER7_HI"
9198 "name": "SQ_PERFCOUNTER8_LO"
9203 "name": "SQ_PERFCOUNTER8_HI"
9208 "name": "SQ_PERFCOUNTER9_LO"
9213 "name": "SQ_PERFCOUNTER9_HI"
9218 "name": "SQ_PERFCOUNTER10_LO"
9223 "name": "SQ_PERFCOUNTER10_HI"
9228 "name": "SQ_PERFCOUNTER11_LO"
9233 "name": "SQ_PERFCOUNTER11_HI"
9238 "name": "SQ_PERFCOUNTER12_LO"
9243 "name": "SQ_PERFCOUNTER12_HI"
9248 "name": "SQ_PERFCOUNTER13_LO"
9253 "name": "SQ_PERFCOUNTER13_HI"
9258 "name": "SQ_PERFCOUNTER14_LO"
9263 "name": "SQ_PERFCOUNTER14_HI"
9268 "name": "SQ_PERFCOUNTER15_LO"
9273 "name": "SQ_PERFCOUNTER15_HI"
9278 "name": "SX_PERFCOUNTER0_LO"
9283 "name": "SX_PERFCOUNTER0_HI"
9288 "name": "SX_PERFCOUNTER1_LO"
9293 "name": "SX_PERFCOUNTER1_HI"
9298 "name": "SX_PERFCOUNTER2_LO"
9303 "name": "SX_PERFCOUNTER2_HI"
9308 "name": "SX_PERFCOUNTER3_LO"
9313 "name": "SX_PERFCOUNTER3_HI"
9318 "name": "GCEA_PERFCOUNTER2_LO"
9323 "name": "GCEA_PERFCOUNTER2_HI"
9328 "name": "GDS_PERFCOUNTER0_LO"
9333 "name": "GDS_PERFCOUNTER0_HI"
9338 "name": "GDS_PERFCOUNTER1_LO"
9343 "name": "GDS_PERFCOUNTER1_HI"
9348 "name": "GDS_PERFCOUNTER2_LO"
9353 "name": "GDS_PERFCOUNTER2_HI"
9358 "name": "GDS_PERFCOUNTER3_LO"
9363 "name": "GDS_PERFCOUNTER3_HI"
9368 "name": "TA_PERFCOUNTER0_LO"
9373 "name": "TA_PERFCOUNTER0_HI"
9378 "name": "TA_PERFCOUNTER1_LO"
9383 "name": "TA_PERFCOUNTER1_HI"
9388 "name": "TD_PERFCOUNTER0_LO"
9393 "name": "TD_PERFCOUNTER0_HI"
9398 "name": "TD_PERFCOUNTER1_LO"
9403 "name": "TD_PERFCOUNTER1_HI"
9408 "name": "TCP_PERFCOUNTER0_LO"
9413 "name": "TCP_PERFCOUNTER0_HI"
9418 "name": "TCP_PERFCOUNTER1_LO"
9423 "name": "TCP_PERFCOUNTER1_HI"
9428 "name": "TCP_PERFCOUNTER2_LO"
9433 "name": "TCP_PERFCOUNTER2_HI"
9438 "name": "TCP_PERFCOUNTER3_LO"
9443 "name": "TCP_PERFCOUNTER3_HI"
9448 "name": "GL2C_PERFCOUNTER0_LO"
9453 "name": "GL2C_PERFCOUNTER0_HI"
9458 "name": "GL2C_PERFCOUNTER1_LO"
9463 "name": "GL2C_PERFCOUNTER1_HI"
9468 "name": "GL2C_PERFCOUNTER2_LO"
9473 "name": "GL2C_PERFCOUNTER2_HI"
9478 "name": "GL2C_PERFCOUNTER3_LO"
9483 "name": "GL2C_PERFCOUNTER3_HI"
9488 "name": "GL2A_PERFCOUNTER0_LO"
9493 "name": "GL2A_PERFCOUNTER0_HI"
9498 "name": "GL2A_PERFCOUNTER1_LO"
9503 "name": "GL2A_PERFCOUNTER1_HI"
9508 "name": "GL2A_PERFCOUNTER2_LO"
9513 "name": "GL2A_PERFCOUNTER2_HI"
9518 "name": "GL2A_PERFCOUNTER3_LO"
9523 "name": "GL2A_PERFCOUNTER3_HI"
9528 "name": "GL1C_PERFCOUNTER0_LO"
9533 "name": "GL1C_PERFCOUNTER0_HI"
9538 "name": "GL1C_PERFCOUNTER1_LO"
9543 "name": "GL1C_PERFCOUNTER1_HI"
9548 "name": "GL1C_PERFCOUNTER2_LO"
9553 "name": "GL1C_PERFCOUNTER2_HI"
9558 "name": "GL1C_PERFCOUNTER3_LO"
9563 "name": "GL1C_PERFCOUNTER3_HI"
9568 "name": "CHC_PERFCOUNTER0_LO"
9573 "name": "CHC_PERFCOUNTER0_HI"
9578 "name": "CHC_PERFCOUNTER1_LO"
9583 "name": "CHC_PERFCOUNTER1_HI"
9588 "name": "CHC_PERFCOUNTER2_LO"
9593 "name": "CHC_PERFCOUNTER2_HI"
9598 "name": "CHC_PERFCOUNTER3_LO"
9603 "name": "CHC_PERFCOUNTER3_HI"
9608 "name": "CHCG_PERFCOUNTER0_LO"
9613 "name": "CHCG_PERFCOUNTER0_HI"
9618 "name": "CHCG_PERFCOUNTER1_LO"
9623 "name": "CHCG_PERFCOUNTER1_HI"
9628 "name": "CHCG_PERFCOUNTER2_LO"
9633 "name": "CHCG_PERFCOUNTER2_HI"
9638 "name": "CHCG_PERFCOUNTER3_LO"
9643 "name": "CHCG_PERFCOUNTER3_HI"
9648 "name": "CB_PERFCOUNTER0_LO"
9653 "name": "CB_PERFCOUNTER0_HI"
9658 "name": "CB_PERFCOUNTER1_LO"
9663 "name": "CB_PERFCOUNTER1_HI"
9668 "name": "CB_PERFCOUNTER2_LO"
9673 "name": "CB_PERFCOUNTER2_HI"
9678 "name": "CB_PERFCOUNTER3_LO"
9683 "name": "CB_PERFCOUNTER3_HI"
9688 "name": "DB_PERFCOUNTER0_LO"
9693 "name": "DB_PERFCOUNTER0_HI"
9698 "name": "DB_PERFCOUNTER1_LO"
9703 "name": "DB_PERFCOUNTER1_HI"
9708 "name": "DB_PERFCOUNTER2_LO"
9713 "name": "DB_PERFCOUNTER2_HI"
9718 "name": "DB_PERFCOUNTER3_LO"
9723 "name": "DB_PERFCOUNTER3_HI"
9728 "name": "RLC_PERFCOUNTER0_LO"
9733 "name": "RLC_PERFCOUNTER0_HI"
9738 "name": "RLC_PERFCOUNTER1_LO"
9743 "name": "RLC_PERFCOUNTER1_HI"
9748 "name": "RMI_PERFCOUNTER0_LO"
9753 "name": "RMI_PERFCOUNTER0_HI"
9758 "name": "RMI_PERFCOUNTER1_LO"
9763 "name": "RMI_PERFCOUNTER1_HI"
9768 "name": "RMI_PERFCOUNTER2_LO"
9773 "name": "RMI_PERFCOUNTER2_HI"
9778 "name": "RMI_PERFCOUNTER3_LO"
9783 "name": "RMI_PERFCOUNTER3_HI"
9788 "name": "GC_ATC_L2_PERFCOUNTER_LO"
9793 "name": "GC_ATC_L2_PERFCOUNTER_HI",
9799 "name": "GCMC_VM_L2_PERFCOUNTER_LO"
9804 "name": "GCMC_VM_L2_PERFCOUNTER_HI",
9810 "name": "GCVML2_PERFCOUNTER2_0_LO"
9815 "name": "GCVML2_PERFCOUNTER2_1_LO"
9820 "name": "GCVML2_PERFCOUNTER2_0_HI"
9825 "name": "GCVML2_PERFCOUNTER2_1_HI"
9830 "name": "GC_ATC_L2_PERFCOUNTER2_LO"
9835 "name": "GC_ATC_L2_PERFCOUNTER2_HI"
9840 "name": "UTCL1_PERFCOUNTER0_LO"
9845 "name": "UTCL1_PERFCOUNTER0_HI"
9850 "name": "UTCL1_PERFCOUNTER1_LO"
9855 "name": "UTCL1_PERFCOUNTER1_HI"
9860 "name": "GCR_PERFCOUNTER0_LO"
9865 "name": "GCR_PERFCOUNTER0_HI"
9870 "name": "GCR_PERFCOUNTER1_LO"
9875 "name": "GCR_PERFCOUNTER1_HI"
9880 "name": "PA_PH_PERFCOUNTER0_LO"
9885 "name": "PA_PH_PERFCOUNTER0_HI"
9890 "name": "PA_PH_PERFCOUNTER1_LO"
9895 "name": "PA_PH_PERFCOUNTER1_HI"
9900 "name": "PA_PH_PERFCOUNTER2_LO"
9905 "name": "PA_PH_PERFCOUNTER2_HI"
9910 "name": "PA_PH_PERFCOUNTER3_LO"
9915 "name": "PA_PH_PERFCOUNTER3_HI"
9920 "name": "PA_PH_PERFCOUNTER4_LO"
9925 "name": "PA_PH_PERFCOUNTER4_HI"
9930 "name": "PA_PH_PERFCOUNTER5_LO"
9935 "name": "PA_PH_PERFCOUNTER5_HI"
9940 "name": "PA_PH_PERFCOUNTER6_LO"
9945 "name": "PA_PH_PERFCOUNTER6_HI"
9950 "name": "PA_PH_PERFCOUNTER7_LO"
9955 "name": "PA_PH_PERFCOUNTER7_HI"
9960 "name": "GL1A_PERFCOUNTER0_LO"
9965 "name": "GL1A_PERFCOUNTER0_HI"
9970 "name": "GL1A_PERFCOUNTER1_LO"
9975 "name": "GL1A_PERFCOUNTER1_HI"
9980 "name": "GL1A_PERFCOUNTER2_LO"
9985 "name": "GL1A_PERFCOUNTER2_HI"
9990 "name": "GL1A_PERFCOUNTER3_LO"
9995 "name": "GL1A_PERFCOUNTER3_HI"
10000 "name": "CHA_PERFCOUNTER0_LO"
10005 "name": "CHA_PERFCOUNTER0_HI"
10010 "name": "CHA_PERFCOUNTER1_LO"
10015 "name": "CHA_PERFCOUNTER1_HI"
10020 "name": "CHA_PERFCOUNTER2_LO"
10025 "name": "CHA_PERFCOUNTER2_HI"
10030 "name": "CHA_PERFCOUNTER3_LO"
10035 "name": "CHA_PERFCOUNTER3_HI"
10040 "name": "GUS_PERFCOUNTER2_LO"
10045 "name": "GUS_PERFCOUNTER2_HI"
10050 "name": "CPG_PERFCOUNTER1_SELECT",
10056 "name": "CPG_PERFCOUNTER0_SELECT1",
10062 "name": "CPG_PERFCOUNTER0_SELECT",
10068 "name": "CPC_PERFCOUNTER1_SELECT",
10074 "name": "CPC_PERFCOUNTER0_SELECT1",
10080 "name": "CPF_PERFCOUNTER1_SELECT",
10086 "name": "CPF_PERFCOUNTER0_SELECT1",
10092 "name": "CPF_PERFCOUNTER0_SELECT",
10098 "name": "CP_PERFMON_CNTL",
10104 "name": "CPC_PERFCOUNTER0_SELECT",
10110 "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT",
10116 "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT",
10122 "name": "CPF_LATENCY_STATS_SELECT",
10128 "name": "CPG_LATENCY_STATS_SELECT",
10134 "name": "CPC_LATENCY_STATS_SELECT",
10140 "name": "CP_DRAW_OBJECT"
10145 "name": "CP_DRAW_OBJECT_COUNTER",
10151 "name": "CP_DRAW_WINDOW_MASK_HI"
10156 "name": "CP_DRAW_WINDOW_HI"
10161 "name": "CP_DRAW_WINDOW_LO",
10167 "name": "CP_DRAW_WINDOW_CNTL",
10173 "name": "GRBM_PERFCOUNTER0_SELECT",
10179 "name": "GRBM_PERFCOUNTER1_SELECT",
10185 "name": "GRBM_SE0_PERFCOUNTER_SELECT",
10191 "name": "GRBM_SE1_PERFCOUNTER_SELECT",
10197 "name": "GRBM_SE2_PERFCOUNTER_SELECT",
10203 "name": "GRBM_SE3_PERFCOUNTER_SELECT",
10209 "name": "GRBM_PERFCOUNTER0_SELECT_HI",
10215 "name": "GRBM_PERFCOUNTER1_SELECT_HI",
10221 "name": "GE_PERFCOUNTER0_SELECT",
10227 "name": "GE_PERFCOUNTER0_SELECT1",
10233 "name": "GE_PERFCOUNTER1_SELECT",
10239 "name": "GE_PERFCOUNTER1_SELECT1",
10245 "name": "GE_PERFCOUNTER2_SELECT",
10251 "name": "GE_PERFCOUNTER2_SELECT1",
10257 "name": "GE_PERFCOUNTER3_SELECT",
10263 "name": "GE_PERFCOUNTER3_SELECT1",
10269 "name": "GE_PERFCOUNTER4_SELECT",
10275 "name": "GE_PERFCOUNTER5_SELECT",
10281 "name": "GE_PERFCOUNTER6_SELECT",
10287 "name": "GE_PERFCOUNTER7_SELECT",
10293 "name": "GE_PERFCOUNTER8_SELECT",
10299 "name": "GE_PERFCOUNTER9_SELECT",
10305 "name": "GE_PERFCOUNTER10_SELECT",
10311 "name": "GE_PERFCOUNTER11_SELECT",
10317 "name": "PA_SU_PERFCOUNTER0_SELECT",
10323 "name": "PA_SU_PERFCOUNTER0_SELECT1",
10329 "name": "PA_SU_PERFCOUNTER1_SELECT",
10335 "name": "PA_SU_PERFCOUNTER1_SELECT1",
10341 "name": "PA_SU_PERFCOUNTER2_SELECT",
10347 "name": "PA_SU_PERFCOUNTER2_SELECT1",
10353 "name": "PA_SU_PERFCOUNTER3_SELECT",
10359 "name": "PA_SU_PERFCOUNTER3_SELECT1",
10365 "name": "PA_SC_PERFCOUNTER0_SELECT",
10371 "name": "PA_SC_PERFCOUNTER0_SELECT1",
10377 "name": "PA_SC_PERFCOUNTER1_SELECT",
10383 "name": "PA_SC_PERFCOUNTER2_SELECT",
10389 "name": "PA_SC_PERFCOUNTER3_SELECT",
10395 "name": "PA_SC_PERFCOUNTER4_SELECT",
10401 "name": "PA_SC_PERFCOUNTER5_SELECT",
10407 "name": "PA_SC_PERFCOUNTER6_SELECT",
10413 "name": "PA_SC_PERFCOUNTER7_SELECT",
10419 "name": "SPI_PERFCOUNTER0_SELECT",
10425 "name": "SPI_PERFCOUNTER1_SELECT",
10431 "name": "SPI_PERFCOUNTER2_SELECT",
10437 "name": "SPI_PERFCOUNTER3_SELECT",
10443 "name": "SPI_PERFCOUNTER0_SELECT1",
10449 "name": "SPI_PERFCOUNTER1_SELECT1",
10455 "name": "SPI_PERFCOUNTER2_SELECT1",
10461 "name": "SPI_PERFCOUNTER3_SELECT1",
10467 "name": "SPI_PERFCOUNTER4_SELECT",
10473 "name": "SPI_PERFCOUNTER5_SELECT",
10479 "name": "SPI_PERFCOUNTER_BINS",
10485 "name": "SQ_PERFCOUNTER0_SELECT",
10491 "name": "SQ_PERFCOUNTER1_SELECT",
10497 "name": "SQ_PERFCOUNTER2_SELECT",
10503 "name": "SQ_PERFCOUNTER3_SELECT",
10509 "name": "SQ_PERFCOUNTER4_SELECT",
10515 "name": "SQ_PERFCOUNTER5_SELECT",
10521 "name": "SQ_PERFCOUNTER6_SELECT",
10527 "name": "SQ_PERFCOUNTER7_SELECT",
10533 "name": "SQ_PERFCOUNTER8_SELECT",
10539 "name": "SQ_PERFCOUNTER9_SELECT",
10545 "name": "SQ_PERFCOUNTER10_SELECT",
10551 "name": "SQ_PERFCOUNTER11_SELECT",
10557 "name": "SQ_PERFCOUNTER12_SELECT",
10563 "name": "SQ_PERFCOUNTER13_SELECT",
10569 "name": "SQ_PERFCOUNTER14_SELECT",
10575 "name": "SQ_PERFCOUNTER15_SELECT",
10581 "name": "SQ_PERFCOUNTER_CTRL",
10587 "name": "SQ_PERFCOUNTER_CTRL2",
10593 "name": "GCEA_PERFCOUNTER2_SELECT",
10599 "name": "GCEA_PERFCOUNTER2_SELECT1",
10605 "name": "GCEA_PERFCOUNTER2_MODE",
10611 "name": "SX_PERFCOUNTER0_SELECT",
10617 "name": "SX_PERFCOUNTER1_SELECT",
10623 "name": "SX_PERFCOUNTER2_SELECT",
10629 "name": "SX_PERFCOUNTER3_SELECT",
10635 "name": "SX_PERFCOUNTER0_SELECT1",
10641 "name": "SX_PERFCOUNTER1_SELECT1",
10647 "name": "GDS_PERFCOUNTER0_SELECT",
10653 "name": "GDS_PERFCOUNTER1_SELECT",
10659 "name": "GDS_PERFCOUNTER2_SELECT",
10665 "name": "GDS_PERFCOUNTER3_SELECT",
10671 "name": "GDS_PERFCOUNTER0_SELECT1",
10677 "name": "TA_PERFCOUNTER0_SELECT",
10683 "name": "TA_PERFCOUNTER0_SELECT1",
10689 "name": "TA_PERFCOUNTER1_SELECT",
10695 "name": "TD_PERFCOUNTER0_SELECT",
10701 "name": "TD_PERFCOUNTER0_SELECT1",
10707 "name": "TD_PERFCOUNTER1_SELECT",
10713 "name": "TCP_PERFCOUNTER0_SELECT",
10719 "name": "TCP_PERFCOUNTER0_SELECT1",
10725 "name": "TCP_PERFCOUNTER1_SELECT",
10731 "name": "TCP_PERFCOUNTER1_SELECT1",
10737 "name": "TCP_PERFCOUNTER2_SELECT",
10743 "name": "TCP_PERFCOUNTER3_SELECT",
10749 "name": "GL2C_PERFCOUNTER0_SELECT",
10755 "name": "GL2C_PERFCOUNTER0_SELECT1",
10761 "name": "GL2C_PERFCOUNTER1_SELECT",
10767 "name": "GL2C_PERFCOUNTER1_SELECT1",
10773 "name": "GL2C_PERFCOUNTER2_SELECT",
10779 "name": "GL2C_PERFCOUNTER3_SELECT",
10785 "name": "GL2A_PERFCOUNTER0_SELECT",
10791 "name": "GL2A_PERFCOUNTER0_SELECT1",
10797 "name": "GL2A_PERFCOUNTER1_SELECT",
10803 "name": "GL2A_PERFCOUNTER1_SELECT1",
10809 "name": "GL2A_PERFCOUNTER2_SELECT",
10815 "name": "GL2A_PERFCOUNTER3_SELECT",
10821 "name": "GL1C_PERFCOUNTER0_SELECT",
10827 "name": "GL1C_PERFCOUNTER0_SELECT1",
10833 "name": "GL1C_PERFCOUNTER1_SELECT",
10839 "name": "GL1C_PERFCOUNTER2_SELECT",
10845 "name": "GL1C_PERFCOUNTER3_SELECT",
10851 "name": "CHC_PERFCOUNTER0_SELECT",
10857 "name": "CHC_PERFCOUNTER0_SELECT1",
10863 "name": "CHC_PERFCOUNTER1_SELECT",
10869 "name": "CHC_PERFCOUNTER2_SELECT",
10875 "name": "CHC_PERFCOUNTER3_SELECT",
10881 "name": "CHCG_PERFCOUNTER0_SELECT",
10887 "name": "CHCG_PERFCOUNTER0_SELECT1",
10893 "name": "CHCG_PERFCOUNTER1_SELECT",
10899 "name": "CHCG_PERFCOUNTER2_SELECT",
10905 "name": "CHCG_PERFCOUNTER3_SELECT",
10911 "name": "CB_PERFCOUNTER_FILTER",
10917 "name": "CB_PERFCOUNTER0_SELECT",
10923 "name": "CB_PERFCOUNTER0_SELECT1",
10929 "name": "CB_PERFCOUNTER1_SELECT",
10935 "name": "CB_PERFCOUNTER2_SELECT",
10941 "name": "CB_PERFCOUNTER3_SELECT",
10947 "name": "DB_PERFCOUNTER0_SELECT",
10953 "name": "DB_PERFCOUNTER0_SELECT1",
10959 "name": "DB_PERFCOUNTER1_SELECT",
10965 "name": "DB_PERFCOUNTER1_SELECT1",
10971 "name": "DB_PERFCOUNTER2_SELECT",
10977 "name": "DB_PERFCOUNTER3_SELECT",
10983 "name": "RLC_SPM_PERFMON_CNTL",
10989 "name": "RLC_SPM_PERFMON_RING_BASE_LO"
10994 "name": "RLC_SPM_PERFMON_RING_BASE_HI",
11000 "name": "RLC_SPM_PERFMON_RING_SIZE"
11005 "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
11011 "name": "RLC_SPM_RING_RDPTR"
11016 "name": "RLC_SPM_SEGMENT_THRESHOLD",
11022 "name": "RLC_SPM_SE_MUXSEL_ADDR",
11028 "name": "RLC_SPM_SE_MUXSEL_DATA"
11033 "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR",
11039 "name": "RLC_SPM_GLOBAL_MUXSEL_DATA"
11044 "name": "RLC_SPM_DESER_START_SKEW",
11050 "name": "RLC_SPM_GLOBALS_SAMPLE_SKEW",
11056 "name": "RLC_SPM_GLOBALS_MUXSEL_SKEW",
11062 "name": "RLC_SPM_SE_SAMPLE_SKEW",
11068 "name": "RLC_SPM_SE_MUXSEL_SKEW",
11074 "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR"
11079 "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA",
11085 "name": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR"
11090 "name": "RLC_SPM_SE_SAMPLEDELAY_IND_DATA",
11096 "name": "RLC_SPM_RING_WRPTR",
11102 "name": "RLC_SPM_ACCUM_DATARAM_ADDR",
11108 "name": "RLC_SPM_ACCUM_DATARAM_DATA"
11113 "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR",
11119 "name": "RLC_SPM_ACCUM_CTRLRAM_DATA",
11125 "name": "RLC_SPM_ACCUM_STATUS",
11131 "name": "RLC_SPM_ACCUM_CTRL",
11137 "name": "RLC_SPM_ACCUM_MODE",
11143 "name": "RLC_SPM_ACCUM_THRESHOLD",
11149 "name": "RLC_SPM_ACCUM_SAMPLES_REQUESTED",
11155 "name": "RLC_SPM_ACCUM_DATARAM_WRCOUNT",
11161 "name": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE",
11167 "name": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE",
11173 "name": "RLC_SPM_VIRT_CTRL",
11179 "name": "RLC_SPM_VIRT_STATUS",
11185 "name": "RLC_PERFMON_CNTL",
11191 "name": "RLC_PERFCOUNTER0_SELECT",
11197 "name": "RLC_PERFCOUNTER1_SELECT",
11203 "name": "RLC_GPU_IOV_PERF_CNT_CNTL",
11209 "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR",
11215 "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA"
11220 "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR",
11226 "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA"
11231 "name": "RLC_PERFMON_CLK_CNTL",
11237 "name": "RLC_PERFMON_CLK_CNTL_UCODE",
11243 "name": "RMI_PERFCOUNTER0_SELECT",
11249 "name": "RMI_PERFCOUNTER0_SELECT1",
11255 "name": "RMI_PERFCOUNTER1_SELECT",
11261 "name": "RMI_PERFCOUNTER2_SELECT",
11267 "name": "RMI_PERFCOUNTER2_SELECT1",
11273 "name": "RMI_PERFCOUNTER3_SELECT",
11279 "name": "RMI_PERF_COUNTER_CNTL",
11285 "name": "GC_ATC_L2_PERFCOUNTER0_CFG",
11291 "name": "GC_ATC_L2_PERFCOUNTER1_CFG",
11297 "name": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL",
11303 "name": "GCMC_VM_L2_PERFCOUNTER0_CFG",
11309 "name": "GCMC_VM_L2_PERFCOUNTER1_CFG",
11315 "name": "GCMC_VM_L2_PERFCOUNTER2_CFG",
11321 "name": "GCMC_VM_L2_PERFCOUNTER3_CFG",
11327 "name": "GCMC_VM_L2_PERFCOUNTER4_CFG",
11333 "name": "GCMC_VM_L2_PERFCOUNTER5_CFG",
11339 "name": "GCMC_VM_L2_PERFCOUNTER6_CFG",
11345 "name": "GCMC_VM_L2_PERFCOUNTER7_CFG",
11351 "name": "GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL",
11357 "name": "GCVML2_PERFCOUNTER2_0_SELECT",
11363 "name": "GCVML2_PERFCOUNTER2_1_SELECT",
11369 "name": "GCVML2_PERFCOUNTER2_0_SELECT1",
11375 "name": "GCVML2_PERFCOUNTER2_1_SELECT1",
11381 "name": "GCVML2_PERFCOUNTER2_0_MODE",
11387 "name": "GCVML2_PERFCOUNTER2_1_MODE",
11393 "name": "GC_ATC_L2_PERFCOUNTER2_SELECT",
11399 "name": "GC_ATC_L2_PERFCOUNTER2_SELECT1",
11405 "name": "GC_ATC_L2_PERFCOUNTER2_MODE",
11411 "name": "GCR_PERFCOUNTER0_SELECT",
11417 "name": "GCR_PERFCOUNTER0_SELECT1",
11423 "name": "GCR_PERFCOUNTER1_SELECT",
11429 "name": "UTCL1_PERFCOUNTER0_SELECT",
11435 "name": "UTCL1_PERFCOUNTER1_SELECT",
11441 "name": "PA_PH_PERFCOUNTER0_SELECT",
11447 "name": "PA_PH_PERFCOUNTER0_SELECT1",
11453 "name": "PA_PH_PERFCOUNTER1_SELECT",
11459 "name": "PA_PH_PERFCOUNTER2_SELECT",
11465 "name": "PA_PH_PERFCOUNTER3_SELECT",
11471 "name": "PA_PH_PERFCOUNTER4_SELECT",
11477 "name": "PA_PH_PERFCOUNTER5_SELECT",
11483 "name": "PA_PH_PERFCOUNTER6_SELECT",
11489 "name": "PA_PH_PERFCOUNTER7_SELECT",
11495 "name": "PA_PH_PERFCOUNTER1_SELECT1",
11501 "name": "PA_PH_PERFCOUNTER2_SELECT1",
11507 "name": "PA_PH_PERFCOUNTER3_SELECT1",
11513 "name": "GL1A_PERFCOUNTER0_SELECT",
11519 "name": "GL1A_PERFCOUNTER0_SELECT1",
11525 "name": "GL1A_PERFCOUNTER1_SELECT",
11531 "name": "GL1A_PERFCOUNTER2_SELECT",
11537 "name": "GL1A_PERFCOUNTER3_SELECT",
11543 "name": "CHA_PERFCOUNTER0_SELECT",
11549 "name": "CHA_PERFCOUNTER0_SELECT1",
11555 "name": "CHA_PERFCOUNTER1_SELECT",
11561 "name": "CHA_PERFCOUNTER2_SELECT",
11567 "name": "CHA_PERFCOUNTER3_SELECT",
11573 "name": "GUS_PERFCOUNTER2_SELECT",
11579 "name": "GUS_PERFCOUNTER2_SELECT1",
11585 "name": "GUS_PERFCOUNTER2_MODE",
11592 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
11593 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
11594 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
11595 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
11596 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
11597 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
11598 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
11599 {"bits": [30, 30], "name": "ENABLE"},
11600 {"bits": [31, 31], "name": "DISABLE_ROP3"}
11605 {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
11606 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
11607 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
11608 {"bits": [12, 14], "name": "NUM_SAMPLES"},
11609 {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
11610 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"},
11611 {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"},
11612 {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"}
11617 {"bits": [0, 13], "name": "MIP0_HEIGHT"},
11618 {"bits": [14, 27], "name": "MIP0_WIDTH"},
11619 {"bits": [28, 31], "name": "MAX_MIP"}
11624 {"bits": [0, 12], "name": "MIP0_DEPTH"},
11625 {"bits": [13, 13], "name": "META_LINEAR"},
11626 {"bits": [14, 18], "name": "COLOR_SW_MODE"},
11627 {"bits": [19, 23], "name": "FMASK_SW_MODE"},
11628 {"bits": [24, 25], "name": "RESOURCE_TYPE"},
11629 {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"},
11630 {"bits": [27, 29], "name": "RESOURCE_LEVEL"},
11631 {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"}
11636 {"bits": [0, 7], "name": "BASE_256B"}
11641 {"bits": [0, 13], "name": "TILE_MAX"}
11646 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
11647 {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
11648 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
11649 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
11650 {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
11651 {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
11652 {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
11653 {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
11654 {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"},
11655 {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
11656 {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"},
11657 {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"}
11662 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
11663 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
11664 {"bits": [7, 7], "name": "LINEAR_GENERAL"},
11665 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
11666 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
11667 {"bits": [13, 13], "name": "FAST_CLEAR"},
11668 {"bits": [14, 14], "name": "COMPRESSION"},
11669 {"bits": [15, 15], "name": "BLEND_CLAMP"},
11670 {"bits": [16, 16], "name": "BLEND_BYPASS"},
11671 {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
11672 {"bits": [18, 18], "name": "ROUND_MODE"},
11673 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
11674 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
11675 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
11676 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
11677 {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
11678 {"bits": [28, 28], "name": "DCC_ENABLE"},
11679 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"},
11680 {"bits": [31, 31], "name": "ALT_TILE_MODE"}
11685 {"bits": [0, 10], "name": "TILE_MAX"},
11686 {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
11691 {"bits": [0, 21], "name": "TILE_MAX"}
11696 {"bits": [0, 12], "name": "SLICE_START"},
11697 {"bits": [13, 25], "name": "SLICE_MAX"},
11698 {"bits": [26, 29], "name": "MIP_LEVEL"}
11703 {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
11704 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
11705 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
11706 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
11711 {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"},
11712 {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"},
11713 {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"},
11714 {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"}
11719 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
11720 {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"},
11721 {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"},
11722 {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"},
11723 {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"},
11724 {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"},
11725 {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"},
11726 {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"}
11731 {"bits": [0, 8], "name": "PERF_SEL"},
11732 {"bits": [10, 18], "name": "PERF_SEL1"},
11733 {"bits": [20, 23], "name": "CNTR_MODE"},
11734 {"bits": [24, 27], "name": "PERF_MODE1"},
11735 {"bits": [28, 31], "name": "PERF_MODE"}
11740 {"bits": [0, 8], "name": "PERF_SEL2"},
11741 {"bits": [10, 18], "name": "PERF_SEL3"},
11742 {"bits": [24, 27], "name": "PERF_MODE3"},
11743 {"bits": [28, 31], "name": "PERF_MODE2"}
11748 {"bits": [0, 8], "name": "PERF_SEL"},
11749 {"bits": [28, 31], "name": "PERF_MODE"}
11754 {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
11755 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
11756 {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
11757 {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
11758 {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
11759 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
11760 {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
11761 {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
11762 {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
11763 {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
11764 {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
11765 {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
11770 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"},
11771 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"},
11772 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"},
11773 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"},
11774 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"},
11775 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"},
11776 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"},
11777 {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"},
11778 {"bits": [30, 30], "name": "FMASK_BIG_PAGE"},
11779 {"bits": [31, 31], "name": "COLOR_BIG_PAGE"}
11784 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
11785 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
11786 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
11787 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
11788 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
11789 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
11790 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
11791 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
11796 {"bits": [0, 3], "name": "TARGET0_ENABLE"},
11797 {"bits": [4, 7], "name": "TARGET1_ENABLE"},
11798 {"bits": [8, 11], "name": "TARGET2_ENABLE"},
11799 {"bits": [12, 15], "name": "TARGET3_ENABLE"},
11800 {"bits": [16, 19], "name": "TARGET4_ENABLE"},
11801 {"bits": [20, 23], "name": "TARGET5_ENABLE"},
11802 {"bits": [24, 27], "name": "TARGET6_ENABLE"},
11803 {"bits": [28, 31], "name": "TARGET7_ENABLE"}
11808 {"bits": [0, 7], "name": "DEST_BASE_HI_256B"}
11813 {"bits": [0, 10], "name": "INDEX"}
11818 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
11819 {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
11820 {"bits": [2, 2], "name": "FORCE_START_AT_000"},
11821 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
11822 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
11823 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
11824 {"bits": [6, 6], "name": "ORDER_MODE"},
11825 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
11826 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
11827 {"bits": [12, 12], "name": "RESERVED"},
11828 {"bits": [13, 13], "name": "TUNNEL_ENABLE"},
11829 {"bits": [14, 14], "name": "RESTORE"},
11830 {"bits": [15, 15], "name": "CS_W32_EN"}
11835 {"bits": [0, 9], "name": "OFF_DELAY"},
11836 {"bits": [10, 10], "name": "IMMEDIATE"}
11841 {"bits": [0, 1], "name": "SEND_SEID"},
11842 {"bits": [2, 2], "name": "RESERVED2"},
11843 {"bits": [3, 3], "name": "RESERVED3"},
11844 {"bits": [4, 4], "name": "RESERVED4"},
11845 {"bits": [5, 16], "name": "WAVE_ID_BASE"}
11850 {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
11851 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
11856 {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
11861 {"bits": [0, 7], "name": "DATA"}
11866 {"bits": [0, 5], "name": "VGPRS"},
11867 {"bits": [6, 9], "name": "SGPRS"},
11868 {"bits": [10, 11], "name": "PRIORITY"},
11869 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11870 {"bits": [20, 20], "name": "PRIV"},
11871 {"bits": [21, 21], "name": "DX10_CLAMP"},
11872 {"bits": [23, 23], "name": "IEEE_MODE"},
11873 {"bits": [24, 24], "name": "BULKY"},
11874 {"bits": [26, 26], "name": "FP16_OVFL"},
11875 {"bits": [29, 29], "name": "WGP_MODE"},
11876 {"bits": [30, 30], "name": "MEM_ORDERED"},
11877 {"bits": [31, 31], "name": "FWD_PROGRESS"}
11882 {"bits": [0, 0], "name": "SCRATCH_EN"},
11883 {"bits": [1, 5], "name": "USER_SGPR"},
11884 {"bits": [6, 6], "name": "TRAP_PRESENT"},
11885 {"bits": [7, 7], "name": "TGID_X_EN"},
11886 {"bits": [8, 8], "name": "TGID_Y_EN"},
11887 {"bits": [9, 9], "name": "TGID_Z_EN"},
11888 {"bits": [10, 10], "name": "TG_SIZE_EN"},
11889 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
11890 {"bits": [13, 14], "name": "EXCP_EN_MSB"},
11891 {"bits": [15, 23], "name": "LDS_SIZE"},
11892 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11897 {"bits": [0, 3], "name": "SHARED_VGPR_CNT"}
11902 {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
11907 {"bits": [0, 29], "name": "PAYLOAD"},
11908 {"bits": [30, 30], "name": "IS_EVENT"},
11909 {"bits": [31, 31], "name": "IS_STATE"}
11914 {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
11915 {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
11916 {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
11917 {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
11918 {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
11919 {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
11920 {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
11921 {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"},
11922 {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"}
11927 {"bits": [0, 9], "name": "WAVES_PER_SH"},
11928 {"bits": [12, 15], "name": "TG_PER_CU"},
11929 {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
11930 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
11931 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
11932 {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
11937 {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
11942 {"bits": [0, 11], "name": "WAVES"},
11943 {"bits": [12, 24], "name": "WAVESIZE"}
11948 {"bits": [0, 3], "name": "DATA"}
11953 {"bits": [0, 15], "name": "ADDR"}
11958 {"bits": [0, 3], "name": "INDEX"},
11959 {"bits": [30, 30], "name": "CLEAR"},
11960 {"bits": [31, 31], "name": "ENABLE"}
11965 {"bits": [0, 2], "name": "INDEX"},
11966 {"bits": [30, 30], "name": "ALWAYS"},
11967 {"bits": [31, 31], "name": "ENABLE"}
11972 {"bits": [0, 4], "name": "INDEX"},
11973 {"bits": [30, 30], "name": "CLEAR"},
11974 {"bits": [31, 31], "name": "ENABLE"}
11979 {"bits": [0, 9], "name": "PERF_SEL2"},
11980 {"bits": [10, 19], "name": "PERF_SEL3"},
11981 {"bits": [24, 27], "name": "CNTR_MODE3"},
11982 {"bits": [28, 31], "name": "CNTR_MODE2"}
11987 {"bits": [0, 9], "name": "PERF_SEL"},
11988 {"bits": [10, 19], "name": "PERF_SEL1"},
11989 {"bits": [20, 23], "name": "SPM_MODE"},
11990 {"bits": [24, 27], "name": "CNTR_MODE1"},
11991 {"bits": [28, 31], "name": "CNTR_MODE0"}
11996 {"bits": [0, 4], "name": "INDEX"},
11997 {"bits": [30, 30], "name": "ALWAYS"},
11998 {"bits": [31, 31], "name": "ENABLE"}
12003 {"bits": [0, 15], "name": "MEM_ADDR_HI"},
12004 {"bits": [16, 16], "name": "CS_PS_SEL"},
12005 {"bits": [25, 26], "name": "CACHE_POLICY"},
12006 {"bits": [29, 31], "name": "COMMAND"}
12011 {"bits": [2, 31], "name": "MEM_ADDR_LO"}
12016 {"bits": [0, 15], "name": "IB1_BASE_HI"}
12021 {"bits": [2, 31], "name": "IB1_BASE_LO"}
12026 {"bits": [0, 19], "name": "IB1_BUFSZ"}
12031 {"bits": [0, 19], "name": "IB1_CMD_REQSZ"}
12036 {"bits": [0, 15], "name": "IB2_BASE_HI"}
12041 {"bits": [2, 31], "name": "IB2_BASE_LO"}
12046 {"bits": [0, 19], "name": "IB2_BUFSZ"}
12051 {"bits": [0, 19], "name": "IB2_CMD_REQSZ"}
12056 {"bits": [0, 15], "name": "INIT_BASE_HI"}
12061 {"bits": [5, 31], "name": "INIT_BASE_LO"}
12066 {"bits": [0, 11], "name": "INIT_BUFSZ"}
12071 {"bits": [0, 11], "name": "INIT_CMD_REQSZ"}
12076 {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
12081 {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
12082 {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"},
12083 {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"},
12084 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
12085 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
12086 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
12087 {"bits": [23, 23], "name": "TC_ACTION_ENA"},
12088 {"bits": [25, 25], "name": "CB_ACTION_ENA"},
12089 {"bits": [26, 26], "name": "DB_ACTION_ENA"},
12090 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
12091 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
12092 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
12093 {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"}
12098 {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
12103 {"bits": [0, 5], "name": "START_DELAY_COUNT"}
12108 {"bits": [24, 25], "name": "MEID"},
12109 {"bits": [31, 31], "name": "STATUS"}
12114 {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
12115 {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
12116 {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
12117 {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
12118 {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
12119 {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
12120 {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
12121 {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
12122 {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
12123 {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
12124 {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
12125 {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
12126 {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
12127 {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
12128 {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
12129 {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
12130 {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
12131 {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
12132 {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
12133 {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
12134 {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
12135 {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
12136 {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
12137 {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
12138 {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
12139 {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
12140 {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
12141 {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
12146 {"bits": [0, 0], "name": "MES_LOAD_BUSY"},
12147 {"bits": [2, 2], "name": "MES_MUTEX_BUSY"},
12148 {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"},
12149 {"bits": [7, 7], "name": "MES_TC_BUSY"},
12150 {"bits": [8, 8], "name": "MES_DMA_BUSY"},
12151 {"bits": [10, 10], "name": "MES_PIPE0_BUSY"},
12152 {"bits": [11, 11], "name": "MES_PIPE1_BUSY"},
12153 {"bits": [12, 12], "name": "MES_PIPE2_BUSY"},
12154 {"bits": [13, 13], "name": "MES_PIPE3_BUSY"}
12159 {"bits": [0, 5], "name": "FREE_COUNT"}
12164 {"bits": [0, 3], "name": "COUNT"}
12169 {"bits": [0, 8], "name": "SCRATCH_INDEX"},
12170 {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
12175 {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
12176 {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
12177 {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
12178 {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
12179 {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
12180 {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
12181 {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
12182 {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
12183 {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
12184 {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
12185 {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
12186 {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"},
12187 {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"},
12188 {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"},
12189 {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"}
12194 {"bits": [0, 0], "name": "MEC1_BUSY"},
12195 {"bits": [1, 1], "name": "MEC2_BUSY"},
12196 {"bits": [2, 2], "name": "DC0_BUSY"},
12197 {"bits": [3, 3], "name": "DC1_BUSY"},
12198 {"bits": [4, 4], "name": "RCIU1_BUSY"},
12199 {"bits": [5, 5], "name": "RCIU2_BUSY"},
12200 {"bits": [6, 6], "name": "ROQ1_BUSY"},
12201 {"bits": [7, 7], "name": "ROQ2_BUSY"},
12202 {"bits": [10, 10], "name": "TCIU_BUSY"},
12203 {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
12204 {"bits": [12, 12], "name": "QU_BUSY"},
12205 {"bits": [13, 13], "name": "UTCL2IU_BUSY"},
12206 {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"},
12207 {"bits": [15, 15], "name": "GCRIU_BUSY"},
12208 {"bits": [16, 16], "name": "MES_BUSY"},
12209 {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"},
12210 {"bits": [18, 18], "name": "RCIU3_BUSY"},
12211 {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"},
12212 {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
12213 {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
12214 {"bits": [31, 31], "name": "CPC_BUSY"}
12219 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
12220 {"bits": [1, 1], "name": "CSF_RING_BUSY"},
12221 {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
12222 {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
12223 {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
12224 {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
12225 {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
12226 {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
12227 {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
12228 {"bits": [9, 9], "name": "CSF_DATA_BUSY"},
12229 {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"},
12230 {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
12231 {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
12232 {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
12233 {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
12234 {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
12235 {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
12236 {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
12237 {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
12238 {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
12239 {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
12240 {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
12241 {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
12242 {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
12243 {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
12244 {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
12245 {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
12246 {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
12247 {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
12248 {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
12249 {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
12250 {"bits": [31, 31], "name": "HQD_IB_BUSY"}
12255 {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"},
12256 {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"},
12257 {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"},
12258 {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"},
12259 {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"},
12260 {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"},
12261 {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"},
12262 {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"},
12263 {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"}
12268 {"bits": [0, 2], "name": "FREE_COUNT"}
12273 {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
12274 {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
12275 {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
12276 {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
12277 {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
12278 {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
12279 {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"},
12280 {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"},
12281 {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"},
12282 {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"},
12283 {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"},
12284 {"bits": [12, 12], "name": "DATA_FETCHING_DATA"},
12285 {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"}
12290 {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
12291 {"bits": [1, 1], "name": "CSF_BUSY"},
12292 {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
12293 {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
12294 {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
12295 {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
12296 {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
12297 {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
12298 {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
12299 {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
12300 {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
12301 {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
12302 {"bits": [14, 14], "name": "TCIU_BUSY"},
12303 {"bits": [15, 15], "name": "HQD_BUSY"},
12304 {"bits": [16, 16], "name": "PRT_BUSY"},
12305 {"bits": [17, 17], "name": "UTCL2IU_BUSY"},
12306 {"bits": [18, 18], "name": "RCIU_BUSY"},
12307 {"bits": [19, 19], "name": "RCIU_GFX_BUSY"},
12308 {"bits": [20, 20], "name": "RCIU_CMP_BUSY"},
12309 {"bits": [21, 21], "name": "ROQ_DATA_BUSY"},
12310 {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"},
12311 {"bits": [23, 23], "name": "GCRIU_BUSY"},
12312 {"bits": [24, 24], "name": "MES_HQD_BUSY"},
12313 {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
12314 {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
12315 {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
12316 {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
12317 {"bits": [31, 31], "name": "CPF_BUSY"}
12322 {"bits": [0, 15], "name": "DB_BASE_HI"}
12327 {"bits": [2, 31], "name": "DB_BASE_LO"}
12332 {"bits": [0, 19], "name": "DB_BUFSZ"}
12337 {"bits": [0, 19], "name": "DB_CMD_REQSZ"}
12342 {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"},
12343 {"bits": [1, 1], "name": "WATCH_CONTROL"},
12344 {"bits": [4, 5], "name": "MIN_AVAILSZ"},
12345 {"bits": [16, 24], "name": "BUFFER_DEPTH"},
12346 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
12347 {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
12348 {"bits": [30, 31], "name": "PIO_COUNT"}
12353 {"bits": [0, 15], "name": "ADDR_HI"},
12354 {"bits": [16, 31], "name": "RSVD"}
12359 {"bits": [0, 1], "name": "RSVD"},
12360 {"bits": [2, 31], "name": "ADDR_LO"}
12365 {"bits": [0, 25], "name": "BYTE_COUNT"},
12366 {"bits": [26, 26], "name": "SAS"},
12367 {"bits": [27, 27], "name": "DAS"},
12368 {"bits": [28, 28], "name": "SAIC"},
12369 {"bits": [29, 29], "name": "DAIC"},
12370 {"bits": [30, 30], "name": "RAW_WAIT"},
12371 {"bits": [31, 31], "name": "DIS_WC"}
12376 {"bits": [0, 15], "name": "DST_ADDR_HI"}
12381 {"bits": [0, 15], "name": "SRC_ADDR_HI"}
12386 {"bits": [10, 10], "name": "MEMLOG_CLEAR"},
12387 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
12388 {"bits": [15, 15], "name": "SRC_VOLATLE"},
12389 {"bits": [20, 21], "name": "DST_SELECT"},
12390 {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
12391 {"bits": [27, 27], "name": "DST_VOLATLE"},
12392 {"bits": [29, 30], "name": "SRC_SELECT"}
12397 {"bits": [0, 25], "name": "DMA_READ_TAG"},
12398 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
12403 {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
12404 {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
12405 {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
12406 {"bits": [8, 8], "name": "MODE"}
12411 {"bits": [0, 15], "name": "MIN"},
12412 {"bits": [16, 31], "name": "MAX"}
12417 {"bits": [0, 15], "name": "ADDR_HI"}
12422 {"bits": [2, 31], "name": "ADDR_LO"}
12427 {"bits": [16, 17], "name": "DST_SEL"},
12428 {"bits": [24, 26], "name": "INT_SEL"},
12429 {"bits": [29, 31], "name": "DATA_SEL"}
12434 {"bits": [2, 27], "name": "DOORBELL_OFFSET"}
12439 {"bits": [12, 23], "name": "GCR_CNTL"},
12440 {"bits": [25, 26], "name": "CACHE_POLICY"},
12441 {"bits": [27, 27], "name": "EOP_VOLATILE"},
12442 {"bits": [28, 28], "name": "EXECUTE"}
12447 {"bits": [0, 19], "name": "IB1_OFFSET"}
12452 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}
12457 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}
12462 {"bits": [0, 19], "name": "IB2_OFFSET"}
12467 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
12472 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
12477 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
12482 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
12483 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
12484 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
12485 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
12486 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
12487 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
12488 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
12489 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
12490 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
12491 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
12492 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
12493 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
12494 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}
12499 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
12500 {"bits": [31, 31], "name": "STATUS"}
12505 {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
12506 {"bits": [22, 23], "name": "CACHE_POLICY"}
12511 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
12516 {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
12517 {"bits": [22, 23], "name": "CACHE_POLICY"}
12522 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
12527 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
12528 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
12529 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
12530 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
12535 {"bits": [31, 31], "name": "PERFMON_ENABLE"}
12540 {"bits": [0, 1], "name": "STATUS"}
12545 {"bits": [0, 7], "name": "IB_EN"}
12550 {"bits": [0, 0], "name": "CONFIG_REG_EN"},
12551 {"bits": [1, 1], "name": "CNTX_REG_EN"},
12552 {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
12553 {"bits": [24, 24], "name": "SH_CS_REG_EN"}
12558 {"bits": [0, 1], "name": "PIPE_ID"}
12563 {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
12568 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
12573 {"bits": [25, 26], "name": "CACHE_POLICY"}
12578 {"bits": [0, 0], "name": "NOT_VISIBLE"}
12583 {"bits": [0, 19], "name": "RB_OFFSET"}
12588 {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
12589 {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
12590 {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
12591 {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
12592 {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
12593 {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
12594 {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
12595 {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
12600 {"bits": [0, 7], "name": "SCRATCH_INDEX"},
12601 {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
12606 {"bits": [0, 15], "name": "SEM_ADDR_HI"},
12607 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
12608 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
12609 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
12610 {"bits": [29, 31], "name": "SEM_SELECT"}
12615 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},
12616 {"bits": [3, 31], "name": "SEM_ADDR_LO"}
12621 {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
12626 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
12631 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
12636 {"bits": [0, 15], "name": "ST_BASE_HI"}
12641 {"bits": [2, 31], "name": "ST_BASE_LO"}
12646 {"bits": [0, 19], "name": "ST_BUFSZ"}
12651 {"bits": [0, 19], "name": "ST_CMD_REQSZ"}
12656 {"bits": [0, 3], "name": "VMID"}
12661 {"bits": [0, 2], "name": "SRC_STATE_ID"}
12666 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
12667 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
12668 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
12669 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
12670 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
12671 {"bits": [16, 16], "name": "OFFSET_ROUND"}
12676 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
12677 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
12678 {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"},
12679 {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"},
12680 {"bits": [4, 6], "name": "SAMPLE_RATE"},
12681 {"bits": [8, 11], "name": "ZPASS_ENABLE"},
12682 {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
12683 {"bits": [16, 19], "name": "SFAIL_ENABLE"},
12684 {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
12685 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
12686 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
12691 {"bits": [0, 0], "name": "STENCIL_ENABLE"},
12692 {"bits": [1, 1], "name": "Z_ENABLE"},
12693 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
12694 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
12695 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
12696 {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
12697 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
12698 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
12699 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
12700 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
12705 {"bits": [0, 13], "name": "X_MAX"},
12706 {"bits": [16, 29], "name": "Y_MAX"}
12711 {"bits": [0, 10], "name": "SLICE_START"},
12712 {"bits": [11, 12], "name": "SLICE_START_HI"},
12713 {"bits": [13, 23], "name": "SLICE_MAX"},
12714 {"bits": [24, 24], "name": "Z_READ_ONLY"},
12715 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"},
12716 {"bits": [26, 29], "name": "MIPID"},
12717 {"bits": [30, 31], "name": "SLICE_MAX_HI"}
12722 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"},
12723 {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"},
12724 {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"}
12729 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
12730 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
12731 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
12732 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
12733 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
12734 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
12735 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
12736 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
12737 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
12738 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
12739 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
12740 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
12745 {"bits": [0, 0], "name": "RESERVED_FIELD_1"},
12746 {"bits": [1, 1], "name": "FULL_CACHE"},
12747 {"bits": [2, 2], "name": "RESERVED_FIELD_2"},
12748 {"bits": [3, 3], "name": "RESERVED_FIELD_3"},
12749 {"bits": [4, 9], "name": "RESERVED_FIELD_4"},
12750 {"bits": [10, 15], "name": "RESERVED_FIELD_5"},
12751 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
12752 {"bits": [17, 17], "name": "RESERVED_FIELD_6"},
12753 {"bits": [18, 18], "name": "PIPE_ALIGNED"}
12758 {"bits": [0, 30], "name": "COUNT_HI"}
12763 {"bits": [0, 7], "name": "START_X"},
12764 {"bits": [8, 15], "name": "START_Y"},
12765 {"bits": [16, 23], "name": "MAX_X"},
12766 {"bits": [24, 31], "name": "MAX_Y"}
12771 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
12772 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
12773 {"bits": [2, 2], "name": "DEPTH_COPY"},
12774 {"bits": [3, 3], "name": "STENCIL_COPY"},
12775 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
12776 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
12777 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
12778 {"bits": [7, 7], "name": "COPY_CENTROID"},
12779 {"bits": [8, 11], "name": "COPY_SAMPLE"},
12780 {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"}
12785 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
12786 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
12787 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
12788 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
12789 {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
12790 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
12791 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
12792 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
12793 {"bits": [11, 11], "name": "FORCE_Z_READ"},
12794 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
12795 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
12796 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
12797 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
12798 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
12799 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
12800 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
12801 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
12802 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
12803 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
12804 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
12805 {"bits": [29, 29], "name": "FORCE_Z_VALID"},
12806 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
12807 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
12812 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
12813 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
12814 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
12815 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
12816 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
12817 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
12818 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
12819 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
12820 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
12821 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
12822 {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
12823 {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
12824 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
12825 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
12826 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
12827 {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"}
12832 {"bits": [0, 10], "name": "FIELD_1"},
12833 {"bits": [11, 21], "name": "FIELD_2"}
12838 {"bits": [0, 3], "name": "FIELD_1"},
12839 {"bits": [4, 7], "name": "FIELD_2"},
12840 {"bits": [8, 12], "name": "FIELD_3"},
12841 {"bits": [13, 14], "name": "FIELD_4"},
12842 {"bits": [15, 16], "name": "FIELD_5"},
12843 {"bits": [17, 18], "name": "FIELD_6"},
12844 {"bits": [19, 20], "name": "FIELD_7"},
12845 {"bits": [28, 31], "name": "RESOURCE_LEVEL"}
12850 {"bits": [0, 21], "name": "FIELD_1"}
12855 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"},
12856 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"},
12857 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"},
12858 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"},
12859 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"},
12860 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"},
12861 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"},
12862 {"bits": [24, 24], "name": "Z_BIG_PAGE"},
12863 {"bits": [25, 25], "name": "S_BIG_PAGE"}
12868 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
12869 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
12870 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
12871 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
12872 {"bits": [6, 6], "name": "KILL_ENABLE"},
12873 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
12874 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
12875 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
12876 {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
12877 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
12878 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
12879 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
12880 {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"},
12881 {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"},
12882 {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"},
12883 {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"},
12884 {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"}
12889 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
12890 {"bits": [4, 11], "name": "COMPAREVALUE0"},
12891 {"bits": [12, 19], "name": "COMPAREMASK0"},
12892 {"bits": [24, 24], "name": "ENABLE0"}
12897 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
12898 {"bits": [4, 11], "name": "COMPAREVALUE1"},
12899 {"bits": [12, 19], "name": "COMPAREMASK1"},
12900 {"bits": [24, 24], "name": "ENABLE1"}
12905 {"bits": [0, 7], "name": "STENCILTESTVAL"},
12906 {"bits": [8, 15], "name": "STENCILMASK"},
12907 {"bits": [16, 23], "name": "STENCILWRITEMASK"},
12908 {"bits": [24, 31], "name": "STENCILOPVAL"}
12913 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
12914 {"bits": [8, 15], "name": "STENCILMASK_BF"},
12915 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
12916 {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
12921 {"bits": [0, 7], "name": "CLEAR"}
12926 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
12927 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
12928 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
12929 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
12930 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
12931 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
12936 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
12937 {"bits": [4, 8], "name": "SW_MODE"},
12938 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12939 {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12940 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12941 {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12942 {"bits": [20, 20], "name": "ITERATE_256"},
12943 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12944 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
12949 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
12950 {"bits": [2, 3], "name": "NUM_SAMPLES"},
12951 {"bits": [4, 8], "name": "SW_MODE"},
12952 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12953 {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12954 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12955 {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12956 {"bits": [16, 19], "name": "MAXMIP"},
12957 {"bits": [20, 20], "name": "ITERATE_256"},
12958 {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
12959 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12960 {"bits": [28, 28], "name": "READ_SIZE"},
12961 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
12962 {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
12967 {"bits": [0, 7], "name": "BASE_HI"}
12972 {"bits": [0, 2], "name": "NUM_PIPES"},
12973 {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"},
12974 {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"},
12975 {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"},
12976 {"bits": [26, 27], "name": "NUM_RB_PER_SE"}
12981 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
12982 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
12983 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
12984 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
12989 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
12990 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
12991 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
12992 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
12993 {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
12998 {"bits": [0, 1], "name": "COMPARE_MODE0"},
12999 {"bits": [2, 3], "name": "COMPARE_MODE1"},
13000 {"bits": [4, 5], "name": "COMPARE_MODE2"},
13001 {"bits": [6, 7], "name": "COMPARE_MODE3"},
13002 {"bits": [8, 11], "name": "COMPARE_VALUE0"},
13003 {"bits": [12, 15], "name": "COMPARE_VALUE1"},
13004 {"bits": [16, 19], "name": "COMPARE_VALUE2"},
13005 {"bits": [20, 23], "name": "COMPARE_VALUE3"}
13010 {"bits": [0, 8], "name": "PERF_SEL"},
13011 {"bits": [24, 27], "name": "PERF_MODE"},
13012 {"bits": [28, 31], "name": "CNTL_MODE"}
13017 {"bits": [0, 7], "name": "PERF_SEL"},
13018 {"bits": [8, 15], "name": "PERF_SEL_END"},
13019 {"bits": [24, 27], "name": "PERF_MODE"},
13020 {"bits": [28, 28], "name": "ENABLE"},
13021 {"bits": [29, 29], "name": "CLEAR"}
13026 {"bits": [0, 15], "name": "COUNTER_HI"},
13027 {"bits": [16, 31], "name": "COMPARE_VALUE"}
13032 {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"},
13033 {"bits": [8, 15], "name": "START_TRIGGER"},
13034 {"bits": [16, 23], "name": "STOP_TRIGGER"},
13035 {"bits": [24, 24], "name": "ENABLE_ANY"},
13036 {"bits": [25, 25], "name": "CLEAR_ALL"},
13037 {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"}
13042 {"bits": [0, 15], "name": "BASE"},
13043 {"bits": [16, 31], "name": "UNUSED"}
13048 {"bits": [0, 5], "name": "AINC"},
13049 {"bits": [6, 7], "name": "UNUSED1"},
13050 {"bits": [8, 9], "name": "DMODE"},
13051 {"bits": [10, 31], "name": "UNUSED2"}
13056 {"bits": [0, 0], "name": "COMPLETE"},
13057 {"bits": [1, 31], "name": "UNUSED"}
13062 {"bits": [0, 7], "name": "OFFSET0"},
13063 {"bits": [8, 31], "name": "UNUSED"}
13068 {"bits": [0, 7], "name": "OFFSET1"},
13069 {"bits": [8, 31], "name": "UNUSED"}
13074 {"bits": [0, 7], "name": "OP"},
13075 {"bits": [8, 31], "name": "UNUSED"}
13080 {"bits": [0, 15], "name": "SIZE"},
13081 {"bits": [16, 31], "name": "UNUSED"}
13086 {"bits": [0, 0], "name": "FLAG"},
13087 {"bits": [1, 12], "name": "COUNTER"},
13088 {"bits": [13, 13], "name": "TYPE"},
13089 {"bits": [14, 14], "name": "DED"},
13090 {"bits": [15, 15], "name": "RELEASE_ALL"},
13091 {"bits": [16, 26], "name": "HEAD_QUEUE"},
13092 {"bits": [27, 27], "name": "HEAD_VALID"},
13093 {"bits": [28, 28], "name": "HEAD_FLAG"},
13094 {"bits": [29, 29], "name": "HALTED"},
13095 {"bits": [30, 31], "name": "UNUSED1"}
13100 {"bits": [0, 15], "name": "RESOURCE_CNT"},
13101 {"bits": [16, 31], "name": "UNUSED"}
13106 {"bits": [0, 5], "name": "INDEX"},
13107 {"bits": [6, 31], "name": "UNUSED"}
13112 {"bits": [0, 15], "name": "DS_ADDRESS"},
13113 {"bits": [16, 19], "name": "CRAWLER_TYPE"},
13114 {"bits": [20, 23], "name": "CRAWLER"},
13115 {"bits": [24, 29], "name": "UNUSED"},
13116 {"bits": [30, 30], "name": "NO_ALLOC"},
13117 {"bits": [31, 31], "name": "ENABLE"}
13122 {"bits": [0, 3], "name": "INDEX"},
13123 {"bits": [4, 31], "name": "UNUSED"}
13128 {"bits": [0, 30], "name": "VALUE"},
13129 {"bits": [31, 31], "name": "INCDEC"}
13134 {"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
13135 {"bits": [9, 17], "name": "VERT_GRP_SIZE"},
13136 {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
13137 {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
13142 {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"}
13147 {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"},
13148 {"bits": [9, 17], "name": "THDS_PER_SUBGRP"}
13153 {"bits": [0, 0], "name": "OVERSUB_EN"},
13154 {"bits": [1, 10], "name": "NUM_PC_LINES"}
13159 {"bits": [0, 9], "name": "PERF_SEL0"},
13160 {"bits": [10, 19], "name": "PERF_SEL1"},
13161 {"bits": [20, 23], "name": "CNTR_MODE"},
13162 {"bits": [24, 27], "name": "PERF_MODE0"},
13163 {"bits": [28, 31], "name": "PERF_MODE1"}
13168 {"bits": [0, 9], "name": "PERF_SEL2"},
13169 {"bits": [10, 19], "name": "PERF_SEL3"},
13170 {"bits": [24, 27], "name": "PERF_MODE2"},
13171 {"bits": [28, 31], "name": "PERF_MODE3"}
13176 {"bits": [0, 9], "name": "PERF_SEL0"},
13177 {"bits": [28, 31], "name": "PERF_MODE"}
13182 {"bits": [0, 2], "name": "RT_SLICE"},
13183 {"bits": [3, 6], "name": "VIEWPORT"},
13184 {"bits": [8, 8], "name": "EN_STEREO"}
13189 {"bits": [0, 0], "name": "EN_USER_VGPR1"},
13190 {"bits": [1, 1], "name": "EN_USER_VGPR2"},
13191 {"bits": [2, 2], "name": "EN_USER_VGPR3"}
13196 {"bits": [0, 7], "name": "INSTANCE_INDEX"},
13197 {"bits": [8, 15], "name": "SA_INDEX"},
13198 {"bits": [16, 23], "name": "SE_INDEX"},
13199 {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"},
13200 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
13201 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
13206 {"bits": [0, 5], "name": "PERF_SEL"},
13207 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
13208 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
13209 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
13210 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
13211 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
13212 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
13213 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
13214 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
13215 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
13216 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
13217 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
13218 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
13219 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
13220 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
13221 {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"},
13222 {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"},
13223 {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"},
13224 {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"},
13225 {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"}
13230 {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
13231 {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"},
13232 {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"},
13233 {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"},
13234 {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"},
13235 {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"},
13236 {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"},
13237 {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
13242 {"bits": [0, 5], "name": "PERF_SEL"},
13243 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
13244 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
13245 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
13246 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
13247 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
13248 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
13249 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
13250 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
13251 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
13252 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"},
13253 {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"},
13254 {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
13255 {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"},
13256 {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
13261 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
13262 {"bits": [5, 5], "name": "RSMU_RQ_PENDING"},
13263 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
13264 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
13265 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
13266 {"bits": [12, 12], "name": "DB_CLEAN"},
13267 {"bits": [13, 13], "name": "CB_CLEAN"},
13268 {"bits": [14, 14], "name": "TA_BUSY"},
13269 {"bits": [15, 15], "name": "GDS_BUSY"},
13270 {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"},
13271 {"bits": [20, 20], "name": "SX_BUSY"},
13272 {"bits": [21, 21], "name": "GE_BUSY"},
13273 {"bits": [22, 22], "name": "SPI_BUSY"},
13274 {"bits": [23, 23], "name": "BCI_BUSY"},
13275 {"bits": [24, 24], "name": "SC_BUSY"},
13276 {"bits": [25, 25], "name": "PA_BUSY"},
13277 {"bits": [26, 26], "name": "DB_BUSY"},
13278 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
13279 {"bits": [29, 29], "name": "CP_BUSY"},
13280 {"bits": [30, 30], "name": "CB_BUSY"},
13281 {"bits": [31, 31], "name": "GUI_ACTIVE"}
13286 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
13287 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
13288 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
13289 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
13290 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
13291 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
13292 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
13293 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
13294 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
13295 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
13296 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
13297 {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
13298 {"bits": [15, 15], "name": "UTCL2_BUSY"},
13299 {"bits": [16, 16], "name": "EA_BUSY"},
13300 {"bits": [17, 17], "name": "RMI_BUSY"},
13301 {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"},
13302 {"bits": [19, 19], "name": "CPF_RQ_PENDING"},
13303 {"bits": [20, 20], "name": "EA_LINK_BUSY"},
13304 {"bits": [21, 21], "name": "SDMA_BUSY"},
13305 {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"},
13306 {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"},
13307 {"bits": [24, 24], "name": "RLC_BUSY"},
13308 {"bits": [25, 25], "name": "TCP_BUSY"},
13309 {"bits": [28, 28], "name": "CPF_BUSY"},
13310 {"bits": [29, 29], "name": "CPC_BUSY"},
13311 {"bits": [30, 30], "name": "CPG_BUSY"},
13312 {"bits": [31, 31], "name": "CPAXI_BUSY"}
13317 {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"},
13318 {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"},
13319 {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"},
13320 {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"},
13321 {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"},
13322 {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"},
13323 {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"},
13324 {"bits": [13, 13], "name": "PH_BUSY"},
13325 {"bits": [14, 14], "name": "CH_BUSY"},
13326 {"bits": [15, 15], "name": "GL2CC_BUSY"},
13327 {"bits": [16, 16], "name": "GL1CC_BUSY"},
13328 {"bits": [28, 28], "name": "GUS_LINK_BUSY"},
13329 {"bits": [29, 29], "name": "GUS_BUSY"},
13330 {"bits": [30, 30], "name": "UTCL1_BUSY"},
13331 {"bits": [31, 31], "name": "PMM_BUSY"}
13336 {"bits": [1, 1], "name": "DB_CLEAN"},
13337 {"bits": [2, 2], "name": "CB_CLEAN"},
13338 {"bits": [3, 3], "name": "UTCL1_BUSY"},
13339 {"bits": [4, 4], "name": "TCP_BUSY"},
13340 {"bits": [5, 5], "name": "GL1CC_BUSY"},
13341 {"bits": [21, 21], "name": "RMI_BUSY"},
13342 {"bits": [22, 22], "name": "BCI_BUSY"},
13343 {"bits": [24, 24], "name": "PA_BUSY"},
13344 {"bits": [25, 25], "name": "TA_BUSY"},
13345 {"bits": [26, 26], "name": "SX_BUSY"},
13346 {"bits": [27, 27], "name": "SPI_BUSY"},
13347 {"bits": [29, 29], "name": "SC_BUSY"},
13348 {"bits": [30, 30], "name": "DB_BUSY"},
13349 {"bits": [31, 31], "name": "CB_BUSY"}
13354 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
13355 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
13356 {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
13357 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
13358 {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
13359 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}
13364 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
13365 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
13366 {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
13367 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
13368 {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
13369 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
13370 {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"},
13371 {"bits": [22, 22], "name": "EN_INST_OPT_ADV"},
13372 {"bits": [23, 23], "name": "HW_USE_ONLY"}
13377 {"bits": [0, 0], "name": "UCP_ENA_0"},
13378 {"bits": [1, 1], "name": "UCP_ENA_1"},
13379 {"bits": [2, 2], "name": "UCP_ENA_2"},
13380 {"bits": [3, 3], "name": "UCP_ENA_3"},
13381 {"bits": [4, 4], "name": "UCP_ENA_4"},
13382 {"bits": [5, 5], "name": "UCP_ENA_5"},
13383 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
13384 {"bits": [14, 15], "name": "PS_UCP_MODE"},
13385 {"bits": [16, 16], "name": "CLIP_DISABLE"},
13386 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
13387 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
13388 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
13389 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
13390 {"bits": [21, 21], "name": "VTX_KILL_OR"},
13391 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
13392 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
13393 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
13394 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
13395 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"},
13396 {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"}
13401 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
13402 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
13403 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
13404 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
13405 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
13406 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
13407 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
13408 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
13409 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
13410 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
13411 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
13412 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
13413 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
13414 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
13415 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
13416 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
13421 {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
13422 {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"}
13427 {"bits": [0, 0], "name": "OBJ_ID_SEL"},
13428 {"bits": [1, 1], "name": "ADD_PIPED_PRIM_ID"}
13433 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
13434 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
13435 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
13436 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
13437 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
13438 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
13439 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
13440 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
13441 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
13442 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
13443 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
13444 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
13445 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
13446 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
13447 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
13448 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
13449 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
13450 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
13451 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
13452 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
13453 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
13454 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
13455 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
13456 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
13457 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
13458 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
13459 {"bits": [26, 26], "name": "USE_VTX_SHD_OBJPRIM_ID"},
13460 {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"}
13465 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
13466 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
13467 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
13468 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
13469 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
13470 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
13471 {"bits": [8, 8], "name": "VTX_XY_FMT"},
13472 {"bits": [9, 9], "name": "VTX_Z_FMT"},
13473 {"bits": [10, 10], "name": "VTX_W0_FMT"},
13474 {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
13479 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
13480 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
13481 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
13482 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
13483 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
13484 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"}
13489 {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
13490 {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
13495 {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
13496 {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
13501 {"bits": [0, 3], "name": "S0_X"},
13502 {"bits": [4, 7], "name": "S0_Y"},
13503 {"bits": [8, 11], "name": "S1_X"},
13504 {"bits": [12, 15], "name": "S1_Y"},
13505 {"bits": [16, 19], "name": "S2_X"},
13506 {"bits": [20, 23], "name": "S2_Y"},
13507 {"bits": [24, 27], "name": "S3_X"},
13508 {"bits": [28, 31], "name": "S3_Y"}
13513 {"bits": [0, 3], "name": "S4_X"},
13514 {"bits": [4, 7], "name": "S4_Y"},
13515 {"bits": [8, 11], "name": "S5_X"},
13516 {"bits": [12, 15], "name": "S5_Y"},
13517 {"bits": [16, 19], "name": "S6_X"},
13518 {"bits": [20, 23], "name": "S6_Y"},
13519 {"bits": [24, 27], "name": "S7_X"},
13520 {"bits": [28, 31], "name": "S7_Y"}
13525 {"bits": [0, 3], "name": "S8_X"},
13526 {"bits": [4, 7], "name": "S8_Y"},
13527 {"bits": [8, 11], "name": "S9_X"},
13528 {"bits": [12, 15], "name": "S9_Y"},
13529 {"bits": [16, 19], "name": "S10_X"},
13530 {"bits": [20, 23], "name": "S10_Y"},
13531 {"bits": [24, 27], "name": "S11_X"},
13532 {"bits": [28, 31], "name": "S11_Y"}
13537 {"bits": [0, 3], "name": "S12_X"},
13538 {"bits": [4, 7], "name": "S12_Y"},
13539 {"bits": [8, 11], "name": "S13_X"},
13540 {"bits": [12, 15], "name": "S13_Y"},
13541 {"bits": [16, 19], "name": "S14_X"},
13542 {"bits": [20, 23], "name": "S14_Y"},
13543 {"bits": [24, 27], "name": "S15_X"},
13544 {"bits": [28, 31], "name": "S15_Y"}
13549 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
13550 {"bits": [2, 2], "name": "BIN_SIZE_X"},
13551 {"bits": [3, 3], "name": "BIN_SIZE_Y"},
13552 {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
13553 {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
13554 {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
13555 {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
13556 {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
13557 {"bits": [19, 26], "name": "FPOVS_PER_BATCH"},
13558 {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"},
13559 {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"},
13560 {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"}
13565 {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"},
13566 {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"}
13571 {"bits": [0, 3], "name": "DISTANCE_0"},
13572 {"bits": [4, 7], "name": "DISTANCE_1"},
13573 {"bits": [8, 11], "name": "DISTANCE_2"},
13574 {"bits": [12, 15], "name": "DISTANCE_3"},
13575 {"bits": [16, 19], "name": "DISTANCE_4"},
13576 {"bits": [20, 23], "name": "DISTANCE_5"},
13577 {"bits": [24, 27], "name": "DISTANCE_6"},
13578 {"bits": [28, 31], "name": "DISTANCE_7"}
13583 {"bits": [0, 3], "name": "DISTANCE_8"},
13584 {"bits": [4, 7], "name": "DISTANCE_9"},
13585 {"bits": [8, 11], "name": "DISTANCE_10"},
13586 {"bits": [12, 15], "name": "DISTANCE_11"},
13587 {"bits": [16, 19], "name": "DISTANCE_12"},
13588 {"bits": [20, 23], "name": "DISTANCE_13"},
13589 {"bits": [24, 27], "name": "DISTANCE_14"},
13590 {"bits": [28, 31], "name": "DISTANCE_15"}
13595 {"bits": [0, 14], "name": "TL_X"},
13596 {"bits": [16, 30], "name": "TL_Y"}
13601 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
13606 {"bits": [0, 0], "name": "OVER_RAST_ENABLE"},
13607 {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"},
13608 {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"},
13609 {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"},
13610 {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"},
13611 {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"},
13612 {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"},
13613 {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
13614 {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
13615 {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
13616 {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
13617 {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13618 {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13619 {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},
13620 {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"},
13621 {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"},
13622 {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"},
13623 {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"},
13624 {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"},
13625 {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"}
13630 {"bits": [0, 3], "name": "ER_TRI"},
13631 {"bits": [4, 7], "name": "ER_POINT"},
13632 {"bits": [8, 11], "name": "ER_RECT"},
13633 {"bits": [12, 17], "name": "ER_LINE_LR"},
13634 {"bits": [18, 23], "name": "ER_LINE_RL"},
13635 {"bits": [24, 27], "name": "ER_LINE_TB"},
13636 {"bits": [28, 31], "name": "ER_LINE_BT"}
13641 {"bits": [0, 7], "name": "TOP_QTR"},
13642 {"bits": [8, 15], "name": "TOP_HALF"},
13643 {"bits": [16, 23], "name": "BOT_HALF"},
13644 {"bits": [24, 31], "name": "BOT_QTR"}
13649 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
13650 {"bits": [10, 10], "name": "LAST_PIXEL"},
13651 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
13652 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"},
13653 {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"}
13658 {"bits": [0, 15], "name": "LINE_PATTERN"},
13659 {"bits": [16, 23], "name": "REPEAT_COUNT"},
13660 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
13661 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
13666 {"bits": [0, 3], "name": "CURRENT_PTR"},
13667 {"bits": [8, 15], "name": "CURRENT_COUNT"}
13672 {"bits": [0, 0], "name": "MSAA_ENABLE"},
13673 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
13674 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
13675 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"},
13676 {"bits": [4, 4], "name": "SCALE_LINE_WIDTH_PAD"},
13677 {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"},
13678 {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"}
13683 {"bits": [0, 0], "name": "WALK_SIZE"},
13684 {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
13685 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
13686 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
13687 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
13688 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
13689 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
13690 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
13691 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
13692 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
13693 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
13694 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
13695 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
13696 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
13697 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
13698 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
13699 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
13700 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
13701 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
13702 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
13703 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
13704 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
13705 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
13706 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
13711 {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"},
13712 {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"}
13717 {"bits": [0, 13], "name": "X_COORD"}
13722 {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
13723 {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
13728 {"bits": [0, 15], "name": "COUNT"}
13733 {"bits": [0, 13], "name": "Y_COORD"}
13738 {"bits": [0, 9], "name": "PERF_SEL"}
13743 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
13744 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
13745 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
13746 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
13747 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
13748 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
13749 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
13750 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
13751 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
13752 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
13753 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
13754 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
13755 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
13756 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
13757 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
13762 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
13763 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
13764 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
13769 {"bits": [0, 7], "name": "LEFT_QTR"},
13770 {"bits": [8, 15], "name": "LEFT_HALF"},
13771 {"bits": [16, 23], "name": "RIGHT_HALF"},
13772 {"bits": [24, 31], "name": "RIGHT_QTR"}
13777 {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
13778 {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
13783 {"bits": [0, 15], "name": "X"},
13784 {"bits": [16, 31], "name": "Y"}
13789 {"bits": [0, 15], "name": "BR_X"},
13790 {"bits": [16, 31], "name": "BR_Y"}
13795 {"bits": [0, 15], "name": "TL_X"},
13796 {"bits": [16, 31], "name": "TL_Y"}
13801 {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"},
13802 {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"},
13803 {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"},
13804 {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"}
13809 {"bits": [0, 0], "name": "ENABLE"},
13810 {"bits": [1, 2], "name": "NUM_SE"},
13811 {"bits": [5, 6], "name": "NUM_RB_PER_SE"},
13812 {"bits": [8, 8], "name": "DISABLE_SRBSL_DB_OPTIMIZED_PACKING"},
13813 {"bits": [12, 13], "name": "NUM_SC"},
13814 {"bits": [16, 17], "name": "NUM_RB_PER_SC"},
13815 {"bits": [20, 20], "name": "NUM_PACKER_PER_SC"}
13820 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
13821 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
13826 {"bits": [0, 14], "name": "BR_X"},
13827 {"bits": [16, 30], "name": "BR_Y"}
13832 {"bits": [0, 14], "name": "TL_X"},
13833 {"bits": [16, 30], "name": "TL_Y"},
13834 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
13839 {"bits": [1, 4], "name": "STEREO_MODE"},
13840 {"bits": [5, 7], "name": "RT_SLICE_MODE"},
13841 {"bits": [8, 11], "name": "RT_SLICE_OFFSET"},
13842 {"bits": [16, 18], "name": "VP_ID_MODE"},
13843 {"bits": [19, 22], "name": "VP_ID_OFFSET"}
13848 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
13849 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
13854 {"bits": [0, 15], "name": "WIDTH"}
13859 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
13860 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
13861 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
13862 {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
13867 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
13872 {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"},
13873 {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"},
13874 {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"},
13875 {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"},
13876 {"bits": [4, 4], "name": "USE_PROVOKING_ZW"}
13881 {"bits": [0, 15], "name": "PERFCOUNTER_HI"}
13886 {"bits": [0, 9], "name": "PERF_SEL"},
13887 {"bits": [10, 19], "name": "PERF_SEL1"},
13888 {"bits": [20, 23], "name": "CNTR_MODE"},
13889 {"bits": [24, 27], "name": "PERF_MODE1"},
13890 {"bits": [28, 31], "name": "PERF_MODE"}
13895 {"bits": [0, 9], "name": "PERF_SEL2"},
13896 {"bits": [10, 19], "name": "PERF_SEL3"},
13897 {"bits": [24, 27], "name": "PERF_MODE3"},
13898 {"bits": [28, 31], "name": "PERF_MODE2"}
13903 {"bits": [0, 15], "name": "MIN_SIZE"},
13904 {"bits": [16, 31], "name": "MAX_SIZE"}
13909 {"bits": [0, 15], "name": "HEIGHT"},
13910 {"bits": [16, 31], "name": "WIDTH"}
13915 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
13916 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
13921 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
13922 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
13923 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
13924 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
13925 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
13926 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
13927 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
13928 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
13929 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
13930 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
13931 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
13936 {"bits": [0, 0], "name": "CULL_FRONT"},
13937 {"bits": [1, 1], "name": "CULL_BACK"},
13938 {"bits": [2, 2], "name": "FACE"},
13939 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
13940 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
13941 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
13942 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
13943 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
13944 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
13945 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
13946 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
13947 {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
13948 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"},
13949 {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"},
13950 {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"},
13951 {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"}
13956 {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"},
13957 {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"},
13958 {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"},
13959 {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"},
13960 {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"},
13961 {"bits": [5, 5], "name": "SRBSL_ENABLE"},
13962 {"bits": [6, 6], "name": "SC_1XMSAA_COMPATIBLE_DISABLE"}
13967 {"bits": [0, 0], "name": "PIX_CENTER"},
13968 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
13969 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
13974 {"bits": [0, 3], "name": "FEATURE_SEL"},
13975 {"bits": [4, 7], "name": "SE_INDEX"},
13976 {"bits": [8, 11], "name": "SA_INDEX"},
13977 {"bits": [12, 15], "name": "WGP_INDEX"},
13978 {"bits": [16, 17], "name": "EVENT_SEL"},
13979 {"bits": [18, 19], "name": "UNUSED"},
13980 {"bits": [20, 20], "name": "ENABLE"},
13981 {"bits": [21, 31], "name": "RESERVED"}
13986 {"bits": [0, 0], "name": "ENABLE"},
13987 {"bits": [1, 1], "name": "MODE_SELECT"},
13988 {"bits": [2, 2], "name": "RESET"},
13989 {"bits": [3, 31], "name": "RESERVED"}
13994 {"bits": [0, 3], "name": "VFID"},
13995 {"bits": [4, 5], "name": "CNT_ID"},
13996 {"bits": [6, 31], "name": "RESERVED"}
14001 {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
14006 {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
14011 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
14012 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
14017 {"bits": [0, 0], "name": "StrobeResetPerfMonitors"},
14018 {"bits": [1, 1], "name": "StrobeStartAccumulation"},
14019 {"bits": [2, 2], "name": "StrobeRearmAccum"},
14020 {"bits": [3, 3], "name": "StrobeSpmDoneInt"},
14021 {"bits": [4, 4], "name": "StrobeAccumDoneInt"},
14022 {"bits": [5, 5], "name": "StrobeResetAccum"},
14023 {"bits": [6, 9], "name": "StrobeStartSpm"},
14024 {"bits": [10, 31], "name": "RESERVED"}
14029 {"bits": [0, 8], "name": "addr"},
14030 {"bits": [9, 31], "name": "RESERVED"}
14035 {"bits": [0, 7], "name": "data"},
14036 {"bits": [8, 31], "name": "RESERVED"}
14041 {"bits": [0, 6], "name": "addr"},
14042 {"bits": [7, 31], "name": "RESERVED"}
14047 {"bits": [0, 18], "name": "DataRamWrCount"},
14048 {"bits": [19, 31], "name": "RESERVED"}
14053 {"bits": [0, 0], "name": "EnableAccum"},
14054 {"bits": [1, 1], "name": "AutoAccumEn"},
14055 {"bits": [2, 2], "name": "AutoSpmEn"},
14056 {"bits": [3, 3], "name": "Globals_LoadOverride"},
14057 {"bits": [4, 4], "name": "SE0_LoadOverride"},
14058 {"bits": [5, 5], "name": "SE1_LoadOverride"},
14059 {"bits": [6, 6], "name": "AutoResetPerfmonDisable"},
14060 {"bits": [7, 31], "name": "RESERVED"}
14065 {"bits": [0, 7], "name": "SamplesRequested"},
14066 {"bits": [8, 31], "name": "RESERVED"}
14071 {"bits": [0, 7], "name": "NumbSamplesCompleted"},
14072 {"bits": [8, 8], "name": "AccumDone"},
14073 {"bits": [9, 9], "name": "SpmDone"},
14074 {"bits": [10, 10], "name": "AccumOverflow"},
14075 {"bits": [11, 11], "name": "AccumArmed"},
14076 {"bits": [12, 12], "name": "SequenceInProgress"},
14077 {"bits": [13, 13], "name": "FinalSequenceInProgress"},
14078 {"bits": [14, 14], "name": "AllFifosEmpty"},
14079 {"bits": [15, 15], "name": "FSMIsIdle"},
14080 {"bits": [16, 31], "name": "RESERVED"}
14085 {"bits": [0, 15], "name": "Threshold"},
14086 {"bits": [16, 31], "name": "RESERVED"}
14091 {"bits": [0, 6], "name": "DESER_START_SKEW"},
14092 {"bits": [7, 31], "name": "RESERVED"}
14097 {"bits": [0, 6], "name": "data"},
14098 {"bits": [7, 31], "name": "RESERVED"}
14103 {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"},
14104 {"bits": [7, 31], "name": "RESERVED"}
14109 {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"},
14110 {"bits": [7, 31], "name": "RESERVED"}
14115 {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"},
14116 {"bits": [8, 31], "name": "RESERVED"}
14121 {"bits": [0, 11], "name": "RESERVED1"},
14122 {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
14123 {"bits": [14, 15], "name": "RESERVED"},
14124 {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
14129 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
14130 {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"},
14131 {"bits": [16, 31], "name": "RESERVED"}
14136 {"bits": [0, 15], "name": "RING_BASE_HI"},
14137 {"bits": [16, 31], "name": "RESERVED"}
14142 {"bits": [0, 7], "name": "SE0_NUM_LINE"},
14143 {"bits": [8, 15], "name": "SE1_NUM_LINE"},
14144 {"bits": [16, 23], "name": "SE2_NUM_LINE"},
14145 {"bits": [24, 31], "name": "SE3_NUM_LINE"}
14150 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
14151 {"bits": [8, 10], "name": "RESERVED1"},
14152 {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
14153 {"bits": [16, 20], "name": "SE0_NUM_LINE"},
14154 {"bits": [21, 25], "name": "SE1_NUM_LINE"},
14155 {"bits": [26, 30], "name": "SE2_NUM_LINE"},
14156 {"bits": [31, 31], "name": "RESERVED"}
14161 {"bits": [0, 4], "name": "RESERVED"},
14162 {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"}
14167 {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"},
14168 {"bits": [8, 31], "name": "RESERVED"}
14173 {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"},
14174 {"bits": [9, 31], "name": "RESERVED"}
14179 {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"},
14180 {"bits": [7, 31], "name": "RESERVED"}
14185 {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"},
14186 {"bits": [7, 31], "name": "RESERVED"}
14191 {"bits": [0, 0], "name": "PauseSpmSamplingRequest"}
14196 {"bits": [0, 0], "name": "SpmSamplingPaused"}
14201 {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"},
14202 {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"},
14203 {"bits": [4, 5], "name": "TC_PERF_EN_SEL"},
14204 {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"},
14205 {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"},
14206 {"bits": [10, 13], "name": "PERF_COUNTER_CID"},
14207 {"bits": [14, 18], "name": "PERF_COUNTER_VMID"},
14208 {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"},
14209 {"bits": [25, 25], "name": "PERF_SOFT_RESET"},
14210 {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"}
14215 {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
14216 {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
14221 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
14222 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
14223 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
14224 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
14225 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
14226 {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
14227 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
14232 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
14233 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
14234 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
14235 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
14236 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},
14237 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"},
14238 {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"},
14239 {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"},
14240 {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"}
14245 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
14246 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
14247 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
14248 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
14249 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
14250 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
14251 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
14256 {"bits": [0, 3], "name": "BIN0_MIN"},
14257 {"bits": [4, 7], "name": "BIN0_MAX"},
14258 {"bits": [8, 11], "name": "BIN1_MIN"},
14259 {"bits": [12, 15], "name": "BIN1_MAX"},
14260 {"bits": [16, 19], "name": "BIN2_MIN"},
14261 {"bits": [20, 23], "name": "BIN2_MAX"},
14262 {"bits": [24, 27], "name": "BIN3_MIN"},
14263 {"bits": [28, 31], "name": "BIN3_MAX"}
14268 {"bits": [0, 5], "name": "OFFSET"},
14269 {"bits": [8, 9], "name": "DEFAULT_VAL"},
14270 {"bits": [10, 10], "name": "FLAT_SHADE"},
14271 {"bits": [13, 16], "name": "CYL_WRAP"},
14272 {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
14273 {"bits": [18, 18], "name": "DUP"},
14274 {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
14275 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
14276 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
14277 {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
14278 {"bits": [24, 24], "name": "ATTR0_VALID"},
14279 {"bits": [25, 25], "name": "ATTR1_VALID"}
14284 {"bits": [0, 5], "name": "OFFSET"},
14285 {"bits": [8, 9], "name": "DEFAULT_VAL"},
14286 {"bits": [10, 10], "name": "FLAT_SHADE"},
14287 {"bits": [18, 18], "name": "DUP"},
14288 {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
14289 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
14290 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
14291 {"bits": [24, 24], "name": "ATTR0_VALID"},
14292 {"bits": [25, 25], "name": "ATTR1_VALID"}
14297 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
14298 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
14299 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
14300 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
14301 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
14302 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
14303 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
14304 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
14305 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
14306 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
14307 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
14308 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
14309 {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
14310 {"bits": [13, 13], "name": "ANCILLARY_ENA"},
14311 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
14312 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
14317 {"bits": [0, 5], "name": "NUM_INTERP"},
14318 {"bits": [6, 6], "name": "PARAM_GEN"},
14319 {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"},
14320 {"bits": [8, 8], "name": "LATE_PC_DEALLOC"},
14321 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"},
14322 {"bits": [15, 15], "name": "PS_W32_EN"}
14327 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
14328 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
14329 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
14330 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
14331 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
14332 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
14333 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
14334 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
14339 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"}
14344 {"bits": [0, 5], "name": "LIMIT"}
14349 {"bits": [0, 7], "name": "MEM_BASE"}
14354 {"bits": [0, 5], "name": "VGPRS"},
14355 {"bits": [6, 9], "name": "SGPRS"},
14356 {"bits": [10, 11], "name": "PRIORITY"},
14357 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14358 {"bits": [20, 20], "name": "PRIV"},
14359 {"bits": [21, 21], "name": "DX10_CLAMP"},
14360 {"bits": [23, 23], "name": "IEEE_MODE"},
14361 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
14362 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
14363 {"bits": [31, 31], "name": "FP16_OVFL"}
14368 {"bits": [0, 5], "name": "VGPRS"},
14369 {"bits": [6, 9], "name": "SGPRS"},
14370 {"bits": [10, 11], "name": "PRIORITY"},
14371 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14372 {"bits": [20, 20], "name": "PRIV"},
14373 {"bits": [21, 21], "name": "DX10_CLAMP"},
14374 {"bits": [23, 23], "name": "IEEE_MODE"},
14375 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
14376 {"bits": [25, 25], "name": "MEM_ORDERED"},
14377 {"bits": [26, 26], "name": "FWD_PROGRESS"},
14378 {"bits": [27, 27], "name": "WGP_MODE"},
14379 {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"},
14380 {"bits": [31, 31], "name": "FP16_OVFL"}
14385 {"bits": [0, 5], "name": "VGPRS"},
14386 {"bits": [6, 9], "name": "SGPRS"},
14387 {"bits": [10, 11], "name": "PRIORITY"},
14388 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14389 {"bits": [20, 20], "name": "PRIV"},
14390 {"bits": [21, 21], "name": "DX10_CLAMP"},
14391 {"bits": [23, 23], "name": "IEEE_MODE"},
14392 {"bits": [24, 24], "name": "MEM_ORDERED"},
14393 {"bits": [25, 25], "name": "FWD_PROGRESS"},
14394 {"bits": [26, 26], "name": "WGP_MODE"},
14395 {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"},
14396 {"bits": [30, 30], "name": "FP16_OVFL"}
14401 {"bits": [0, 5], "name": "VGPRS"},
14402 {"bits": [6, 9], "name": "SGPRS"},
14403 {"bits": [10, 11], "name": "PRIORITY"},
14404 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14405 {"bits": [20, 20], "name": "PRIV"},
14406 {"bits": [21, 21], "name": "DX10_CLAMP"},
14407 {"bits": [23, 23], "name": "IEEE_MODE"},
14408 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
14409 {"bits": [30, 30], "name": "FP16_OVFL"}
14414 {"bits": [0, 5], "name": "VGPRS"},
14415 {"bits": [6, 9], "name": "SGPRS"},
14416 {"bits": [10, 11], "name": "PRIORITY"},
14417 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14418 {"bits": [20, 20], "name": "PRIV"},
14419 {"bits": [21, 21], "name": "DX10_CLAMP"},
14420 {"bits": [23, 23], "name": "IEEE_MODE"},
14421 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
14422 {"bits": [25, 25], "name": "MEM_ORDERED"},
14423 {"bits": [26, 26], "name": "FWD_PROGRESS"},
14424 {"bits": [29, 29], "name": "FP16_OVFL"}
14429 {"bits": [0, 5], "name": "VGPRS"},
14430 {"bits": [6, 9], "name": "SGPRS"},
14431 {"bits": [10, 11], "name": "PRIORITY"},
14432 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14433 {"bits": [20, 20], "name": "PRIV"},
14434 {"bits": [21, 21], "name": "DX10_CLAMP"},
14435 {"bits": [23, 23], "name": "IEEE_MODE"},
14436 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
14437 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
14438 {"bits": [27, 27], "name": "MEM_ORDERED"},
14439 {"bits": [28, 28], "name": "FWD_PROGRESS"},
14440 {"bits": [31, 31], "name": "FP16_OVFL"}
14445 {"bits": [0, 0], "name": "SCRATCH_EN"},
14446 {"bits": [1, 5], "name": "USER_SGPR"},
14447 {"bits": [6, 6], "name": "TRAP_PRESENT"},
14448 {"bits": [7, 7], "name": "OC_LDS_EN"},
14449 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14450 {"bits": [20, 28], "name": "LDS_SIZE"}
14455 {"bits": [0, 0], "name": "SCRATCH_EN"},
14456 {"bits": [1, 5], "name": "USER_SGPR"},
14457 {"bits": [6, 6], "name": "TRAP_PRESENT"},
14458 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14459 {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"},
14460 {"bits": [18, 18], "name": "OC_LDS_EN"},
14461 {"bits": [19, 26], "name": "LDS_SIZE"},
14462 {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14463 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14468 {"bits": [0, 0], "name": "SCRATCH_EN"},
14469 {"bits": [1, 5], "name": "USER_SGPR"},
14470 {"bits": [6, 6], "name": "TRAP_PRESENT"},
14471 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14472 {"bits": [16, 17], "name": "VGPR_COMP_CNT"},
14473 {"bits": [18, 18], "name": "OC_LDS_EN"},
14474 {"bits": [19, 26], "name": "LDS_SIZE"},
14475 {"bits": [27, 27], "name": "SKIP_USGPR0"},
14476 {"bits": [28, 28], "name": "USER_SGPR_MSB"}
14481 {"bits": [0, 0], "name": "SCRATCH_EN"},
14482 {"bits": [1, 5], "name": "USER_SGPR"},
14483 {"bits": [6, 6], "name": "TRAP_PRESENT"},
14484 {"bits": [7, 7], "name": "OC_LDS_EN"},
14485 {"bits": [8, 8], "name": "TG_SIZE_EN"},
14486 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14487 {"bits": [18, 26], "name": "LDS_SIZE"},
14488 {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14489 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14494 {"bits": [0, 0], "name": "SCRATCH_EN"},
14495 {"bits": [1, 5], "name": "USER_SGPR"},
14496 {"bits": [6, 6], "name": "TRAP_PRESENT"},
14497 {"bits": [7, 15], "name": "LDS_SIZE"},
14498 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
14503 {"bits": [0, 0], "name": "SCRATCH_EN"},
14504 {"bits": [1, 5], "name": "USER_SGPR"},
14505 {"bits": [6, 6], "name": "TRAP_PRESENT"},
14506 {"bits": [7, 7], "name": "WAVE_CNT_EN"},
14507 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
14508 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14509 {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"},
14510 {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"},
14511 {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14512 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14517 {"bits": [0, 0], "name": "SCRATCH_EN"},
14518 {"bits": [1, 5], "name": "USER_SGPR"},
14519 {"bits": [6, 6], "name": "TRAP_PRESENT"},
14520 {"bits": [7, 7], "name": "OC_LDS_EN"},
14521 {"bits": [8, 8], "name": "SO_BASE0_EN"},
14522 {"bits": [9, 9], "name": "SO_BASE1_EN"},
14523 {"bits": [10, 10], "name": "SO_BASE2_EN"},
14524 {"bits": [11, 11], "name": "SO_BASE3_EN"},
14525 {"bits": [12, 12], "name": "SO_EN"},
14526 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14527 {"bits": [22, 22], "name": "PC_BASE_EN"},
14528 {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"},
14529 {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14530 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14535 {"bits": [0, 15], "name": "CU_EN"},
14536 {"bits": [16, 21], "name": "WAVE_LIMIT"},
14537 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
14538 {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
14543 {"bits": [0, 5], "name": "WAVE_LIMIT"},
14544 {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
14545 {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"},
14546 {"bits": [16, 31], "name": "CU_EN"}
14551 {"bits": [0, 15], "name": "CU_EN"},
14552 {"bits": [16, 21], "name": "WAVE_LIMIT"},
14553 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
14558 {"bits": [0, 15], "name": "CU_EN"},
14559 {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"}
14564 {"bits": [0, 15], "name": "CU_EN"}
14569 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
14570 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
14571 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
14572 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"},
14573 {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"}
14578 {"bits": [0, 2], "name": "TOTAL_WAVE_COUNT_HIER_SELECT"},
14579 {"bits": [3, 5], "name": "PER_TYPE_WAVE_COUNT_HIER_SELECT"},
14580 {"bits": [6, 6], "name": "GROUP_UPDATE_EN"},
14581 {"bits": [8, 15], "name": "TOTAL_WAVE_COUNT_COEFFICIENT"},
14582 {"bits": [16, 23], "name": "PER_TYPE_WAVE_COUNT_COEFFICIENT"}
14587 {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
14588 {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
14589 {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
14590 {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
14591 {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
14592 {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
14593 {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
14594 {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}
14599 {"bits": [0, 6], "name": "CONTRIBUTION"}
14604 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
14609 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
14610 {"bits": [6, 6], "name": "VS_HALF_PACK"},
14611 {"bits": [7, 7], "name": "NO_PC_EXPORT"}
14616 {"bits": [0, 0], "name": "TARGET_INST"},
14617 {"bits": [1, 1], "name": "TARGET_DATA"},
14618 {"bits": [2, 2], "name": "INVALIDATE"},
14619 {"bits": [3, 3], "name": "WRITEBACK"},
14620 {"bits": [4, 4], "name": "VOL"},
14621 {"bits": [16, 16], "name": "COMPLETE"},
14622 {"bits": [17, 18], "name": "L2_WB_POLICY"}
14627 {"bits": [0, 0], "name": "DWB"},
14628 {"bits": [1, 1], "name": "DIRTY"}
14633 {"bits": [0, 8], "name": "PERF_SEL"},
14634 {"bits": [12, 15], "name": "SQC_BANK_MASK"},
14635 {"bits": [20, 23], "name": "SPM_MODE"},
14636 {"bits": [28, 31], "name": "PERF_MODE"}
14641 {"bits": [0, 0], "name": "PS_EN"},
14642 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
14643 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
14644 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
14645 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
14646 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
14647 {"bits": [6, 6], "name": "CS_EN"},
14648 {"bits": [8, 9], "name": "CNTR_RATE"},
14649 {"bits": [13, 13], "name": "DISABLE_FLUSH"}
14654 {"bits": [0, 0], "name": "FORCE_EN"}
14659 {"bits": [0, 3], "name": "BASE_HI"},
14660 {"bits": [8, 29], "name": "SIZE"}
14665 {"bits": [0, 1], "name": "MODE"},
14666 {"bits": [2, 2], "name": "ALL_VMID"},
14667 {"bits": [3, 3], "name": "CH_PERF_EN"},
14668 {"bits": [4, 4], "name": "INTERRUPT_EN"},
14669 {"bits": [5, 5], "name": "DOUBLE_BUFFER"},
14670 {"bits": [6, 8], "name": "HIWATER"},
14671 {"bits": [9, 9], "name": "REG_STALL_EN"},
14672 {"bits": [10, 10], "name": "SPI_STALL_EN"},
14673 {"bits": [11, 11], "name": "SQ_STALL_EN"},
14674 {"bits": [12, 12], "name": "REG_DROP_ON_STALL"},
14675 {"bits": [13, 13], "name": "UTIL_TIMER"},
14676 {"bits": [14, 15], "name": "WAVESTART_MODE"},
14677 {"bits": [16, 17], "name": "RT_FREQ"},
14678 {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"},
14679 {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"},
14680 {"bits": [30, 30], "name": "CAPTURE_ALL"},
14681 {"bits": [31, 31], "name": "DRAW_EVENT_EN"}
14686 {"bits": [0, 1], "name": "SIMD_SEL"},
14687 {"bits": [4, 7], "name": "WGP_SEL"},
14688 {"bits": [9, 9], "name": "SA_SEL"},
14689 {"bits": [10, 16], "name": "WTYPE_INCLUDE"}
14694 {"bits": [0, 11], "name": "FINISH_PENDING"},
14695 {"bits": [12, 23], "name": "FINISH_DONE"},
14696 {"bits": [24, 24], "name": "UTC_ERR"},
14697 {"bits": [25, 25], "name": "BUSY"},
14698 {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"},
14699 {"bits": [27, 27], "name": "EVENT_CNTR_STALL"}
14704 {"bits": [0, 11], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
14705 {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
14706 {"bits": [24, 25], "name": "INST_EXCLUDE"},
14707 {"bits": [31, 31], "name": "REG_DETAIL_ALL"}
14712 {"bits": [0, 28], "name": "OFFSET"},
14713 {"bits": [31, 31], "name": "BUFFER_ID"}
14718 {"bits": [0, 7], "name": "VGPR_BASE"},
14719 {"bits": [8, 15], "name": "VGPR_SIZE"},
14720 {"bits": [16, 23], "name": "SGPR_BASE"},
14721 {"bits": [24, 27], "name": "SGPR_SIZE"}
14726 {"bits": [0, 4], "name": "WAVE_ID"},
14727 {"bits": [8, 9], "name": "SIMD_ID"},
14728 {"bits": [10, 13], "name": "WGP_ID"},
14729 {"bits": [16, 16], "name": "SA_ID"},
14730 {"bits": [18, 19], "name": "SE_ID"}
14735 {"bits": [0, 3], "name": "QUEUE_ID"},
14736 {"bits": [4, 5], "name": "PIPE_ID"},
14737 {"bits": [8, 9], "name": "ME_ID"},
14738 {"bits": [12, 14], "name": "STATE_ID"},
14739 {"bits": [16, 20], "name": "WG_ID"},
14740 {"bits": [24, 27], "name": "VM_ID"},
14741 {"bits": [29, 30], "name": "COMPAT_LEVEL"}
14746 {"bits": [0, 3], "name": "WAVE_ID"},
14747 {"bits": [4, 5], "name": "SIMD_ID"},
14748 {"bits": [6, 7], "name": "PIPE_ID"},
14749 {"bits": [8, 11], "name": "CU_ID"},
14750 {"bits": [12, 12], "name": "SH_ID"},
14751 {"bits": [13, 14], "name": "SE_ID"},
14752 {"bits": [15, 15], "name": "WAVE_ID_MSB"},
14753 {"bits": [16, 19], "name": "TG_ID"},
14754 {"bits": [20, 23], "name": "VM_ID"},
14755 {"bits": [24, 26], "name": "QUEUE_ID"},
14756 {"bits": [27, 29], "name": "STATE_ID"},
14757 {"bits": [30, 31], "name": "ME_ID"}
14762 {"bits": [0, 0], "name": "XNACK_ERROR"},
14763 {"bits": [1, 1], "name": "XNACK"},
14764 {"bits": [2, 2], "name": "TA_NEED_RESET"},
14765 {"bits": [3, 3], "name": "XNACK_OVERRIDE"},
14766 {"bits": [4, 9], "name": "XCNT"},
14767 {"bits": [11, 16], "name": "QCNT"},
14768 {"bits": [18, 23], "name": "RCNT"},
14769 {"bits": [24, 24], "name": "WAVE_IDLE"},
14770 {"bits": [25, 31], "name": "MISC_CNT"}
14775 {"bits": [0, 3], "name": "VM_CNT"},
14776 {"bits": [4, 6], "name": "EXP_CNT"},
14777 {"bits": [7, 7], "name": "LGKM_CNT_BIT4"},
14778 {"bits": [8, 11], "name": "LGKM_CNT"},
14779 {"bits": [12, 14], "name": "VALU_CNT"},
14780 {"bits": [15, 15], "name": "FIRST_REPLAY"},
14781 {"bits": [16, 21], "name": "RCNT"},
14782 {"bits": [22, 23], "name": "VM_CNT_HI"},
14783 {"bits": [24, 24], "name": "LGKM_CNT_BIT5"},
14784 {"bits": [25, 25], "name": "REPLAY_W64H"},
14785 {"bits": [26, 31], "name": "VS_CNT"}
14790 {"bits": [0, 1], "name": "INST_PREFETCH"},
14791 {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"},
14792 {"bits": [8, 9], "name": "MEM_ORDER"},
14793 {"bits": [10, 10], "name": "FWD_PROGRESS"},
14794 {"bits": [11, 11], "name": "WAVE64"},
14795 {"bits": [12, 12], "name": "WAVE64HI"},
14796 {"bits": [13, 13], "name": "SUBV_LOOP"}
14801 {"bits": [0, 8], "name": "LDS_BASE"},
14802 {"bits": [12, 20], "name": "LDS_SIZE"},
14803 {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"}
14808 {"bits": [0, 3], "name": "FP_ROUND"},
14809 {"bits": [4, 7], "name": "FP_DENORM"},
14810 {"bits": [8, 8], "name": "DX10_CLAMP"},
14811 {"bits": [9, 9], "name": "IEEE"},
14812 {"bits": [10, 10], "name": "LOD_CLAMPED"},
14813 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14814 {"bits": [23, 23], "name": "FP16_OVFL"},
14815 {"bits": [27, 27], "name": "DISABLE_PERF"},
14816 {"bits": [28, 28], "name": "VSKIP"},
14817 {"bits": [29, 31], "name": "CSP"}
14822 {"bits": [0, 15], "name": "PC_HI"}
14827 {"bits": [0, 0], "name": "POPS_EN"},
14828 {"bits": [1, 2], "name": "POPS_PACKER_ID"}
14833 {"bits": [0, 1], "name": "DEP_MODE"}
14838 {"bits": [0, 0], "name": "SCC"},
14839 {"bits": [1, 2], "name": "SPI_PRIO"},
14840 {"bits": [3, 4], "name": "USER_PRIO"},
14841 {"bits": [5, 5], "name": "PRIV"},
14842 {"bits": [6, 6], "name": "TRAP_EN"},
14843 {"bits": [7, 7], "name": "TTRACE_EN"},
14844 {"bits": [8, 8], "name": "EXPORT_RDY"},
14845 {"bits": [9, 9], "name": "EXECZ"},
14846 {"bits": [10, 10], "name": "VCCZ"},
14847 {"bits": [11, 11], "name": "IN_TG"},
14848 {"bits": [12, 12], "name": "IN_BARRIER"},
14849 {"bits": [13, 13], "name": "HALT"},
14850 {"bits": [14, 14], "name": "TRAP"},
14851 {"bits": [15, 15], "name": "TTRACE_SIMD_EN"},
14852 {"bits": [16, 16], "name": "VALID"},
14853 {"bits": [17, 17], "name": "ECC_ERR"},
14854 {"bits": [18, 18], "name": "SKIP_EXPORT"},
14855 {"bits": [19, 19], "name": "PERF_EN"},
14856 {"bits": [23, 23], "name": "FATAL_HALT"},
14857 {"bits": [27, 27], "name": "MUST_EXPORT"}
14862 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
14863 {"bits": [10, 10], "name": "SAVECTX"},
14864 {"bits": [11, 11], "name": "ILLEGAL_INST"},
14865 {"bits": [12, 14], "name": "EXCP_HI"},
14866 {"bits": [15, 15], "name": "BUFFER_OOB"},
14867 {"bits": [16, 19], "name": "EXCP_CYCLE"},
14868 {"bits": [20, 23], "name": "EXCP_GROUP_MASK"},
14869 {"bits": [24, 24], "name": "EXCP_WAVE64HI"},
14870 {"bits": [28, 28], "name": "XNACK_ERROR"},
14871 {"bits": [29, 31], "name": "DP_RATE"}
14876 {"bits": [0, 5], "name": "SRC0"},
14877 {"bits": [6, 11], "name": "SRC1"},
14878 {"bits": [12, 17], "name": "SRC2"},
14879 {"bits": [18, 23], "name": "DST"}
14884 {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
14885 {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
14886 {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
14887 {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
14888 {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
14889 {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
14890 {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
14891 {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
14892 {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
14893 {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
14894 {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
14895 {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
14896 {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
14897 {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
14898 {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
14899 {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
14900 {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
14905 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
14906 {"bits": [4, 7], "name": "MRT1_EPSILON"},
14907 {"bits": [8, 11], "name": "MRT2_EPSILON"},
14908 {"bits": [12, 15], "name": "MRT3_EPSILON"},
14909 {"bits": [16, 19], "name": "MRT4_EPSILON"},
14910 {"bits": [20, 23], "name": "MRT5_EPSILON"},
14911 {"bits": [24, 27], "name": "MRT6_EPSILON"},
14912 {"bits": [28, 31], "name": "MRT7_EPSILON"}
14917 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
14918 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
14919 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
14920 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
14921 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
14922 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
14927 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"},
14928 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"},
14929 {"bits": [20, 23], "name": "CNTR_MODE"}
14934 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"},
14935 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"}
14940 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
14941 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
14942 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
14943 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
14944 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
14945 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
14946 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
14947 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
14952 {"bits": [0, 7], "name": "ADDRESS"}
14957 {"bits": [0, 7], "name": "PERF_SEL"},
14958 {"bits": [10, 17], "name": "PERF_SEL1"},
14959 {"bits": [20, 23], "name": "CNTR_MODE"},
14960 {"bits": [24, 27], "name": "PERF_MODE1"},
14961 {"bits": [28, 31], "name": "PERF_MODE"}
14966 {"bits": [0, 7], "name": "PERF_SEL2"},
14967 {"bits": [10, 17], "name": "PERF_SEL3"},
14968 {"bits": [24, 27], "name": "PERF_MODE3"},
14969 {"bits": [28, 31], "name": "PERF_MODE2"}
14974 {"bits": [0, 7], "name": "PERF_SEL"},
14975 {"bits": [20, 23], "name": "CNTR_MODE"},
14976 {"bits": [28, 31], "name": "PERF_MODE"}
14981 {"bits": [0, 9], "name": "PERF_SEL"},
14982 {"bits": [20, 23], "name": "CNTR_MODE"},
14983 {"bits": [28, 31], "name": "PERF_MODE"}
14988 {"bits": [0, 9], "name": "PERF_SEL"},
14989 {"bits": [28, 31], "name": "COUNTER_MODE"}
14994 {"bits": [0, 15], "name": "BASE_ADDR"}
14999 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
15000 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
15001 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
15002 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
15003 {"bits": [8, 8], "name": "ATC"},
15004 {"bits": [9, 9], "name": "NOT_EOP"},
15005 {"bits": [10, 10], "name": "REQ_PATH"},
15006 {"bits": [11, 13], "name": "MTYPE"}
15011 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
15012 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
15013 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
15014 {"bits": [5, 5], "name": "NOT_EOP"},
15015 {"bits": [6, 6], "name": "USE_OPAQUE"},
15016 {"bits": [7, 7], "name": "UNROLLED_INST"},
15017 {"bits": [8, 8], "name": "GRBM_SKEW_NO_DEC"},
15018 {"bits": [29, 31], "name": "REG_RT_INDEX"}
15023 {"bits": [0, 0], "name": "OBJPRIM_ID_EN"},
15024 {"bits": [1, 1], "name": "EN_REG_RT_INDEX"},
15025 {"bits": [2, 2], "name": "OBJECT_ID_INST_EN"},
15026 {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"},
15027 {"bits": [4, 4], "name": "EN_DRAW_VP"}
15032 {"bits": [0, 14], "name": "ITEMSIZE"}
15037 {"bits": [0, 10], "name": "ES_PER_GS"}
15042 {"bits": [0, 27], "name": "ADDRESS_LOW"}
15047 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
15048 {"bits": [10, 26], "name": "ADDRESS_HI"},
15049 {"bits": [27, 27], "name": "EXTENDED_EVENT"}
15054 {"bits": [0, 3], "name": "DECR"}
15059 {"bits": [0, 3], "name": "FIRST_DECR"}
15064 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
15065 {"bits": [14, 14], "name": "RETAIN_ORDER"},
15066 {"bits": [15, 15], "name": "RETAIN_QUADS"},
15067 {"bits": [16, 18], "name": "PRIM_ORDER"}
15072 {"bits": [0, 0], "name": "COMP_X_EN"},
15073 {"bits": [1, 1], "name": "COMP_Y_EN"},
15074 {"bits": [2, 2], "name": "COMP_Z_EN"},
15075 {"bits": [3, 3], "name": "COMP_W_EN"},
15076 {"bits": [8, 15], "name": "STRIDE"},
15077 {"bits": [16, 23], "name": "SHIFT"}
15082 {"bits": [0, 3], "name": "X_CONV"},
15083 {"bits": [4, 7], "name": "X_OFFSET"},
15084 {"bits": [8, 11], "name": "Y_CONV"},
15085 {"bits": [12, 15], "name": "Y_OFFSET"},
15086 {"bits": [16, 19], "name": "Z_CONV"},
15087 {"bits": [20, 23], "name": "Z_OFFSET"},
15088 {"bits": [24, 27], "name": "W_CONV"},
15089 {"bits": [28, 31], "name": "W_OFFSET"}
15094 {"bits": [0, 14], "name": "OFFSET"}
15099 {"bits": [0, 0], "name": "ENABLE"},
15100 {"bits": [2, 8], "name": "CNT"},
15101 {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"}
15106 {"bits": [0, 10], "name": "MAX_VERT_OUT"}
15111 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
15112 {"bits": [3, 3], "name": "RESERVED_0"},
15113 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
15114 {"bits": [6, 10], "name": "RESERVED_1"},
15115 {"bits": [11, 11], "name": "GS_C_PACK_EN"},
15116 {"bits": [12, 12], "name": "RESERVED_2"},
15117 {"bits": [13, 13], "name": "ES_PASSTHRU"},
15118 {"bits": [14, 14], "name": "COMPUTE_MODE"},
15119 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"},
15120 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"},
15121 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
15122 {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
15123 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
15124 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
15125 {"bits": [21, 22], "name": "ONCHIP"}
15130 {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
15131 {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"},
15132 {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"}
15137 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
15138 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
15139 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
15140 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
15141 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
15146 {"bits": [0, 10], "name": "GS_PER_ES"}
15151 {"bits": [0, 3], "name": "GS_PER_VS"}
15156 {"bits": [0, 1], "name": "TESS_MODE"}
15161 {"bits": [0, 7], "name": "REUSE_DEPTH"}
15166 {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},
15167 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
15172 {"bits": [0, 7], "name": "NUM_PATCHES"},
15173 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
15174 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
15179 {"bits": [0, 0], "name": "RESET_EN"},
15180 {"bits": [1, 1], "name": "MATCH_ALL_BITS"}
15185 {"bits": [0, 2], "name": "PATH_SELECT"}
15190 {"bits": [0, 6], "name": "DEALLOC_DIST"}
15195 {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
15196 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"},
15197 {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"}
15202 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
15207 {"bits": [0, 0], "name": "REUSE_OFF"}
15212 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
15213 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
15214 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
15215 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
15216 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
15217 {"bits": [8, 8], "name": "DYNAMIC_HS"},
15218 {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
15219 {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
15220 {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
15221 {"bits": [12, 12], "name": "VS_WAVE_ID_EN"},
15222 {"bits": [13, 13], "name": "PRIMGEN_EN"},
15223 {"bits": [14, 14], "name": "ORDERED_ID_MODE"},
15224 {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"},
15225 {"bits": [19, 20], "name": "GS_FAST_LAUNCH"},
15226 {"bits": [21, 21], "name": "HS_W32_EN"},
15227 {"bits": [22, 22], "name": "GS_W32_EN"},
15228 {"bits": [23, 23], "name": "VS_W32_EN"},
15229 {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"},
15230 {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"}
15235 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
15236 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
15237 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
15238 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
15243 {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
15244 {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
15245 {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
15246 {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
15247 {"bits": [4, 6], "name": "RAST_STREAM"},
15248 {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"},
15249 {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
15250 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
15255 {"bits": [0, 8], "name": "VERTEX_STRIDE"}
15260 {"bits": [0, 9], "name": "STRIDE"}
15265 {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
15266 {"bits": [8, 15], "name": "ACCUM_TRI"},
15267 {"bits": [16, 23], "name": "ACCUM_QUAD"},
15268 {"bits": [24, 28], "name": "DONUT_SPLIT"},
15269 {"bits": [29, 31], "name": "TRAP_SPLIT"}
15274 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
15275 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
15276 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
15277 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
15278 {"bits": [9, 9], "name": "DEPRECATED"},
15279 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
15280 {"bits": [14, 14], "name": "DISABLE_DONUTS"},
15281 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
15282 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
15283 {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"},
15284 {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"},
15285 {"bits": [23, 25], "name": "MTYPE"}
15290 {"bits": [0, 15], "name": "SIZE"}
15295 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
15300 {"bits": [0, 0], "name": "VTX_CNT_EN"}