Lines Matching refs:name
5 {"name": "ARRAY_LINEAR_GENERAL", "value": 0},
6 {"name": "ARRAY_LINEAR_ALIGNED", "value": 1},
7 {"name": "ARRAY_1D_TILED_THIN1", "value": 2},
8 {"name": "ARRAY_1D_TILED_THICK", "value": 3},
9 {"name": "ARRAY_2D_TILED_THIN1", "value": 4},
10 {"name": "ARRAY_PRT_TILED_THIN1", "value": 5},
11 {"name": "ARRAY_PRT_2D_TILED_THIN1", "value": 6},
12 {"name": "ARRAY_2D_TILED_THICK", "value": 7},
13 {"name": "ARRAY_2D_TILED_XTHICK", "value": 8},
14 {"name": "ARRAY_PRT_TILED_THICK", "value": 9},
15 {"name": "ARRAY_PRT_2D_TILED_THICK", "value": 10},
16 {"name": "ARRAY_PRT_3D_TILED_THIN1", "value": 11},
17 {"name": "ARRAY_3D_TILED_THIN1", "value": 12},
18 {"name": "ARRAY_3D_TILED_THICK", "value": 13},
19 {"name": "ARRAY_3D_TILED_XTHICK", "value": 14},
20 {"name": "ARRAY_PRT_3D_TILED_THICK", "value": 15}
25 {"name": "BUF_DATA_FORMAT_INVALID", "value": 0},
26 {"name": "BUF_DATA_FORMAT_8", "value": 1},
27 {"name": "BUF_DATA_FORMAT_16", "value": 2},
28 {"name": "BUF_DATA_FORMAT_8_8", "value": 3},
29 {"name": "BUF_DATA_FORMAT_32", "value": 4},
30 {"name": "BUF_DATA_FORMAT_16_16", "value": 5},
31 {"name": "BUF_DATA_FORMAT_10_11_11", "value": 6},
32 {"name": "BUF_DATA_FORMAT_11_11_10", "value": 7},
33 {"name": "BUF_DATA_FORMAT_10_10_10_2", "value": 8},
34 {"name": "BUF_DATA_FORMAT_2_10_10_10", "value": 9},
35 {"name": "BUF_DATA_FORMAT_8_8_8_8", "value": 10},
36 {"name": "BUF_DATA_FORMAT_32_32", "value": 11},
37 {"name": "BUF_DATA_FORMAT_16_16_16_16", "value": 12},
38 {"name": "BUF_DATA_FORMAT_32_32_32", "value": 13},
39 {"name": "BUF_DATA_FORMAT_32_32_32_32", "value": 14},
40 {"name": "BUF_DATA_FORMAT_RESERVED_15", "value": 15}
45 {"name": "BUF_NUM_FORMAT_UNORM", "value": 0},
46 {"name": "BUF_NUM_FORMAT_SNORM", "value": 1},
47 {"name": "BUF_NUM_FORMAT_USCALED", "value": 2},
48 {"name": "BUF_NUM_FORMAT_SSCALED", "value": 3},
49 {"name": "BUF_NUM_FORMAT_UINT", "value": 4},
50 {"name": "BUF_NUM_FORMAT_SINT", "value": 5},
51 {"name": "BUF_NUM_FORMAT_SNORM_OGL", "value": 6},
52 {"name": "BUF_NUM_FORMAT_FLOAT", "value": 7}
57 {"name": "ADDR_SURF_BANK_HEIGHT_1", "value": 0},
58 {"name": "ADDR_SURF_BANK_HEIGHT_2", "value": 1},
59 {"name": "ADDR_SURF_BANK_HEIGHT_4", "value": 2},
60 {"name": "ADDR_SURF_BANK_HEIGHT_8", "value": 3}
65 {"name": "ADDR_SURF_BANK_WIDTH_1", "value": 0},
66 {"name": "ADDR_SURF_BANK_WIDTH_2", "value": 1},
67 {"name": "ADDR_SURF_BANK_WIDTH_4", "value": 2},
68 {"name": "ADDR_SURF_BANK_WIDTH_8", "value": 3}
73 {"name": "BLEND_ZERO", "value": 0},
74 {"name": "BLEND_ONE", "value": 1},
75 {"name": "BLEND_SRC_COLOR", "value": 2},
76 {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},
77 {"name": "BLEND_SRC_ALPHA", "value": 4},
78 {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},
79 {"name": "BLEND_DST_ALPHA", "value": 6},
80 {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},
81 {"name": "BLEND_DST_COLOR", "value": 8},
82 {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},
83 {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},
84 {"name": "BLEND_BOTH_SRC_ALPHA", "value": 11},
85 {"name": "BLEND_BOTH_INV_SRC_ALPHA", "value": 12},
86 {"name": "BLEND_CONSTANT_COLOR", "value": 13},
87 {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 14},
88 {"name": "BLEND_SRC1_COLOR", "value": 15},
89 {"name": "BLEND_INV_SRC1_COLOR", "value": 16},
90 {"name": "BLEND_SRC1_ALPHA", "value": 17},
91 {"name": "BLEND_INV_SRC1_ALPHA", "value": 18},
92 {"name": "BLEND_CONSTANT_ALPHA", "value": 19},
93 {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 20}
98 {"name": "FORCE_OPT_AUTO", "value": 0},
99 {"name": "FORCE_OPT_DISABLE", "value": 1},
100 {"name": "FORCE_OPT_ENABLE_IF_SRC_A_0", "value": 2},
101 {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},
102 {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},
103 {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},
104 {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},
105 {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}
110 {"name": "CB_DISABLE", "value": 0},
111 {"name": "CB_NORMAL", "value": 1},
112 {"name": "CB_ELIMINATE_FAST_CLEAR", "value": 2},
113 {"name": "CB_RESOLVE", "value": 3},
114 {"name": "CB_DECOMPRESS", "value": 4},
115 {"name": "CB_FMASK_DECOMPRESS", "value": 5}
120 {"name": "OUT", "value": 1},
121 {"name": "IN_0", "value": 2},
122 {"name": "IN_1", "value": 4},
123 {"name": "IN_10", "value": 8},
124 {"name": "IN_2", "value": 16},
125 {"name": "IN_20", "value": 32},
126 {"name": "IN_21", "value": 64},
127 {"name": "IN_210", "value": 128},
128 {"name": "IN_3", "value": 256},
129 {"name": "IN_30", "value": 512},
130 {"name": "IN_31", "value": 1024},
131 {"name": "IN_310", "value": 2048},
132 {"name": "IN_32", "value": 4096},
133 {"name": "IN_320", "value": 8192},
134 {"name": "IN_321", "value": 16384},
135 {"name": "IN_3210", "value": 32768}
140 {"name": "CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT", "value": 0},
141 {"name": "CP_PERFMON_ENABLE_MODE_RESERVED_1", "value": 1},
142 {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},
143 {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE", "value": 3}
148 {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
149 {"name": "CP_PERFMON_STATE_START_COUNTING", "value": 1},
150 {"name": "CP_PERFMON_STATE_STOP_COUNTING", "value": 2},
151 {"name": "CP_PERFMON_STATE_RESERVED_3", "value": 3},
152 {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
153 {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
158 {"name": "COLOR_INVALID", "value": 0},
159 {"name": "COLOR_8", "value": 1},
160 {"name": "COLOR_16", "value": 2},
161 {"name": "COLOR_8_8", "value": 3},
162 {"name": "COLOR_32", "value": 4},
163 {"name": "COLOR_16_16", "value": 5},
164 {"name": "COLOR_10_11_11", "value": 6},
165 {"name": "COLOR_11_11_10", "value": 7},
166 {"name": "COLOR_10_10_10_2", "value": 8},
167 {"name": "COLOR_2_10_10_10", "value": 9},
168 {"name": "COLOR_8_8_8_8", "value": 10},
169 {"name": "COLOR_32_32", "value": 11},
170 {"name": "COLOR_16_16_16_16", "value": 12},
171 {"name": "COLOR_RESERVED_13", "value": 13},
172 {"name": "COLOR_32_32_32_32", "value": 14},
173 {"name": "COLOR_RESERVED_15", "value": 15},
174 {"name": "COLOR_5_6_5", "value": 16},
175 {"name": "COLOR_1_5_5_5", "value": 17},
176 {"name": "COLOR_5_5_5_1", "value": 18},
177 {"name": "COLOR_4_4_4_4", "value": 19},
178 {"name": "COLOR_8_24", "value": 20},
179 {"name": "COLOR_24_8", "value": 21},
180 {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
181 {"name": "COLOR_RESERVED_23", "value": 23}
186 {"name": "COMB_DST_PLUS_SRC", "value": 0},
187 {"name": "COMB_SRC_MINUS_DST", "value": 1},
188 {"name": "COMB_MIN_DST_SRC", "value": 2},
189 {"name": "COMB_MAX_DST_SRC", "value": 3},
190 {"name": "COMB_DST_MINUS_SRC", "value": 4}
195 {"name": "FRAG_NEVER", "value": 0},
196 {"name": "FRAG_LESS", "value": 1},
197 {"name": "FRAG_EQUAL", "value": 2},
198 {"name": "FRAG_LEQUAL", "value": 3},
199 {"name": "FRAG_GREATER", "value": 4},
200 {"name": "FRAG_NOTEQUAL", "value": 5},
201 {"name": "FRAG_GEQUAL", "value": 6},
202 {"name": "FRAG_ALWAYS", "value": 7}
207 {"name": "EXPORT_ANY_Z", "value": 0},
208 {"name": "EXPORT_LESS_THAN_Z", "value": 1},
209 {"name": "EXPORT_GREATER_THAN_Z", "value": 2},
210 {"name": "EXPORT_RESERVED", "value": 3}
215 {"name": "PSLC_AUTO", "value": 0},
216 {"name": "PSLC_ON_HANG_ONLY", "value": 1},
217 {"name": "PSLC_ASAP", "value": 2},
218 {"name": "PSLC_COUNTDOWN", "value": 3}
223 {"name": "INVALID", "value": 1},
224 {"name": "INPUT_DENORMAL", "value": 2},
225 {"name": "DIVIDE_BY_ZERO", "value": 4},
226 {"name": "OVERFLOW", "value": 8},
227 {"name": "UNDERFLOW", "value": 16},
228 {"name": "INEXACT", "value": 32},
229 {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
230 {"name": "ADDRESS_WATCH", "value": 128},
231 {"name": "MEMORY_VIOLATION", "value": 256}
236 {"name": "FP_32_DENORMS", "value": 48},
237 {"name": "FP_64_DENORMS", "value": 192},
238 {"name": "FP_ALL_DENORMS", "value": 240}
243 {"name": "FORCE_OFF", "value": 0},
244 {"name": "FORCE_ENABLE", "value": 1},
245 {"name": "FORCE_DISABLE", "value": 2},
246 {"name": "FORCE_RESERVED", "value": 3}
251 {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0},
252 {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
253 {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
254 {"name": "ADDR_SURF_THICK_MICRO_TILING_GFX6", "value": 3}
259 {"name": "IMG_DATA_FORMAT_INVALID", "value": 0},
260 {"name": "IMG_DATA_FORMAT_8", "value": 1},
261 {"name": "IMG_DATA_FORMAT_16", "value": 2},
262 {"name": "IMG_DATA_FORMAT_8_8", "value": 3},
263 {"name": "IMG_DATA_FORMAT_32", "value": 4},
264 {"name": "IMG_DATA_FORMAT_16_16", "value": 5},
265 {"name": "IMG_DATA_FORMAT_10_11_11", "value": 6},
266 {"name": "IMG_DATA_FORMAT_11_11_10", "value": 7},
267 {"name": "IMG_DATA_FORMAT_10_10_10_2", "value": 8},
268 {"name": "IMG_DATA_FORMAT_2_10_10_10", "value": 9},
269 {"name": "IMG_DATA_FORMAT_8_8_8_8", "value": 10},
270 {"name": "IMG_DATA_FORMAT_32_32", "value": 11},
271 {"name": "IMG_DATA_FORMAT_16_16_16_16", "value": 12},
272 {"name": "IMG_DATA_FORMAT_32_32_32", "value": 13},
273 {"name": "IMG_DATA_FORMAT_32_32_32_32", "value": 14},
274 {"name": "IMG_DATA_FORMAT_RESERVED_15", "value": 15},
275 {"name": "IMG_DATA_FORMAT_5_6_5", "value": 16},
276 {"name": "IMG_DATA_FORMAT_1_5_5_5", "value": 17},
277 {"name": "IMG_DATA_FORMAT_5_5_5_1", "value": 18},
278 {"name": "IMG_DATA_FORMAT_4_4_4_4", "value": 19},
279 {"name": "IMG_DATA_FORMAT_8_24", "value": 20},
280 {"name": "IMG_DATA_FORMAT_24_8", "value": 21},
281 {"name": "IMG_DATA_FORMAT_X24_8_32", "value": 22},
282 {"name": "IMG_DATA_FORMAT_RESERVED_23", "value": 23},
283 {"name": "IMG_DATA_FORMAT_RESERVED_24", "value": 24},
284 {"name": "IMG_DATA_FORMAT_RESERVED_25", "value": 25},
285 {"name": "IMG_DATA_FORMAT_RESERVED_26", "value": 26},
286 {"name": "IMG_DATA_FORMAT_RESERVED_27", "value": 27},
287 {"name": "IMG_DATA_FORMAT_RESERVED_28", "value": 28},
288 {"name": "IMG_DATA_FORMAT_RESERVED_29", "value": 29},
289 {"name": "IMG_DATA_FORMAT_RESERVED_30", "value": 30},
290 {"name": "IMG_DATA_FORMAT_RESERVED_31", "value": 31},
291 {"name": "IMG_DATA_FORMAT_GB_GR", "value": 32},
292 {"name": "IMG_DATA_FORMAT_BG_RG", "value": 33},
293 {"name": "IMG_DATA_FORMAT_5_9_9_9", "value": 34},
294 {"name": "IMG_DATA_FORMAT_BC1", "value": 35},
295 {"name": "IMG_DATA_FORMAT_BC2", "value": 36},
296 {"name": "IMG_DATA_FORMAT_BC3", "value": 37},
297 {"name": "IMG_DATA_FORMAT_BC4", "value": 38},
298 {"name": "IMG_DATA_FORMAT_BC5", "value": 39},
299 {"name": "IMG_DATA_FORMAT_BC6", "value": 40},
300 {"name": "IMG_DATA_FORMAT_BC7", "value": 41},
301 {"name": "IMG_DATA_FORMAT_RESERVED_42", "value": 42},
302 {"name": "IMG_DATA_FORMAT_RESERVED_43", "value": 43},
303 {"name": "IMG_DATA_FORMAT_FMASK8_S2_F1", "value": 44},
304 {"name": "IMG_DATA_FORMAT_FMASK8_S4_F1", "value": 45},
305 {"name": "IMG_DATA_FORMAT_FMASK8_S8_F1", "value": 46},
306 {"name": "IMG_DATA_FORMAT_FMASK8_S2_F2", "value": 47},
307 {"name": "IMG_DATA_FORMAT_FMASK8_S4_F2", "value": 48},
308 {"name": "IMG_DATA_FORMAT_FMASK8_S4_F4", "value": 49},
309 {"name": "IMG_DATA_FORMAT_FMASK16_S16_F1", "value": 50},
310 {"name": "IMG_DATA_FORMAT_FMASK16_S8_F2", "value": 51},
311 {"name": "IMG_DATA_FORMAT_FMASK32_S16_F2", "value": 52},
312 {"name": "IMG_DATA_FORMAT_FMASK32_S8_F4", "value": 53},
313 {"name": "IMG_DATA_FORMAT_FMASK32_S8_F8", "value": 54},
314 {"name": "IMG_DATA_FORMAT_FMASK64_S16_F4", "value": 55},
315 {"name": "IMG_DATA_FORMAT_FMASK64_S16_F8", "value": 56},
316 {"name": "IMG_DATA_FORMAT_4_4", "value": 57},
317 {"name": "IMG_DATA_FORMAT_6_5_5", "value": 58},
318 {"name": "IMG_DATA_FORMAT_1", "value": 59},
319 {"name": "IMG_DATA_FORMAT_1_REVERSED", "value": 60},
320 {"name": "IMG_DATA_FORMAT_32_AS_8", "value": 61},
321 {"name": "IMG_DATA_FORMAT_32_AS_8_8", "value": 62},
322 {"name": "IMG_DATA_FORMAT_32_AS_32_32_32_32", "value": 63}
327 {"name": "IMG_NUM_FORMAT_UNORM", "value": 0},
328 {"name": "IMG_NUM_FORMAT_SNORM", "value": 1},
329 {"name": "IMG_NUM_FORMAT_USCALED", "value": 2},
330 {"name": "IMG_NUM_FORMAT_SSCALED", "value": 3},
331 {"name": "IMG_NUM_FORMAT_UINT", "value": 4},
332 {"name": "IMG_NUM_FORMAT_SINT", "value": 5},
333 {"name": "IMG_NUM_FORMAT_SNORM_OGL", "value": 6},
334 {"name": "IMG_NUM_FORMAT_FLOAT", "value": 7},
335 {"name": "IMG_NUM_FORMAT_RESERVED_8", "value": 8},
336 {"name": "IMG_NUM_FORMAT_SRGB", "value": 9},
337 {"name": "IMG_NUM_FORMAT_UBNORM", "value": 10},
338 {"name": "IMG_NUM_FORMAT_UBNORM_OGL", "value": 11},
339 {"name": "IMG_NUM_FORMAT_UBINT", "value": 12},
340 {"name": "IMG_NUM_FORMAT_UBSCALED", "value": 13},
341 {"name": "IMG_NUM_FORMAT_RESERVED_14", "value": 14},
342 {"name": "IMG_NUM_FORMAT_RESERVED_15", "value": 15}
347 {"name": "ADDR_SURF_MACRO_ASPECT_1", "value": 0},
348 {"name": "ADDR_SURF_MACRO_ASPECT_2", "value": 1},
349 {"name": "ADDR_SURF_MACRO_ASPECT_4", "value": 2},
350 {"name": "ADDR_SURF_MACRO_ASPECT_8", "value": 3}
355 {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0},
356 {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
357 {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
358 {"name": "ADDR_SURF_ROTATED_MICRO_TILING", "value": 3},
359 {"name": "ADDR_SURF_THICK_MICRO_TILING", "value": 4}
364 {"name": "ADDR_SURF_2_BANK", "value": 0},
365 {"name": "ADDR_SURF_4_BANK", "value": 1},
366 {"name": "ADDR_SURF_8_BANK", "value": 2},
367 {"name": "ADDR_SURF_16_BANK", "value": 3}
372 {"name": "X_DRAW_POINTS", "value": 0},
373 {"name": "X_DRAW_LINES", "value": 1},
374 {"name": "X_DRAW_TRIANGLES", "value": 2}
379 {"name": "X_DISABLE_POLY_MODE", "value": 0},
380 {"name": "X_DUAL_MODE", "value": 1}
385 {"name": "X_TRUNCATE", "value": 0},
386 {"name": "X_ROUND", "value": 1},
387 {"name": "X_ROUND_TO_EVEN", "value": 2},
388 {"name": "X_ROUND_TO_ODD", "value": 3}
393 {"name": "ADDR_SURF_P2", "value": 0},
394 {"name": "ADDR_SURF_P2_RESERVED0", "value": 1},
395 {"name": "ADDR_SURF_P2_RESERVED1", "value": 2},
396 {"name": "ADDR_SURF_P2_RESERVED2", "value": 3},
397 {"name": "ADDR_SURF_P4_8x16", "value": 4},
398 {"name": "ADDR_SURF_P4_16x16", "value": 5},
399 {"name": "ADDR_SURF_P4_16x32", "value": 6},
400 {"name": "ADDR_SURF_P4_32x32", "value": 7},
401 {"name": "ADDR_SURF_P8_16x16_8x16", "value": 8},
402 {"name": "ADDR_SURF_P8_16x32_8x16", "value": 9},
403 {"name": "ADDR_SURF_P8_32x32_8x16", "value": 10},
404 {"name": "ADDR_SURF_P8_16x32_16x16", "value": 11},
405 {"name": "ADDR_SURF_P8_32x32_16x16", "value": 12},
406 {"name": "ADDR_SURF_P8_32x32_16x32", "value": 13},
407 {"name": "ADDR_SURF_P8_32x64_32x32", "value": 14},
408 {"name": "ADDR_SURF_P8_RESERVED0", "value": 15},
409 {"name": "ADDR_SURF_P16_32x32_8x16", "value": 16},
410 {"name": "ADDR_SURF_P16_32x32_16x16", "value": 17}
415 {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
416 {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
417 {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
418 {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
423 {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
424 {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
425 {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
426 {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
431 {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
432 {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
433 {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
434 {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
439 {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
440 {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
441 {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
442 {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
447 {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
448 {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
449 {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
450 {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
451 {"name": "X_16_8_FIXED_POINT_1", "value": 4},
452 {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
453 {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
454 {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
459 {"name": "ROP3_CLEAR", "value": 0},
460 {"name": "X_0X05", "value": 5},
461 {"name": "X_0X0A", "value": 10},
462 {"name": "X_0X0F", "value": 15},
463 {"name": "ROP3_NOR", "value": 17},
464 {"name": "ROP3_AND_INVERTED", "value": 34},
465 {"name": "ROP3_COPY_INVERTED", "value": 51},
466 {"name": "ROP3_AND_REVERSE", "value": 68},
467 {"name": "X_0X50", "value": 80},
468 {"name": "ROP3_INVERT", "value": 85},
469 {"name": "X_0X5A", "value": 90},
470 {"name": "X_0X5F", "value": 95},
471 {"name": "ROP3_XOR", "value": 102},
472 {"name": "ROP3_NAND", "value": 119},
473 {"name": "ROP3_AND", "value": 136},
474 {"name": "ROP3_EQUIVALENT", "value": 153},
475 {"name": "X_0XA0", "value": 160},
476 {"name": "X_0XA5", "value": 165},
477 {"name": "ROP3_NO_OP", "value": 170},
478 {"name": "X_0XAF", "value": 175},
479 {"name": "ROP3_OR_INVERTED", "value": 187},
480 {"name": "ROP3_COPY", "value": 204},
481 {"name": "ROP3_OR_REVERSE", "value": 221},
482 {"name": "ROP3_OR", "value": 238},
483 {"name": "X_0XF0", "value": 240},
484 {"name": "X_0XF5", "value": 245},
485 {"name": "X_0XFA", "value": 250},
486 {"name": "ROP3_SET", "value": 255}
491 {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
492 {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
493 {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
494 {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
499 {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
500 {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
505 {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
506 {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
507 {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
508 {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
513 {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
514 {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
519 {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
520 {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
521 {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
522 {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
523 {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
528 {"name": "SPI_SHADER_ZERO", "value": 0},
529 {"name": "SPI_SHADER_32_R", "value": 1},
530 {"name": "SPI_SHADER_32_GR", "value": 2},
531 {"name": "SPI_SHADER_32_AR", "value": 3},
532 {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
533 {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
534 {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
535 {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
536 {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
537 {"name": "SPI_SHADER_32_ABGR", "value": 9}
542 {"name": "SPI_SHADER_NONE", "value": 0},
543 {"name": "SPI_SHADER_1COMP", "value": 1},
544 {"name": "SPI_SHADER_2COMP", "value": 2},
545 {"name": "SPI_SHADER_4COMPRESS", "value": 3},
546 {"name": "SPI_SHADER_4COMP", "value": 4}
551 {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
552 {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
553 {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
554 {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
555 {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
556 {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
561 {"name": "SQ_IMG_FILTER_MODE_BLEND", "value": 0},
562 {"name": "SQ_IMG_FILTER_MODE_MIN", "value": 1},
563 {"name": "SQ_IMG_FILTER_MODE_MAX", "value": 2}
568 {"name": "SQ_RSRC_BUF", "value": 0},
569 {"name": "SQ_RSRC_BUF_RSVD_1", "value": 1},
570 {"name": "SQ_RSRC_BUF_RSVD_2", "value": 2},
571 {"name": "SQ_RSRC_BUF_RSVD_3", "value": 3}
576 {"name": "SQ_RSRC_IMG_RSVD_0", "value": 0},
577 {"name": "SQ_RSRC_IMG_RSVD_1", "value": 1},
578 {"name": "SQ_RSRC_IMG_RSVD_2", "value": 2},
579 {"name": "SQ_RSRC_IMG_RSVD_3", "value": 3},
580 {"name": "SQ_RSRC_IMG_RSVD_4", "value": 4},
581 {"name": "SQ_RSRC_IMG_RSVD_5", "value": 5},
582 {"name": "SQ_RSRC_IMG_RSVD_6", "value": 6},
583 {"name": "SQ_RSRC_IMG_RSVD_7", "value": 7},
584 {"name": "SQ_RSRC_IMG_1D", "value": 8},
585 {"name": "SQ_RSRC_IMG_2D", "value": 9},
586 {"name": "SQ_RSRC_IMG_3D", "value": 10},
587 {"name": "SQ_RSRC_IMG_CUBE", "value": 11},
588 {"name": "SQ_RSRC_IMG_1D_ARRAY", "value": 12},
589 {"name": "SQ_RSRC_IMG_2D_ARRAY", "value": 13},
590 {"name": "SQ_RSRC_IMG_2D_MSAA", "value": 14},
591 {"name": "SQ_RSRC_IMG_2D_MSAA_ARRAY", "value": 15}
596 {"name": "SQ_SEL_0", "value": 0},
597 {"name": "SQ_SEL_1", "value": 1},
598 {"name": "SQ_SEL_RESERVED_0", "value": 2},
599 {"name": "SQ_SEL_RESERVED_1", "value": 3},
600 {"name": "SQ_SEL_X", "value": 4},
601 {"name": "SQ_SEL_Y", "value": 5},
602 {"name": "SQ_SEL_Z", "value": 6},
603 {"name": "SQ_SEL_W", "value": 7}
608 {"name": "SQ_TEX_BORDER_COLOR_TRANS_BLACK", "value": 0},
609 {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_BLACK", "value": 1},
610 {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_WHITE", "value": 2},
611 {"name": "SQ_TEX_BORDER_COLOR_REGISTER", "value": 3}
616 {"name": "SQ_TEX_WRAP", "value": 0},
617 {"name": "SQ_TEX_MIRROR", "value": 1},
618 {"name": "SQ_TEX_CLAMP_LAST_TEXEL", "value": 2},
619 {"name": "SQ_TEX_MIRROR_ONCE_LAST_TEXEL", "value": 3},
620 {"name": "SQ_TEX_CLAMP_HALF_BORDER", "value": 4},
621 {"name": "SQ_TEX_MIRROR_ONCE_HALF_BORDER", "value": 5},
622 {"name": "SQ_TEX_CLAMP_BORDER", "value": 6},
623 {"name": "SQ_TEX_MIRROR_ONCE_BORDER", "value": 7}
628 {"name": "SQ_TEX_DEPTH_COMPARE_NEVER", "value": 0},
629 {"name": "SQ_TEX_DEPTH_COMPARE_LESS", "value": 1},
630 {"name": "SQ_TEX_DEPTH_COMPARE_EQUAL", "value": 2},
631 {"name": "SQ_TEX_DEPTH_COMPARE_LESSEQUAL", "value": 3},
632 {"name": "SQ_TEX_DEPTH_COMPARE_GREATER", "value": 4},
633 {"name": "SQ_TEX_DEPTH_COMPARE_NOTEQUAL", "value": 5},
634 {"name": "SQ_TEX_DEPTH_COMPARE_GREATEREQUAL", "value": 6},
635 {"name": "SQ_TEX_DEPTH_COMPARE_ALWAYS", "value": 7}
640 {"name": "SQ_TEX_MIP_FILTER_NONE", "value": 0},
641 {"name": "SQ_TEX_MIP_FILTER_POINT", "value": 1},
642 {"name": "SQ_TEX_MIP_FILTER_LINEAR", "value": 2}
647 {"name": "SQ_TEX_XY_FILTER_POINT", "value": 0},
648 {"name": "SQ_TEX_XY_FILTER_BILINEAR", "value": 1},
649 {"name": "SQ_TEX_XY_FILTER_ANISO_POINT", "value": 2},
650 {"name": "SQ_TEX_XY_FILTER_ANISO_BILINEAR", "value": 3}
655 {"name": "SQ_TEX_Z_FILTER_NONE", "value": 0},
656 {"name": "SQ_TEX_Z_FILTER_POINT", "value": 1},
657 {"name": "SQ_TEX_Z_FILTER_LINEAR", "value": 2}
662 {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
663 {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
664 {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
665 {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
670 {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
671 {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
672 {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
673 {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
678 {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
679 {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
680 {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
681 {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
686 {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
687 {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
688 {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
689 {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
694 {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
695 {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
696 {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
697 {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
702 {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
703 {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
704 {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
705 {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
710 {"name": "STENCIL_INVALID", "value": 0},
711 {"name": "STENCIL_8", "value": 1}
716 {"name": "STENCIL_KEEP", "value": 0},
717 {"name": "STENCIL_ZERO", "value": 1},
718 {"name": "STENCIL_ONES", "value": 2},
719 {"name": "STENCIL_REPLACE_TEST", "value": 3},
720 {"name": "STENCIL_REPLACE_OP", "value": 4},
721 {"name": "STENCIL_ADD_CLAMP", "value": 5},
722 {"name": "STENCIL_SUB_CLAMP", "value": 6},
723 {"name": "STENCIL_INVERT", "value": 7},
724 {"name": "STENCIL_ADD_WRAP", "value": 8},
725 {"name": "STENCIL_SUB_WRAP", "value": 9},
726 {"name": "STENCIL_AND", "value": 10},
727 {"name": "STENCIL_OR", "value": 11},
728 {"name": "STENCIL_XOR", "value": 12},
729 {"name": "STENCIL_NAND", "value": 13},
730 {"name": "STENCIL_NOR", "value": 14},
731 {"name": "STENCIL_XNOR", "value": 15}
736 {"name": "ENDIAN_NONE", "value": 0},
737 {"name": "ENDIAN_8IN16", "value": 1},
738 {"name": "ENDIAN_8IN32", "value": 2},
739 {"name": "ENDIAN_8IN64", "value": 3}
744 {"name": "NUMBER_UNORM", "value": 0},
745 {"name": "NUMBER_SNORM", "value": 1},
746 {"name": "NUMBER_USCALED", "value": 2},
747 {"name": "NUMBER_SSCALED", "value": 3},
748 {"name": "NUMBER_UINT", "value": 4},
749 {"name": "NUMBER_SINT", "value": 5},
750 {"name": "NUMBER_SRGB", "value": 6},
751 {"name": "NUMBER_FLOAT", "value": 7}
756 {"name": "SWAP_STD", "value": 0},
757 {"name": "SWAP_ALT", "value": 1},
758 {"name": "SWAP_STD_REV", "value": 2},
759 {"name": "SWAP_ALT_REV", "value": 3}
764 {"name": "ADDR_SURF_TILE_SPLIT_64B", "value": 0},
765 {"name": "ADDR_SURF_TILE_SPLIT_128B", "value": 1},
766 {"name": "ADDR_SURF_TILE_SPLIT_256B", "value": 2},
767 {"name": "ADDR_SURF_TILE_SPLIT_512B", "value": 3},
768 {"name": "ADDR_SURF_TILE_SPLIT_1KB", "value": 4},
769 {"name": "ADDR_SURF_TILE_SPLIT_2KB", "value": 5},
770 {"name": "ADDR_SURF_TILE_SPLIT_4KB", "value": 6}
775 {"name": "DI_MAJOR_MODE_0", "value": 0},
776 {"name": "DI_MAJOR_MODE_1", "value": 1}
781 {"name": "DI_PT_NONE", "value": 0},
782 {"name": "DI_PT_POINTLIST", "value": 1},
783 {"name": "DI_PT_LINELIST", "value": 2},
784 {"name": "DI_PT_LINESTRIP", "value": 3},
785 {"name": "DI_PT_TRILIST", "value": 4},
786 {"name": "DI_PT_TRIFAN", "value": 5},
787 {"name": "DI_PT_TRISTRIP", "value": 6},
788 {"name": "DI_PT_UNUSED_0", "value": 7},
789 {"name": "DI_PT_UNUSED_1", "value": 8},
790 {"name": "DI_PT_PATCH", "value": 9},
791 {"name": "DI_PT_LINELIST_ADJ", "value": 10},
792 {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
793 {"name": "DI_PT_TRILIST_ADJ", "value": 12},
794 {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
795 {"name": "DI_PT_UNUSED_3", "value": 14},
796 {"name": "DI_PT_UNUSED_4", "value": 15},
797 {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
798 {"name": "DI_PT_RECTLIST", "value": 17},
799 {"name": "DI_PT_LINELOOP", "value": 18},
800 {"name": "DI_PT_QUADLIST", "value": 19},
801 {"name": "DI_PT_QUADSTRIP", "value": 20},
802 {"name": "DI_PT_POLYGON", "value": 21},
803 {"name": "DI_PT_2D_COPY_RECT_LIST_V0", "value": 22},
804 {"name": "DI_PT_2D_COPY_RECT_LIST_V1", "value": 23},
805 {"name": "DI_PT_2D_COPY_RECT_LIST_V2", "value": 24},
806 {"name": "DI_PT_2D_COPY_RECT_LIST_V3", "value": 25},
807 {"name": "DI_PT_2D_FILL_RECT_LIST", "value": 26},
808 {"name": "DI_PT_2D_LINE_STRIP", "value": 27},
809 {"name": "DI_PT_2D_TRI_STRIP", "value": 28}
814 {"name": "DI_SRC_SEL_DMA", "value": 0},
815 {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
816 {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
817 {"name": "DI_SRC_SEL_RESERVED", "value": 3}
822 {"name": "VGT_DMA_BUF_MEM", "value": 0},
823 {"name": "VGT_DMA_BUF_RING", "value": 1},
824 {"name": "VGT_DMA_BUF_SETUP", "value": 2}
829 {"name": "VGT_DMA_SWAP_NONE", "value": 0},
830 {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
831 {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
832 {"name": "VGT_DMA_SWAP_WORD", "value": 3}
837 {"name": "Reserved_0x00", "value": 0},
838 {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
839 {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
840 {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
841 {"name": "CACHE_FLUSH_TS", "value": 4},
842 {"name": "CONTEXT_DONE", "value": 5},
843 {"name": "CACHE_FLUSH", "value": 6},
844 {"name": "CS_PARTIAL_FLUSH", "value": 7},
845 {"name": "VGT_STREAMOUT_SYNC", "value": 8},
846 {"name": "Reserved_0x09", "value": 9},
847 {"name": "VGT_STREAMOUT_RESET", "value": 10},
848 {"name": "END_OF_PIPE_INCR_DE", "value": 11},
849 {"name": "END_OF_PIPE_IB_END", "value": 12},
850 {"name": "RST_PIX_CNT", "value": 13},
851 {"name": "Reserved_0x0E", "value": 14},
852 {"name": "VS_PARTIAL_FLUSH", "value": 15},
853 {"name": "PS_PARTIAL_FLUSH", "value": 16},
854 {"name": "FLUSH_HS_OUTPUT", "value": 17},
855 {"name": "FLUSH_LS_OUTPUT", "value": 18},
856 {"name": "Reserved_0x13", "value": 19},
857 {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
858 {"name": "ZPASS_DONE", "value": 21},
859 {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
860 {"name": "PERFCOUNTER_START", "value": 23},
861 {"name": "PERFCOUNTER_STOP", "value": 24},
862 {"name": "PIPELINESTAT_START", "value": 25},
863 {"name": "PIPELINESTAT_STOP", "value": 26},
864 {"name": "PERFCOUNTER_SAMPLE", "value": 27},
865 {"name": "FLUSH_ES_OUTPUT", "value": 28},
866 {"name": "FLUSH_GS_OUTPUT", "value": 29},
867 {"name": "SAMPLE_PIPELINESTAT", "value": 30},
868 {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
869 {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
870 {"name": "RESET_VTX_CNT", "value": 33},
871 {"name": "BLOCK_CONTEXT_DONE", "value": 34},
872 {"name": "CS_CONTEXT_DONE", "value": 35},
873 {"name": "VGT_FLUSH", "value": 36},
874 {"name": "Reserved_0x25", "value": 37},
875 {"name": "SQ_NON_EVENT", "value": 38},
876 {"name": "SC_SEND_DB_VPZ", "value": 39},
877 {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
878 {"name": "FLUSH_SX_TS", "value": 41},
879 {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
880 {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
881 {"name": "FLUSH_AND_INV_DB_META", "value": 44},
882 {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
883 {"name": "FLUSH_AND_INV_CB_META", "value": 46},
884 {"name": "CS_DONE", "value": 47},
885 {"name": "PS_DONE", "value": 48},
886 {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
887 {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
888 {"name": "THREAD_TRACE_START", "value": 51},
889 {"name": "THREAD_TRACE_STOP", "value": 52},
890 {"name": "THREAD_TRACE_MARKER", "value": 53},
891 {"name": "THREAD_TRACE_FLUSH", "value": 54},
892 {"name": "THREAD_TRACE_FINISH", "value": 55},
893 {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
894 {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
895 {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
896 {"name": "CONTEXT_SUSPEND", "value": 59}
901 {"name": "GS_CUT_1024", "value": 0},
902 {"name": "GS_CUT_512", "value": 1},
903 {"name": "GS_CUT_256", "value": 2},
904 {"name": "GS_CUT_128", "value": 3}
909 {"name": "GS_OFF", "value": 0},
910 {"name": "GS_SCENARIO_A", "value": 1},
911 {"name": "GS_SCENARIO_B", "value": 2},
912 {"name": "GS_SCENARIO_G", "value": 3},
913 {"name": "GS_SCENARIO_C", "value": 4},
914 {"name": "SPRITE_EN", "value": 5}
919 {"name": "POINTLIST", "value": 0},
920 {"name": "LINESTRIP", "value": 1},
921 {"name": "TRISTRIP", "value": 2}
926 {"name": "X_8K_DWORDS", "value": 0},
927 {"name": "X_4K_DWORDS", "value": 1},
928 {"name": "X_2K_DWORDS", "value": 2},
929 {"name": "X_1K_DWORDS", "value": 3}
934 {"name": "VGT_INDEX_16", "value": 0},
935 {"name": "VGT_INDEX_32", "value": 1}
940 {"name": "VGT_POLICY_LRU", "value": 0},
941 {"name": "VGT_POLICY_STREAM", "value": 1},
942 {"name": "VGT_POLICY_BYPASS", "value": 2},
943 {"name": "VGT_POLICY_RESERVED", "value": 3}
948 {"name": "ES_STAGE_OFF", "value": 0},
949 {"name": "ES_STAGE_DS", "value": 1},
950 {"name": "ES_STAGE_REAL", "value": 2},
951 {"name": "RESERVED_ES", "value": 3}
956 {"name": "GS_STAGE_OFF", "value": 0},
957 {"name": "GS_STAGE_ON", "value": 1}
962 {"name": "HS_STAGE_OFF", "value": 0},
963 {"name": "HS_STAGE_ON", "value": 1}
968 {"name": "LS_STAGE_OFF", "value": 0},
969 {"name": "LS_STAGE_ON", "value": 1},
970 {"name": "CS_STAGE_ON", "value": 2},
971 {"name": "RESERVED_LS", "value": 3}
976 {"name": "VS_STAGE_REAL", "value": 0},
977 {"name": "VS_STAGE_DS", "value": 1},
978 {"name": "VS_STAGE_COPY_SHADER", "value": 2},
979 {"name": "RESERVED_VS", "value": 3}
984 {"name": "PART_INTEGER", "value": 0},
985 {"name": "PART_POW2", "value": 1},
986 {"name": "PART_FRAC_ODD", "value": 2},
987 {"name": "PART_FRAC_EVEN", "value": 3}
992 {"name": "OUTPUT_POINT", "value": 0},
993 {"name": "OUTPUT_LINE", "value": 1},
994 {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
995 {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
1000 {"name": "TESS_ISOLINE", "value": 0},
1001 {"name": "TESS_TRIANGLE", "value": 1},
1002 {"name": "TESS_QUAD", "value": 2}
1007 {"name": "Z_INVALID", "value": 0},
1008 {"name": "Z_16", "value": 1},
1009 {"name": "Z_24", "value": 2},
1010 {"name": "Z_32_FLOAT", "value": 3}
1015 {"name": "FORCE_SUMM_OFF", "value": 0},
1016 {"name": "FORCE_SUMM_MINZ", "value": 1},
1017 {"name": "FORCE_SUMM_MAXZ", "value": 2},
1018 {"name": "FORCE_SUMM_BOTH", "value": 3}
1023 {"name": "LATE_Z", "value": 0},
1024 {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
1025 {"name": "RE_Z", "value": 2},
1026 {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
1034 "name": "SQ_WAVE_MODE",
1040 "name": "SQ_WAVE_STATUS",
1046 "name": "SQ_WAVE_TRAPSTS",
1052 "name": "SQ_WAVE_HW_ID",
1058 "name": "SQ_WAVE_GPR_ALLOC",
1064 "name": "SQ_WAVE_LDS_ALLOC",
1070 "name": "SQ_WAVE_IB_STS",
1076 "name": "SQ_WAVE_PC_LO"
1081 "name": "SQ_WAVE_PC_HI",
1087 "name": "SQ_WAVE_INST_DW0"
1092 "name": "SQ_WAVE_INST_DW1"
1097 "name": "SQ_WAVE_IB_DBG0",
1103 "name": "SQ_WAVE_TBA_LO"
1108 "name": "SQ_WAVE_TBA_HI",
1114 "name": "SQ_WAVE_TMA_LO"
1119 "name": "SQ_WAVE_TMA_HI",
1125 "name": "SQ_WAVE_TTMP0"
1130 "name": "SQ_WAVE_TTMP1"
1135 "name": "SQ_WAVE_TTMP2"
1140 "name": "SQ_WAVE_TTMP3"
1145 "name": "SQ_WAVE_TTMP4"
1150 "name": "SQ_WAVE_TTMP5"
1155 "name": "SQ_WAVE_TTMP6"
1160 "name": "SQ_WAVE_TTMP7"
1165 "name": "SQ_WAVE_TTMP8"
1170 "name": "SQ_WAVE_TTMP9"
1175 "name": "SQ_WAVE_TTMP10"
1180 "name": "SQ_WAVE_TTMP11"
1185 "name": "SQ_WAVE_M0"
1190 "name": "SQ_WAVE_EXEC_LO"
1195 "name": "SQ_WAVE_EXEC_HI"
1200 "name": "GRBM_CNTL",
1206 "name": "GRBM_SKEW_CNTL",
1212 "name": "GRBM_STATUS2",
1218 "name": "GRBM_PWR_CNTL",
1224 "name": "GRBM_STATUS",
1230 "name": "GRBM_STATUS_SE0",
1236 "name": "GRBM_STATUS_SE1",
1242 "name": "GRBM_SOFT_RESET",
1248 "name": "GRBM_DEBUG_CNTL",
1254 "name": "GRBM_DEBUG_DATA"
1259 "name": "GRBM_GFX_INDEX",
1265 "name": "GRBM_GFX_CLKEN_CNTL",
1271 "name": "GRBM_WAIT_IDLE_CLOCKS",
1277 "name": "GRBM_DEBUG",
1283 "name": "GRBM_DEBUG_SNAPSHOT",
1289 "name": "GRBM_READ_ERROR",
1295 "name": "GRBM_INT_CNTL",
1301 "name": "GRBM_PERFCOUNTER0_SELECT",
1307 "name": "GRBM_PERFCOUNTER1_SELECT",
1313 "name": "GRBM_PERFCOUNTER0_LO"
1318 "name": "GRBM_PERFCOUNTER0_HI"
1323 "name": "GRBM_PERFCOUNTER1_LO"
1328 "name": "GRBM_PERFCOUNTER1_HI"
1333 "name": "GRBM_SE0_PERFCOUNTER_SELECT",
1339 "name": "GRBM_SE1_PERFCOUNTER_SELECT",
1345 "name": "GRBM_SE0_PERFCOUNTER_LO"
1350 "name": "GRBM_SE0_PERFCOUNTER_HI"
1355 "name": "GRBM_SE1_PERFCOUNTER_LO"
1360 "name": "GRBM_SE1_PERFCOUNTER_HI"
1365 "name": "DEBUG_INDEX",
1371 "name": "DEBUG_DATA"
1376 "name": "GRBM_NOWHERE"
1381 "name": "GRBM_SCRATCH_REG0"
1386 "name": "GRBM_SCRATCH_REG1"
1391 "name": "GRBM_SCRATCH_REG2"
1396 "name": "GRBM_SCRATCH_REG3"
1401 "name": "GRBM_SCRATCH_REG4"
1406 "name": "GRBM_SCRATCH_REG5"
1411 "name": "GRBM_SCRATCH_REG6"
1416 "name": "GRBM_SCRATCH_REG7"
1421 "name": "SQ_INTERRUPT_WORD_AUTO",
1427 "name": "CP_EOP_DONE_ADDR_LO",
1433 "name": "CP_EOP_DONE_ADDR_HI",
1439 "name": "CP_EOP_DONE_DATA_LO"
1444 "name": "CP_EOP_DONE_DATA_HI"
1449 "name": "CP_EOP_LAST_FENCE_LO"
1454 "name": "CP_EOP_LAST_FENCE_HI"
1459 "name": "CP_STREAM_OUT_ADDR_LO",
1465 "name": "CP_STREAM_OUT_ADDR_HI"
1470 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
1475 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
1480 "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
1485 "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
1490 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
1495 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
1500 "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
1505 "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
1510 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
1515 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
1520 "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
1525 "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
1530 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
1535 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
1540 "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
1545 "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
1550 "name": "CP_PIPE_STATS_ADDR_LO",
1556 "name": "CP_PIPE_STATS_ADDR_HI"
1561 "name": "CP_VGT_IAVERT_COUNT_LO"
1566 "name": "CP_VGT_IAVERT_COUNT_HI"
1571 "name": "CP_VGT_IAPRIM_COUNT_LO"
1576 "name": "CP_VGT_IAPRIM_COUNT_HI"
1581 "name": "CP_VGT_GSPRIM_COUNT_LO"
1586 "name": "CP_VGT_GSPRIM_COUNT_HI"
1591 "name": "CP_VGT_VSINVOC_COUNT_LO"
1596 "name": "CP_VGT_VSINVOC_COUNT_HI"
1601 "name": "CP_VGT_GSINVOC_COUNT_LO"
1606 "name": "CP_VGT_GSINVOC_COUNT_HI"
1611 "name": "CP_VGT_HSINVOC_COUNT_LO"
1616 "name": "CP_VGT_HSINVOC_COUNT_HI"
1621 "name": "CP_VGT_DSINVOC_COUNT_LO"
1626 "name": "CP_VGT_DSINVOC_COUNT_HI"
1631 "name": "CP_PA_CINVOC_COUNT_LO"
1636 "name": "CP_PA_CINVOC_COUNT_HI"
1641 "name": "CP_PA_CPRIM_COUNT_LO"
1646 "name": "CP_PA_CPRIM_COUNT_HI"
1651 "name": "CP_SC_PSINVOC_COUNT0_LO"
1656 "name": "CP_SC_PSINVOC_COUNT0_HI"
1661 "name": "CP_SC_PSINVOC_COUNT1_LO"
1666 "name": "CP_SC_PSINVOC_COUNT1_HI"
1671 "name": "CP_VGT_CSINVOC_COUNT_LO"
1676 "name": "CP_VGT_CSINVOC_COUNT_HI"
1681 "name": "CP_STRMOUT_CNTL",
1687 "name": "SCRATCH_REG0"
1692 "name": "SCRATCH_REG1"
1697 "name": "SCRATCH_REG2"
1702 "name": "SCRATCH_REG3"
1707 "name": "SCRATCH_REG4"
1712 "name": "SCRATCH_REG5"
1717 "name": "SCRATCH_REG6"
1722 "name": "SCRATCH_REG7"
1727 "name": "SCRATCH_UMSK",
1733 "name": "SCRATCH_ADDR"
1738 "name": "CP_APPEND_ADDR_LO",
1744 "name": "CP_APPEND_ADDR_HI",
1750 "name": "CP_APPEND_DATA"
1755 "name": "CP_APPEND_LAST_CS_FENCE"
1760 "name": "CP_APPEND_LAST_PS_FENCE"
1765 "name": "CP_ATOMIC_PREOP_LO"
1770 "name": "CP_ATOMIC_PREOP_HI"
1775 "name": "CP_GDS_ATOMIC0_PREOP_LO"
1780 "name": "CP_GDS_ATOMIC0_PREOP_HI"
1785 "name": "CP_GDS_ATOMIC1_PREOP_LO"
1790 "name": "CP_GDS_ATOMIC1_PREOP_HI"
1795 "name": "CP_ME_MC_WADDR_LO",
1801 "name": "CP_ME_MC_WADDR_HI",
1807 "name": "CP_ME_MC_WDATA_LO"
1812 "name": "CP_ME_MC_WDATA_HI"
1817 "name": "CP_ME_MC_RADDR_LO",
1823 "name": "CP_ME_MC_RADDR_HI",
1829 "name": "CP_SEM_WAIT_TIMER"
1834 "name": "CP_SIG_SEM_ADDR_LO",
1840 "name": "CP_SIG_SEM_ADDR_HI",
1846 "name": "CP_WAIT_REG_MEM_TIMEOUT"
1851 "name": "CP_WAIT_SEM_ADDR_LO",
1857 "name": "CP_WAIT_SEM_ADDR_HI",
1863 "name": "CP_COHER_START_DELAY",
1869 "name": "CP_COHER_CNTL",
1875 "name": "CP_COHER_SIZE"
1880 "name": "CP_COHER_BASE"
1885 "name": "CP_COHER_STATUS",
1891 "name": "CP_DMA_ME_SRC_ADDR"
1896 "name": "CP_DMA_ME_SRC_ADDR_HI",
1902 "name": "CP_DMA_ME_DST_ADDR"
1907 "name": "CP_DMA_ME_DST_ADDR_HI",
1913 "name": "CP_DMA_ME_COMMAND",
1919 "name": "CP_DMA_PFP_SRC_ADDR"
1924 "name": "CP_DMA_PFP_SRC_ADDR_HI",
1930 "name": "CP_DMA_PFP_DST_ADDR"
1935 "name": "CP_DMA_PFP_DST_ADDR_HI",
1941 "name": "CP_DMA_PFP_COMMAND",
1947 "name": "CP_DMA_CNTL",
1953 "name": "CP_DMA_READ_TAGS",
1959 "name": "CP_PFP_IB_CONTROL",
1965 "name": "CP_PFP_LOAD_CONTROL",
1971 "name": "CP_SCRATCH_INDEX",
1977 "name": "CP_SCRATCH_DATA"
1982 "name": "CP_RB_OFFSET",
1988 "name": "CP_IB1_OFFSET",
1994 "name": "CP_IB2_OFFSET",
2000 "name": "CP_IB1_PREAMBLE_BEGIN",
2006 "name": "CP_IB1_PREAMBLE_END",
2012 "name": "CP_IB2_PREAMBLE_BEGIN",
2018 "name": "CP_IB2_PREAMBLE_END",
2024 "name": "CP_STALLED_STAT3",
2030 "name": "CP_STALLED_STAT1",
2036 "name": "CP_STALLED_STAT2",
2042 "name": "CP_BUSY_STAT",
2048 "name": "CP_STAT",
2054 "name": "CP_ME_HEADER_DUMP"
2059 "name": "CP_PFP_HEADER_DUMP"
2064 "name": "CP_GRBM_FREE_COUNT",
2070 "name": "CP_CE_HEADER_DUMP"
2075 "name": "CP_MC_PACK_DELAY_CNT",
2081 "name": "CP_CSF_STAT",
2087 "name": "CP_CSF_CNTL",
2093 "name": "CP_ME_CNTL",
2099 "name": "CP_CNTX_STAT",
2105 "name": "CP_ME_PREEMPTION",
2111 "name": "CP_RB2_RPTR",
2117 "name": "CP_RB1_RPTR",
2123 "name": "CP_RB0_RPTR",
2129 "name": "CP_RB_WPTR_DELAY",
2135 "name": "CP_RB_WPTR_POLL_CNTL",
2141 "name": "CP_CE_INIT_BASE_LO",
2147 "name": "CP_CE_INIT_BASE_HI",
2153 "name": "CP_CE_INIT_BUFSZ",
2159 "name": "CP_CE_IB1_BASE_LO",
2165 "name": "CP_CE_IB1_BASE_HI",
2171 "name": "CP_CE_IB1_BUFSZ",
2177 "name": "CP_CE_IB2_BASE_LO",
2183 "name": "CP_CE_IB2_BASE_HI",
2189 "name": "CP_CE_IB2_BUFSZ",
2195 "name": "CP_IB1_BASE_LO",
2201 "name": "CP_IB1_BASE_HI",
2207 "name": "CP_IB1_BUFSZ",
2213 "name": "CP_IB2_BASE_LO",
2219 "name": "CP_IB2_BASE_HI",
2225 "name": "CP_IB2_BUFSZ",
2231 "name": "CP_ST_BASE_LO",
2237 "name": "CP_ST_BASE_HI",
2243 "name": "CP_ST_BUFSZ",
2249 "name": "CP_ROQ1_THRESHOLDS",
2255 "name": "CP_ROQ2_THRESHOLDS",
2261 "name": "CP_STQ_THRESHOLDS",
2267 "name": "CP_QUEUE_THRESHOLDS",
2273 "name": "CP_MEQ_THRESHOLDS",
2279 "name": "CP_ROQ_AVAIL",
2285 "name": "CP_STQ_AVAIL",
2291 "name": "CP_ROQ2_AVAIL",
2297 "name": "CP_MEQ_AVAIL",
2303 "name": "CP_CMD_INDEX",
2309 "name": "CP_CMD_DATA"
2314 "name": "CP_ROQ_RB_STAT",
2320 "name": "CP_ROQ_IB1_STAT",
2326 "name": "CP_ROQ_IB2_STAT",
2332 "name": "CP_STQ_STAT",
2338 "name": "CP_MEQ_STAT",
2344 "name": "CP_CEQ1_AVAIL",
2350 "name": "CP_CEQ2_AVAIL",
2356 "name": "CP_CE_ROQ_RB_STAT",
2362 "name": "CP_CE_ROQ_IB1_STAT",
2368 "name": "CP_CE_ROQ_IB2_STAT",
2374 "name": "CP_INT_STAT_DEBUG",
2380 "name": "CP_PERFMON_CNTL",
2386 "name": "IA_PERFCOUNTER0_SELECT",
2392 "name": "IA_PERFCOUNTER1_SELECT",
2398 "name": "IA_PERFCOUNTER2_SELECT",
2404 "name": "IA_PERFCOUNTER3_SELECT",
2410 "name": "IA_PERFCOUNTER0_LO"
2415 "name": "IA_PERFCOUNTER0_HI"
2420 "name": "IA_PERFCOUNTER1_LO"
2425 "name": "IA_PERFCOUNTER1_HI"
2430 "name": "IA_PERFCOUNTER2_LO"
2435 "name": "IA_PERFCOUNTER2_HI"
2440 "name": "IA_PERFCOUNTER3_LO"
2445 "name": "IA_PERFCOUNTER3_HI"
2450 "name": "VGT_VTX_VECT_EJECT_REG",
2456 "name": "VGT_DMA_DATA_FIFO_DEPTH",
2462 "name": "VGT_DMA_REQ_FIFO_DEPTH",
2468 "name": "VGT_DRAW_INIT_FIFO_DEPTH",
2474 "name": "VGT_LAST_COPY_STATE",
2480 "name": "VGT_CACHE_INVALIDATION",
2486 "name": "VGT_ESGS_RING_SIZE"
2491 "name": "VGT_GSVS_RING_SIZE"
2496 "name": "VGT_FIFO_DEPTHS",
2502 "name": "VGT_GS_VERTEX_REUSE",
2508 "name": "VGT_MC_LAT_CNTL",
2514 "name": "IA_CNTL_STATUS",
2520 "name": "VGT_DEBUG_CNTL",
2526 "name": "VGT_DEBUG_DATA"
2531 "name": "IA_DEBUG_CNTL",
2537 "name": "IA_DEBUG_DATA"
2542 "name": "VGT_CNTL_STATUS",
2548 "name": "VGT_PERFCOUNTER_SEID_MASK",
2554 "name": "VGT_PERFCOUNTER0_SELECT",
2560 "name": "VGT_PERFCOUNTER1_SELECT",
2566 "name": "VGT_PERFCOUNTER2_SELECT",
2572 "name": "VGT_PERFCOUNTER3_SELECT",
2578 "name": "VGT_PERFCOUNTER0_LO"
2583 "name": "VGT_PERFCOUNTER0_HI"
2588 "name": "VGT_PERFCOUNTER1_LO"
2593 "name": "VGT_PERFCOUNTER1_HI"
2598 "name": "VGT_PERFCOUNTER2_LO"
2603 "name": "VGT_PERFCOUNTER2_HI"
2608 "name": "VGT_PERFCOUNTER3_LO"
2613 "name": "VGT_PERFCOUNTER3_HI"
2618 "name": "VGT_PRIMITIVE_TYPE",
2624 "name": "VGT_INDEX_TYPE",
2630 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0"
2635 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1"
2640 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2"
2645 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3"
2650 "name": "VGT_NUM_INDICES"
2655 "name": "VGT_NUM_INSTANCES"
2660 "name": "CGTT_VGT_CLK_CTRL",
2666 "name": "IA_VMID_OVERRIDE",
2672 "name": "CGTT_IA_CLK_CTRL",
2678 "name": "VGT_TF_RING_SIZE",
2684 "name": "VGT_SYS_CONFIG",
2690 "name": "VGT_HS_OFFCHIP_PARAM",
2696 "name": "VGT_TF_MEMORY_BASE"
2701 "name": "CC_GC_SHADER_ARRAY_CONFIG",
2707 "name": "GC_USER_SHADER_ARRAY_CONFIG",
2713 "name": "PA_SU_DEBUG_CNTL",
2719 "name": "PA_SU_DEBUG_DATA"
2724 "name": "PA_CL_CNTL_STATUS",
2730 "name": "PA_CL_ENHANCE",
2736 "name": "CGTT_PA_CLK_CTRL",
2742 "name": "PA_SU_PERFCOUNTER0_SELECT",
2748 "name": "PA_SU_PERFCOUNTER1_SELECT",
2754 "name": "PA_SU_PERFCOUNTER2_SELECT",
2760 "name": "PA_SU_PERFCOUNTER3_SELECT",
2766 "name": "PA_SU_PERFCOUNTER0_LO"
2771 "name": "PA_SU_PERFCOUNTER0_HI",
2777 "name": "PA_SU_PERFCOUNTER1_LO"
2782 "name": "PA_SU_PERFCOUNTER1_HI",
2788 "name": "PA_SU_PERFCOUNTER2_LO"
2793 "name": "PA_SU_PERFCOUNTER2_HI",
2799 "name": "PA_SU_PERFCOUNTER3_LO"
2804 "name": "PA_SU_PERFCOUNTER3_HI",
2810 "name": "PA_SU_CNTL_STATUS",
2816 "name": "PA_SC_FIFO_DEPTH_CNTL",
2822 "name": "PA_SU_LINE_STIPPLE_VALUE",
2828 "name": "PA_SC_PERFCOUNTER0_SELECT",
2834 "name": "PA_SC_PERFCOUNTER1_SELECT",
2840 "name": "PA_SC_PERFCOUNTER2_SELECT",
2846 "name": "PA_SC_PERFCOUNTER3_SELECT",
2852 "name": "PA_SC_PERFCOUNTER4_SELECT",
2858 "name": "PA_SC_PERFCOUNTER5_SELECT",
2864 "name": "PA_SC_PERFCOUNTER6_SELECT",
2870 "name": "PA_SC_PERFCOUNTER7_SELECT",
2876 "name": "PA_SC_PERFCOUNTER0_LO"
2881 "name": "PA_SC_PERFCOUNTER0_HI"
2886 "name": "PA_SC_PERFCOUNTER1_LO"
2891 "name": "PA_SC_PERFCOUNTER1_HI"
2896 "name": "PA_SC_PERFCOUNTER2_LO"
2901 "name": "PA_SC_PERFCOUNTER2_HI"
2906 "name": "PA_SC_PERFCOUNTER3_LO"
2911 "name": "PA_SC_PERFCOUNTER3_HI"
2916 "name": "PA_SC_PERFCOUNTER4_LO"
2921 "name": "PA_SC_PERFCOUNTER4_HI"
2926 "name": "PA_SC_PERFCOUNTER5_LO"
2931 "name": "PA_SC_PERFCOUNTER5_HI"
2936 "name": "PA_SC_PERFCOUNTER6_LO"
2941 "name": "PA_SC_PERFCOUNTER6_HI"
2946 "name": "PA_SC_PERFCOUNTER7_LO"
2951 "name": "PA_SC_PERFCOUNTER7_HI"
2956 "name": "PA_SC_LINE_STIPPLE_STATE",
2962 "name": "PA_SC_FORCE_EOV_MAX_CNTS",
2968 "name": "CGTT_SC_CLK_CTRL",
2974 "name": "PA_SC_FIFO_SIZE",
2980 "name": "PA_SC_IF_FIFO_SIZE",
2986 "name": "PA_SC_DEBUG_CNTL",
2992 "name": "PA_SC_DEBUG_DATA"
2997 "name": "PA_SC_ENHANCE",
3003 "name": "SQ_CONFIG",
3009 "name": "SQC_CONFIG",
3015 "name": "SQC_CACHES",
3021 "name": "SQ_RANDOM_WAVE_PRI",
3027 "name": "SQ_REG_CREDITS",
3033 "name": "SQ_FIFO_SIZES",
3039 "name": "SQ_PERFCOUNTER_CTRL",
3045 "name": "CC_SQC_BANK_DISABLE",
3051 "name": "USER_SQC_BANK_DISABLE",
3057 "name": "SQ_DEBUG_STS_GLOBAL",
3063 "name": "SQ_PERFCOUNTER0_LO"
3068 "name": "SQ_PERFCOUNTER0_HI"
3073 "name": "SQ_PERFCOUNTER1_LO"
3078 "name": "SQ_PERFCOUNTER1_HI"
3083 "name": "SQ_PERFCOUNTER2_LO"
3088 "name": "SQ_PERFCOUNTER2_HI"
3093 "name": "SQ_PERFCOUNTER3_LO"
3098 "name": "SQ_PERFCOUNTER3_HI"
3103 "name": "SQ_PERFCOUNTER4_LO"
3108 "name": "SQ_PERFCOUNTER4_HI"
3113 "name": "SQ_PERFCOUNTER5_LO"
3118 "name": "SQ_PERFCOUNTER5_HI"
3123 "name": "SQ_PERFCOUNTER6_LO"
3128 "name": "SQ_PERFCOUNTER6_HI"
3133 "name": "SQ_PERFCOUNTER7_LO"
3138 "name": "SQ_PERFCOUNTER7_HI"
3143 "name": "SQ_PERFCOUNTER8_LO"
3148 "name": "SQ_PERFCOUNTER8_HI"
3153 "name": "SQ_PERFCOUNTER9_LO"
3158 "name": "SQ_PERFCOUNTER9_HI"
3163 "name": "SQ_PERFCOUNTER10_LO"
3168 "name": "SQ_PERFCOUNTER10_HI"
3173 "name": "SQ_PERFCOUNTER11_LO"
3178 "name": "SQ_PERFCOUNTER11_HI"
3183 "name": "SQ_PERFCOUNTER12_LO"
3188 "name": "SQ_PERFCOUNTER12_HI"
3193 "name": "SQ_PERFCOUNTER13_LO"
3198 "name": "SQ_PERFCOUNTER13_HI"
3203 "name": "SQ_PERFCOUNTER14_LO"
3208 "name": "SQ_PERFCOUNTER14_HI"
3213 "name": "SQ_PERFCOUNTER15_LO"
3218 "name": "SQ_PERFCOUNTER15_HI"
3223 "name": "SQ_PERFCOUNTER0_SELECT",
3229 "name": "SQ_PERFCOUNTER1_SELECT",
3235 "name": "SQ_PERFCOUNTER2_SELECT",
3241 "name": "SQ_PERFCOUNTER3_SELECT",
3247 "name": "SQ_PERFCOUNTER4_SELECT",
3253 "name": "SQ_PERFCOUNTER5_SELECT",
3259 "name": "SQ_PERFCOUNTER6_SELECT",
3265 "name": "SQ_PERFCOUNTER7_SELECT",
3271 "name": "SQ_PERFCOUNTER8_SELECT",
3277 "name": "SQ_PERFCOUNTER9_SELECT",
3283 "name": "SQ_PERFCOUNTER10_SELECT",
3289 "name": "SQ_PERFCOUNTER11_SELECT",
3295 "name": "SQ_PERFCOUNTER12_SELECT",
3301 "name": "SQ_PERFCOUNTER13_SELECT",
3307 "name": "SQ_PERFCOUNTER14_SELECT",
3313 "name": "SQ_PERFCOUNTER15_SELECT",
3319 "name": "SQ_ALU_CLK_CTRL",
3325 "name": "SQ_TEX_CLK_CTRL",
3331 "name": "CGTT_SQ_CLK_CTRL",
3337 "name": "CGTT_SQG_CLK_CTRL",
3343 "name": "SQ_IND_INDEX",
3349 "name": "SQ_IND_DATA"
3354 "name": "SQ_TIME_HI"
3359 "name": "SQ_TIME_LO"
3364 "name": "SQ_THREAD_TRACE_BASE"
3369 "name": "SQ_THREAD_TRACE_SIZE",
3375 "name": "SQ_THREAD_TRACE_MASK",
3381 "name": "SQ_THREAD_TRACE_TOKEN_MASK",
3387 "name": "SQ_THREAD_TRACE_PERF_MASK",
3393 "name": "SQ_THREAD_TRACE_USERDATA_0"
3398 "name": "SQ_THREAD_TRACE_USERDATA_1"
3403 "name": "SQ_THREAD_TRACE_USERDATA_2"
3408 "name": "SQ_THREAD_TRACE_USERDATA_3"
3413 "name": "SQ_THREAD_TRACE_WPTR",
3419 "name": "SQ_THREAD_TRACE_STATUS",
3425 "name": "SQ_THREAD_TRACE_MODE",
3431 "name": "SQ_THREAD_TRACE_CTRL",
3437 "name": "SQ_THREAD_TRACE_CNTR"
3442 "name": "SQ_THREAD_TRACE_HIWATER",
3448 "name": "SQ_POWER_THROTTLE",
3454 "name": "SQ_POWER_THROTTLE2",
3460 "name": "SQ_LB_CTR_CTRL",
3466 "name": "SQ_LB_DATA_ALU_CYCLES"
3471 "name": "SQ_LB_DATA_TEX_CYCLES"
3476 "name": "SQ_LB_DATA_ALU_STALLS"
3481 "name": "SQ_LB_DATA_TEX_STALLS"
3486 "name": "SQC_SECDED_CNT",
3492 "name": "SQ_SEC_CNT",
3498 "name": "SQ_DED_CNT",
3504 "name": "SQ_DED_INFO",
3510 "name": "SQ_BUF_RSRC_WORD0"
3515 "name": "SQ_BUF_RSRC_WORD1",
3521 "name": "SQ_BUF_RSRC_WORD2"
3526 "name": "SQ_BUF_RSRC_WORD3",
3532 "name": "SQ_IMG_RSRC_WORD0"
3537 "name": "SQ_IMG_RSRC_WORD1",
3543 "name": "SQ_IMG_RSRC_WORD2",
3549 "name": "SQ_IMG_RSRC_WORD3",
3555 "name": "SQ_IMG_RSRC_WORD4",
3561 "name": "SQ_IMG_RSRC_WORD5",
3567 "name": "SQ_IMG_RSRC_WORD6",
3573 "name": "SQ_IMG_RSRC_WORD7"
3578 "name": "SQ_IMG_SAMP_WORD0",
3584 "name": "SQ_IMG_SAMP_WORD1",
3590 "name": "SQ_IMG_SAMP_WORD2",
3596 "name": "SQ_IMG_SAMP_WORD3",
3602 "name": "SPI_CONFIG_CNTL",
3608 "name": "TA_CS_BC_BASE_ADDR"
3613 "name": "GB_ADDR_CONFIG",
3619 "name": "GB_TILE_MODE0",
3625 "name": "GB_TILE_MODE1",
3631 "name": "GB_TILE_MODE2",
3637 "name": "GB_TILE_MODE3",
3643 "name": "GB_TILE_MODE4",
3649 "name": "GB_TILE_MODE5",
3655 "name": "GB_TILE_MODE6",
3661 "name": "GB_TILE_MODE7",
3667 "name": "GB_TILE_MODE8",
3673 "name": "GB_TILE_MODE9",
3679 "name": "GB_TILE_MODE10",
3685 "name": "GB_TILE_MODE11",
3691 "name": "GB_TILE_MODE12",
3697 "name": "GB_TILE_MODE13",
3703 "name": "GB_TILE_MODE14",
3709 "name": "GB_TILE_MODE15",
3715 "name": "GB_TILE_MODE16",
3721 "name": "GB_TILE_MODE17",
3727 "name": "GB_TILE_MODE18",
3733 "name": "GB_TILE_MODE19",
3739 "name": "GB_TILE_MODE20",
3745 "name": "GB_TILE_MODE21",
3751 "name": "GB_TILE_MODE22",
3757 "name": "GB_TILE_MODE23",
3763 "name": "GB_TILE_MODE24",
3769 "name": "GB_TILE_MODE25",
3775 "name": "GB_TILE_MODE26",
3781 "name": "GB_TILE_MODE27",
3787 "name": "GB_TILE_MODE28",
3793 "name": "GB_TILE_MODE29",
3799 "name": "GB_TILE_MODE30",
3805 "name": "GB_TILE_MODE31",
3811 "name": "SPI_SHADER_TBA_LO_PS"
3816 "name": "SPI_SHADER_TBA_HI_PS",
3822 "name": "SPI_SHADER_TMA_LO_PS"
3827 "name": "SPI_SHADER_TMA_HI_PS",
3833 "name": "SPI_SHADER_PGM_LO_PS"
3838 "name": "SPI_SHADER_PGM_HI_PS",
3844 "name": "SPI_SHADER_PGM_RSRC1_PS",
3850 "name": "SPI_SHADER_PGM_RSRC2_PS",
3856 "name": "SPI_SHADER_USER_DATA_PS_0"
3861 "name": "SPI_SHADER_USER_DATA_PS_1"
3866 "name": "SPI_SHADER_USER_DATA_PS_2"
3871 "name": "SPI_SHADER_USER_DATA_PS_3"
3876 "name": "SPI_SHADER_USER_DATA_PS_4"
3881 "name": "SPI_SHADER_USER_DATA_PS_5"
3886 "name": "SPI_SHADER_USER_DATA_PS_6"
3891 "name": "SPI_SHADER_USER_DATA_PS_7"
3896 "name": "SPI_SHADER_USER_DATA_PS_8"
3901 "name": "SPI_SHADER_USER_DATA_PS_9"
3906 "name": "SPI_SHADER_USER_DATA_PS_10"
3911 "name": "SPI_SHADER_USER_DATA_PS_11"
3916 "name": "SPI_SHADER_USER_DATA_PS_12"
3921 "name": "SPI_SHADER_USER_DATA_PS_13"
3926 "name": "SPI_SHADER_USER_DATA_PS_14"
3931 "name": "SPI_SHADER_USER_DATA_PS_15"
3936 "name": "SPI_SHADER_TBA_LO_VS"
3941 "name": "SPI_SHADER_TBA_HI_VS",
3947 "name": "SPI_SHADER_TMA_LO_VS"
3952 "name": "SPI_SHADER_TMA_HI_VS",
3958 "name": "SPI_SHADER_PGM_LO_VS"
3963 "name": "SPI_SHADER_PGM_HI_VS",
3969 "name": "SPI_SHADER_PGM_RSRC1_VS",
3975 "name": "SPI_SHADER_PGM_RSRC2_VS",
3981 "name": "SPI_SHADER_USER_DATA_VS_0"
3986 "name": "SPI_SHADER_USER_DATA_VS_1"
3991 "name": "SPI_SHADER_USER_DATA_VS_2"
3996 "name": "SPI_SHADER_USER_DATA_VS_3"
4001 "name": "SPI_SHADER_USER_DATA_VS_4"
4006 "name": "SPI_SHADER_USER_DATA_VS_5"
4011 "name": "SPI_SHADER_USER_DATA_VS_6"
4016 "name": "SPI_SHADER_USER_DATA_VS_7"
4021 "name": "SPI_SHADER_USER_DATA_VS_8"
4026 "name": "SPI_SHADER_USER_DATA_VS_9"
4031 "name": "SPI_SHADER_USER_DATA_VS_10"
4036 "name": "SPI_SHADER_USER_DATA_VS_11"
4041 "name": "SPI_SHADER_USER_DATA_VS_12"
4046 "name": "SPI_SHADER_USER_DATA_VS_13"
4051 "name": "SPI_SHADER_USER_DATA_VS_14"
4056 "name": "SPI_SHADER_USER_DATA_VS_15"
4061 "name": "SPI_SHADER_TBA_LO_GS"
4066 "name": "SPI_SHADER_TBA_HI_GS",
4072 "name": "SPI_SHADER_TMA_LO_GS"
4077 "name": "SPI_SHADER_TMA_HI_GS",
4083 "name": "SPI_SHADER_PGM_LO_GS"
4088 "name": "SPI_SHADER_PGM_HI_GS",
4094 "name": "SPI_SHADER_PGM_RSRC1_GS",
4100 "name": "SPI_SHADER_PGM_RSRC2_GS",
4106 "name": "SPI_SHADER_USER_DATA_GS_0"
4111 "name": "SPI_SHADER_USER_DATA_GS_1"
4116 "name": "SPI_SHADER_USER_DATA_GS_2"
4121 "name": "SPI_SHADER_USER_DATA_GS_3"
4126 "name": "SPI_SHADER_USER_DATA_GS_4"
4131 "name": "SPI_SHADER_USER_DATA_GS_5"
4136 "name": "SPI_SHADER_USER_DATA_GS_6"
4141 "name": "SPI_SHADER_USER_DATA_GS_7"
4146 "name": "SPI_SHADER_USER_DATA_GS_8"
4151 "name": "SPI_SHADER_USER_DATA_GS_9"
4156 "name": "SPI_SHADER_USER_DATA_GS_10"
4161 "name": "SPI_SHADER_USER_DATA_GS_11"
4166 "name": "SPI_SHADER_USER_DATA_GS_12"
4171 "name": "SPI_SHADER_USER_DATA_GS_13"
4176 "name": "SPI_SHADER_USER_DATA_GS_14"
4181 "name": "SPI_SHADER_USER_DATA_GS_15"
4186 "name": "SPI_SHADER_TBA_LO_ES"
4191 "name": "SPI_SHADER_TBA_HI_ES",
4197 "name": "SPI_SHADER_TMA_LO_ES"
4202 "name": "SPI_SHADER_TMA_HI_ES",
4208 "name": "SPI_SHADER_PGM_LO_ES"
4213 "name": "SPI_SHADER_PGM_HI_ES",
4219 "name": "SPI_SHADER_PGM_RSRC1_ES",
4225 "name": "SPI_SHADER_PGM_RSRC2_ES",
4231 "name": "SPI_SHADER_USER_DATA_ES_0"
4236 "name": "SPI_SHADER_USER_DATA_ES_1"
4241 "name": "SPI_SHADER_USER_DATA_ES_2"
4246 "name": "SPI_SHADER_USER_DATA_ES_3"
4251 "name": "SPI_SHADER_USER_DATA_ES_4"
4256 "name": "SPI_SHADER_USER_DATA_ES_5"
4261 "name": "SPI_SHADER_USER_DATA_ES_6"
4266 "name": "SPI_SHADER_USER_DATA_ES_7"
4271 "name": "SPI_SHADER_USER_DATA_ES_8"
4276 "name": "SPI_SHADER_USER_DATA_ES_9"
4281 "name": "SPI_SHADER_USER_DATA_ES_10"
4286 "name": "SPI_SHADER_USER_DATA_ES_11"
4291 "name": "SPI_SHADER_USER_DATA_ES_12"
4296 "name": "SPI_SHADER_USER_DATA_ES_13"
4301 "name": "SPI_SHADER_USER_DATA_ES_14"
4306 "name": "SPI_SHADER_USER_DATA_ES_15"
4311 "name": "SPI_SHADER_TBA_LO_HS"
4316 "name": "SPI_SHADER_TBA_HI_HS",
4322 "name": "SPI_SHADER_TMA_LO_HS"
4327 "name": "SPI_SHADER_TMA_HI_HS",
4333 "name": "SPI_SHADER_PGM_LO_HS"
4338 "name": "SPI_SHADER_PGM_HI_HS",
4344 "name": "SPI_SHADER_PGM_RSRC1_HS",
4350 "name": "SPI_SHADER_PGM_RSRC2_HS",
4356 "name": "SPI_SHADER_USER_DATA_HS_0"
4361 "name": "SPI_SHADER_USER_DATA_HS_1"
4366 "name": "SPI_SHADER_USER_DATA_HS_2"
4371 "name": "SPI_SHADER_USER_DATA_HS_3"
4376 "name": "SPI_SHADER_USER_DATA_HS_4"
4381 "name": "SPI_SHADER_USER_DATA_HS_5"
4386 "name": "SPI_SHADER_USER_DATA_HS_6"
4391 "name": "SPI_SHADER_USER_DATA_HS_7"
4396 "name": "SPI_SHADER_USER_DATA_HS_8"
4401 "name": "SPI_SHADER_USER_DATA_HS_9"
4406 "name": "SPI_SHADER_USER_DATA_HS_10"
4411 "name": "SPI_SHADER_USER_DATA_HS_11"
4416 "name": "SPI_SHADER_USER_DATA_HS_12"
4421 "name": "SPI_SHADER_USER_DATA_HS_13"
4426 "name": "SPI_SHADER_USER_DATA_HS_14"
4431 "name": "SPI_SHADER_USER_DATA_HS_15"
4436 "name": "SPI_SHADER_TBA_LO_LS"
4441 "name": "SPI_SHADER_TBA_HI_LS",
4447 "name": "SPI_SHADER_TMA_LO_LS"
4452 "name": "SPI_SHADER_TMA_HI_LS",
4458 "name": "SPI_SHADER_PGM_LO_LS"
4463 "name": "SPI_SHADER_PGM_HI_LS",
4469 "name": "SPI_SHADER_PGM_RSRC1_LS",
4475 "name": "SPI_SHADER_PGM_RSRC2_LS",
4481 "name": "SPI_SHADER_USER_DATA_LS_0"
4486 "name": "SPI_SHADER_USER_DATA_LS_1"
4491 "name": "SPI_SHADER_USER_DATA_LS_2"
4496 "name": "SPI_SHADER_USER_DATA_LS_3"
4501 "name": "SPI_SHADER_USER_DATA_LS_4"
4506 "name": "SPI_SHADER_USER_DATA_LS_5"
4511 "name": "SPI_SHADER_USER_DATA_LS_6"
4516 "name": "SPI_SHADER_USER_DATA_LS_7"
4521 "name": "SPI_SHADER_USER_DATA_LS_8"
4526 "name": "SPI_SHADER_USER_DATA_LS_9"
4531 "name": "SPI_SHADER_USER_DATA_LS_10"
4536 "name": "SPI_SHADER_USER_DATA_LS_11"
4541 "name": "SPI_SHADER_USER_DATA_LS_12"
4546 "name": "SPI_SHADER_USER_DATA_LS_13"
4551 "name": "SPI_SHADER_USER_DATA_LS_14"
4556 "name": "SPI_SHADER_USER_DATA_LS_15"
4561 "name": "COMPUTE_DISPATCH_INITIATOR",
4567 "name": "COMPUTE_DIM_X"
4572 "name": "COMPUTE_DIM_Y"
4577 "name": "COMPUTE_DIM_Z"
4582 "name": "COMPUTE_START_X"
4587 "name": "COMPUTE_START_Y"
4592 "name": "COMPUTE_START_Z"
4597 "name": "COMPUTE_NUM_THREAD_X",
4603 "name": "COMPUTE_NUM_THREAD_Y",
4609 "name": "COMPUTE_NUM_THREAD_Z",
4615 "name": "COMPUTE_PGM_LO"
4620 "name": "COMPUTE_PGM_HI",
4626 "name": "COMPUTE_TBA_LO"
4631 "name": "COMPUTE_TBA_HI",
4637 "name": "COMPUTE_TMA_LO"
4642 "name": "COMPUTE_TMA_HI",
4648 "name": "COMPUTE_PGM_RSRC1",
4654 "name": "COMPUTE_PGM_RSRC2",
4660 "name": "COMPUTE_VMID",
4666 "name": "COMPUTE_RESOURCE_LIMITS",
4672 "name": "COMPUTE_STATIC_THREAD_MGMT_SE0",
4678 "name": "COMPUTE_STATIC_THREAD_MGMT_SE1",
4684 "name": "COMPUTE_TMPRING_SIZE",
4690 "name": "COMPUTE_USER_DATA_0"
4695 "name": "COMPUTE_USER_DATA_1"
4700 "name": "COMPUTE_USER_DATA_2"
4705 "name": "COMPUTE_USER_DATA_3"
4710 "name": "COMPUTE_USER_DATA_4"
4715 "name": "COMPUTE_USER_DATA_5"
4720 "name": "COMPUTE_USER_DATA_6"
4725 "name": "COMPUTE_USER_DATA_7"
4730 "name": "COMPUTE_USER_DATA_8"
4735 "name": "COMPUTE_USER_DATA_9"
4740 "name": "COMPUTE_USER_DATA_10"
4745 "name": "COMPUTE_USER_DATA_11"
4750 "name": "COMPUTE_USER_DATA_12"
4755 "name": "COMPUTE_USER_DATA_13"
4760 "name": "COMPUTE_USER_DATA_14"
4765 "name": "COMPUTE_USER_DATA_15"
4770 "name": "DB_RENDER_CONTROL",
4776 "name": "DB_COUNT_CONTROL",
4782 "name": "DB_DEPTH_VIEW",
4788 "name": "DB_RENDER_OVERRIDE",
4794 "name": "DB_RENDER_OVERRIDE2",
4800 "name": "DB_HTILE_DATA_BASE"
4805 "name": "DB_DEPTH_BOUNDS_MIN"
4810 "name": "DB_DEPTH_BOUNDS_MAX"
4815 "name": "DB_STENCIL_CLEAR",
4821 "name": "DB_DEPTH_CLEAR"
4826 "name": "PA_SC_SCREEN_SCISSOR_TL",
4832 "name": "PA_SC_SCREEN_SCISSOR_BR",
4838 "name": "DB_DEPTH_INFO",
4844 "name": "DB_Z_INFO",
4850 "name": "DB_STENCIL_INFO",
4856 "name": "DB_Z_READ_BASE"
4861 "name": "DB_STENCIL_READ_BASE"
4866 "name": "DB_Z_WRITE_BASE"
4871 "name": "DB_STENCIL_WRITE_BASE"
4876 "name": "DB_DEPTH_SIZE",
4882 "name": "DB_DEPTH_SLICE",
4888 "name": "TA_BC_BASE_ADDR"
4893 "name": "COHER_DEST_BASE_2"
4898 "name": "COHER_DEST_BASE_3"
4903 "name": "PA_SC_WINDOW_OFFSET",
4909 "name": "PA_SC_WINDOW_SCISSOR_TL",
4915 "name": "PA_SC_WINDOW_SCISSOR_BR",
4921 "name": "PA_SC_CLIPRECT_RULE",
4927 "name": "PA_SC_CLIPRECT_0_TL",
4933 "name": "PA_SC_CLIPRECT_0_BR",
4939 "name": "PA_SC_CLIPRECT_1_TL",
4945 "name": "PA_SC_CLIPRECT_1_BR",
4951 "name": "PA_SC_CLIPRECT_2_TL",
4957 "name": "PA_SC_CLIPRECT_2_BR",
4963 "name": "PA_SC_CLIPRECT_3_TL",
4969 "name": "PA_SC_CLIPRECT_3_BR",
4975 "name": "PA_SC_EDGERULE",
4981 "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
4987 "name": "CB_TARGET_MASK",
4993 "name": "CB_SHADER_MASK",
4999 "name": "PA_SC_GENERIC_SCISSOR_TL",
5005 "name": "PA_SC_GENERIC_SCISSOR_BR",
5011 "name": "COHER_DEST_BASE_0"
5016 "name": "COHER_DEST_BASE_1"
5021 "name": "PA_SC_VPORT_SCISSOR_0_TL",
5027 "name": "PA_SC_VPORT_SCISSOR_0_BR",
5033 "name": "PA_SC_VPORT_SCISSOR_1_TL",
5039 "name": "PA_SC_VPORT_SCISSOR_1_BR",
5045 "name": "PA_SC_VPORT_SCISSOR_2_TL",
5051 "name": "PA_SC_VPORT_SCISSOR_2_BR",
5057 "name": "PA_SC_VPORT_SCISSOR_3_TL",
5063 "name": "PA_SC_VPORT_SCISSOR_3_BR",
5069 "name": "PA_SC_VPORT_SCISSOR_4_TL",
5075 "name": "PA_SC_VPORT_SCISSOR_4_BR",
5081 "name": "PA_SC_VPORT_SCISSOR_5_TL",
5087 "name": "PA_SC_VPORT_SCISSOR_5_BR",
5093 "name": "PA_SC_VPORT_SCISSOR_6_TL",
5099 "name": "PA_SC_VPORT_SCISSOR_6_BR",
5105 "name": "PA_SC_VPORT_SCISSOR_7_TL",
5111 "name": "PA_SC_VPORT_SCISSOR_7_BR",
5117 "name": "PA_SC_VPORT_SCISSOR_8_TL",
5123 "name": "PA_SC_VPORT_SCISSOR_8_BR",
5129 "name": "PA_SC_VPORT_SCISSOR_9_TL",
5135 "name": "PA_SC_VPORT_SCISSOR_9_BR",
5141 "name": "PA_SC_VPORT_SCISSOR_10_TL",
5147 "name": "PA_SC_VPORT_SCISSOR_10_BR",
5153 "name": "PA_SC_VPORT_SCISSOR_11_TL",
5159 "name": "PA_SC_VPORT_SCISSOR_11_BR",
5165 "name": "PA_SC_VPORT_SCISSOR_12_TL",
5171 "name": "PA_SC_VPORT_SCISSOR_12_BR",
5177 "name": "PA_SC_VPORT_SCISSOR_13_TL",
5183 "name": "PA_SC_VPORT_SCISSOR_13_BR",
5189 "name": "PA_SC_VPORT_SCISSOR_14_TL",
5195 "name": "PA_SC_VPORT_SCISSOR_14_BR",
5201 "name": "PA_SC_VPORT_SCISSOR_15_TL",
5207 "name": "PA_SC_VPORT_SCISSOR_15_BR",
5213 "name": "PA_SC_VPORT_ZMIN_0"
5218 "name": "PA_SC_VPORT_ZMAX_0"
5223 "name": "PA_SC_VPORT_ZMIN_1"
5228 "name": "PA_SC_VPORT_ZMAX_1"
5233 "name": "PA_SC_VPORT_ZMIN_2"
5238 "name": "PA_SC_VPORT_ZMAX_2"
5243 "name": "PA_SC_VPORT_ZMIN_3"
5248 "name": "PA_SC_VPORT_ZMAX_3"
5253 "name": "PA_SC_VPORT_ZMIN_4"
5258 "name": "PA_SC_VPORT_ZMAX_4"
5263 "name": "PA_SC_VPORT_ZMIN_5"
5268 "name": "PA_SC_VPORT_ZMAX_5"
5273 "name": "PA_SC_VPORT_ZMIN_6"
5278 "name": "PA_SC_VPORT_ZMAX_6"
5283 "name": "PA_SC_VPORT_ZMIN_7"
5288 "name": "PA_SC_VPORT_ZMAX_7"
5293 "name": "PA_SC_VPORT_ZMIN_8"
5298 "name": "PA_SC_VPORT_ZMAX_8"
5303 "name": "PA_SC_VPORT_ZMIN_9"
5308 "name": "PA_SC_VPORT_ZMAX_9"
5313 "name": "PA_SC_VPORT_ZMIN_10"
5318 "name": "PA_SC_VPORT_ZMAX_10"
5323 "name": "PA_SC_VPORT_ZMIN_11"
5328 "name": "PA_SC_VPORT_ZMAX_11"
5333 "name": "PA_SC_VPORT_ZMIN_12"
5338 "name": "PA_SC_VPORT_ZMAX_12"
5343 "name": "PA_SC_VPORT_ZMIN_13"
5348 "name": "PA_SC_VPORT_ZMAX_13"
5353 "name": "PA_SC_VPORT_ZMIN_14"
5358 "name": "PA_SC_VPORT_ZMAX_14"
5363 "name": "PA_SC_VPORT_ZMIN_15"
5368 "name": "PA_SC_VPORT_ZMAX_15"
5373 "name": "PA_SC_RASTER_CONFIG",
5379 "name": "CP_PERFMON_CNTX_CNTL",
5385 "name": "CP_RINGID",
5391 "name": "CP_VMID",
5397 "name": "VGT_MAX_VTX_INDX"
5402 "name": "VGT_MIN_VTX_INDX"
5407 "name": "VGT_INDX_OFFSET"
5412 "name": "VGT_MULTI_PRIM_IB_RESET_INDX"
5417 "name": "CB_BLEND_RED"
5422 "name": "CB_BLEND_GREEN"
5427 "name": "CB_BLEND_BLUE"
5432 "name": "CB_BLEND_ALPHA"
5437 "name": "DB_STENCIL_CONTROL",
5443 "name": "DB_STENCILREFMASK",
5449 "name": "DB_STENCILREFMASK_BF",
5455 "name": "PA_CL_VPORT_XSCALE"
5460 "name": "PA_CL_VPORT_XOFFSET"
5465 "name": "PA_CL_VPORT_YSCALE"
5470 "name": "PA_CL_VPORT_YOFFSET"
5475 "name": "PA_CL_VPORT_ZSCALE"
5480 "name": "PA_CL_VPORT_ZOFFSET"
5485 "name": "PA_CL_VPORT_XSCALE_1"
5490 "name": "PA_CL_VPORT_XOFFSET_1"
5495 "name": "PA_CL_VPORT_YSCALE_1"
5500 "name": "PA_CL_VPORT_YOFFSET_1"
5505 "name": "PA_CL_VPORT_ZSCALE_1"
5510 "name": "PA_CL_VPORT_ZOFFSET_1"
5515 "name": "PA_CL_VPORT_XSCALE_2"
5520 "name": "PA_CL_VPORT_XOFFSET_2"
5525 "name": "PA_CL_VPORT_YSCALE_2"
5530 "name": "PA_CL_VPORT_YOFFSET_2"
5535 "name": "PA_CL_VPORT_ZSCALE_2"
5540 "name": "PA_CL_VPORT_ZOFFSET_2"
5545 "name": "PA_CL_VPORT_XSCALE_3"
5550 "name": "PA_CL_VPORT_XOFFSET_3"
5555 "name": "PA_CL_VPORT_YSCALE_3"
5560 "name": "PA_CL_VPORT_YOFFSET_3"
5565 "name": "PA_CL_VPORT_ZSCALE_3"
5570 "name": "PA_CL_VPORT_ZOFFSET_3"
5575 "name": "PA_CL_VPORT_XSCALE_4"
5580 "name": "PA_CL_VPORT_XOFFSET_4"
5585 "name": "PA_CL_VPORT_YSCALE_4"
5590 "name": "PA_CL_VPORT_YOFFSET_4"
5595 "name": "PA_CL_VPORT_ZSCALE_4"
5600 "name": "PA_CL_VPORT_ZOFFSET_4"
5605 "name": "PA_CL_VPORT_XSCALE_5"
5610 "name": "PA_CL_VPORT_XOFFSET_5"
5615 "name": "PA_CL_VPORT_YSCALE_5"
5620 "name": "PA_CL_VPORT_YOFFSET_5"
5625 "name": "PA_CL_VPORT_ZSCALE_5"
5630 "name": "PA_CL_VPORT_ZOFFSET_5"
5635 "name": "PA_CL_VPORT_XSCALE_6"
5640 "name": "PA_CL_VPORT_XOFFSET_6"
5645 "name": "PA_CL_VPORT_YSCALE_6"
5650 "name": "PA_CL_VPORT_YOFFSET_6"
5655 "name": "PA_CL_VPORT_ZSCALE_6"
5660 "name": "PA_CL_VPORT_ZOFFSET_6"
5665 "name": "PA_CL_VPORT_XSCALE_7"
5670 "name": "PA_CL_VPORT_XOFFSET_7"
5675 "name": "PA_CL_VPORT_YSCALE_7"
5680 "name": "PA_CL_VPORT_YOFFSET_7"
5685 "name": "PA_CL_VPORT_ZSCALE_7"
5690 "name": "PA_CL_VPORT_ZOFFSET_7"
5695 "name": "PA_CL_VPORT_XSCALE_8"
5700 "name": "PA_CL_VPORT_XOFFSET_8"
5705 "name": "PA_CL_VPORT_YSCALE_8"
5710 "name": "PA_CL_VPORT_YOFFSET_8"
5715 "name": "PA_CL_VPORT_ZSCALE_8"
5720 "name": "PA_CL_VPORT_ZOFFSET_8"
5725 "name": "PA_CL_VPORT_XSCALE_9"
5730 "name": "PA_CL_VPORT_XOFFSET_9"
5735 "name": "PA_CL_VPORT_YSCALE_9"
5740 "name": "PA_CL_VPORT_YOFFSET_9"
5745 "name": "PA_CL_VPORT_ZSCALE_9"
5750 "name": "PA_CL_VPORT_ZOFFSET_9"
5755 "name": "PA_CL_VPORT_XSCALE_10"
5760 "name": "PA_CL_VPORT_XOFFSET_10"
5765 "name": "PA_CL_VPORT_YSCALE_10"
5770 "name": "PA_CL_VPORT_YOFFSET_10"
5775 "name": "PA_CL_VPORT_ZSCALE_10"
5780 "name": "PA_CL_VPORT_ZOFFSET_10"
5785 "name": "PA_CL_VPORT_XSCALE_11"
5790 "name": "PA_CL_VPORT_XOFFSET_11"
5795 "name": "PA_CL_VPORT_YSCALE_11"
5800 "name": "PA_CL_VPORT_YOFFSET_11"
5805 "name": "PA_CL_VPORT_ZSCALE_11"
5810 "name": "PA_CL_VPORT_ZOFFSET_11"
5815 "name": "PA_CL_VPORT_XSCALE_12"
5820 "name": "PA_CL_VPORT_XOFFSET_12"
5825 "name": "PA_CL_VPORT_YSCALE_12"
5830 "name": "PA_CL_VPORT_YOFFSET_12"
5835 "name": "PA_CL_VPORT_ZSCALE_12"
5840 "name": "PA_CL_VPORT_ZOFFSET_12"
5845 "name": "PA_CL_VPORT_XSCALE_13"
5850 "name": "PA_CL_VPORT_XOFFSET_13"
5855 "name": "PA_CL_VPORT_YSCALE_13"
5860 "name": "PA_CL_VPORT_YOFFSET_13"
5865 "name": "PA_CL_VPORT_ZSCALE_13"
5870 "name": "PA_CL_VPORT_ZOFFSET_13"
5875 "name": "PA_CL_VPORT_XSCALE_14"
5880 "name": "PA_CL_VPORT_XOFFSET_14"
5885 "name": "PA_CL_VPORT_YSCALE_14"
5890 "name": "PA_CL_VPORT_YOFFSET_14"
5895 "name": "PA_CL_VPORT_ZSCALE_14"
5900 "name": "PA_CL_VPORT_ZOFFSET_14"
5905 "name": "PA_CL_VPORT_XSCALE_15"
5910 "name": "PA_CL_VPORT_XOFFSET_15"
5915 "name": "PA_CL_VPORT_YSCALE_15"
5920 "name": "PA_CL_VPORT_YOFFSET_15"
5925 "name": "PA_CL_VPORT_ZSCALE_15"
5930 "name": "PA_CL_VPORT_ZOFFSET_15"
5935 "name": "PA_CL_UCP_0_X"
5940 "name": "PA_CL_UCP_0_Y"
5945 "name": "PA_CL_UCP_0_Z"
5950 "name": "PA_CL_UCP_0_W"
5955 "name": "PA_CL_UCP_1_X"
5960 "name": "PA_CL_UCP_1_Y"
5965 "name": "PA_CL_UCP_1_Z"
5970 "name": "PA_CL_UCP_1_W"
5975 "name": "PA_CL_UCP_2_X"
5980 "name": "PA_CL_UCP_2_Y"
5985 "name": "PA_CL_UCP_2_Z"
5990 "name": "PA_CL_UCP_2_W"
5995 "name": "PA_CL_UCP_3_X"
6000 "name": "PA_CL_UCP_3_Y"
6005 "name": "PA_CL_UCP_3_Z"
6010 "name": "PA_CL_UCP_3_W"
6015 "name": "PA_CL_UCP_4_X"
6020 "name": "PA_CL_UCP_4_Y"
6025 "name": "PA_CL_UCP_4_Z"
6030 "name": "PA_CL_UCP_4_W"
6035 "name": "PA_CL_UCP_5_X"
6040 "name": "PA_CL_UCP_5_Y"
6045 "name": "PA_CL_UCP_5_Z"
6050 "name": "PA_CL_UCP_5_W"
6055 "name": "SPI_PS_INPUT_CNTL_0",
6061 "name": "SPI_PS_INPUT_CNTL_1",
6067 "name": "SPI_PS_INPUT_CNTL_2",
6073 "name": "SPI_PS_INPUT_CNTL_3",
6079 "name": "SPI_PS_INPUT_CNTL_4",
6085 "name": "SPI_PS_INPUT_CNTL_5",
6091 "name": "SPI_PS_INPUT_CNTL_6",
6097 "name": "SPI_PS_INPUT_CNTL_7",
6103 "name": "SPI_PS_INPUT_CNTL_8",
6109 "name": "SPI_PS_INPUT_CNTL_9",
6115 "name": "SPI_PS_INPUT_CNTL_10",
6121 "name": "SPI_PS_INPUT_CNTL_11",
6127 "name": "SPI_PS_INPUT_CNTL_12",
6133 "name": "SPI_PS_INPUT_CNTL_13",
6139 "name": "SPI_PS_INPUT_CNTL_14",
6145 "name": "SPI_PS_INPUT_CNTL_15",
6151 "name": "SPI_PS_INPUT_CNTL_16",
6157 "name": "SPI_PS_INPUT_CNTL_17",
6163 "name": "SPI_PS_INPUT_CNTL_18",
6169 "name": "SPI_PS_INPUT_CNTL_19",
6175 "name": "SPI_PS_INPUT_CNTL_20",
6181 "name": "SPI_PS_INPUT_CNTL_21",
6187 "name": "SPI_PS_INPUT_CNTL_22",
6193 "name": "SPI_PS_INPUT_CNTL_23",
6199 "name": "SPI_PS_INPUT_CNTL_24",
6205 "name": "SPI_PS_INPUT_CNTL_25",
6211 "name": "SPI_PS_INPUT_CNTL_26",
6217 "name": "SPI_PS_INPUT_CNTL_27",
6223 "name": "SPI_PS_INPUT_CNTL_28",
6229 "name": "SPI_PS_INPUT_CNTL_29",
6235 "name": "SPI_PS_INPUT_CNTL_30",
6241 "name": "SPI_PS_INPUT_CNTL_31",
6247 "name": "SPI_VS_OUT_CONFIG",
6253 "name": "SPI_PS_INPUT_ENA",
6259 "name": "SPI_PS_INPUT_ADDR",
6265 "name": "SPI_INTERP_CONTROL_0",
6271 "name": "SPI_PS_IN_CONTROL",
6277 "name": "SPI_BARYC_CNTL",
6283 "name": "SPI_TMPRING_SIZE",
6289 "name": "SPI_SHADER_POS_FORMAT",
6295 "name": "SPI_SHADER_Z_FORMAT",
6301 "name": "SPI_SHADER_COL_FORMAT",
6307 "name": "CB_BLEND0_CONTROL",
6313 "name": "CB_BLEND1_CONTROL",
6319 "name": "CB_BLEND2_CONTROL",
6325 "name": "CB_BLEND3_CONTROL",
6331 "name": "CB_BLEND4_CONTROL",
6337 "name": "CB_BLEND5_CONTROL",
6343 "name": "CB_BLEND6_CONTROL",
6349 "name": "CB_BLEND7_CONTROL",
6355 "name": "CS_COPY_STATE",
6361 "name": "GFX_COPY_STATE",
6367 "name": "PA_CL_POINT_X_RAD"
6372 "name": "PA_CL_POINT_Y_RAD"
6377 "name": "PA_CL_POINT_SIZE"
6382 "name": "PA_CL_POINT_CULL_RAD"
6387 "name": "VGT_DMA_BASE_HI",
6393 "name": "VGT_DMA_BASE"
6398 "name": "VGT_DRAW_INITIATOR",
6404 "name": "VGT_IMMED_DATA"
6409 "name": "VGT_EVENT_ADDRESS_REG",
6415 "name": "DB_DEPTH_CONTROL",
6421 "name": "DB_EQAA",
6427 "name": "CB_COLOR_CONTROL",
6433 "name": "DB_SHADER_CONTROL",
6439 "name": "PA_CL_CLIP_CNTL",
6445 "name": "PA_SU_SC_MODE_CNTL",
6451 "name": "PA_CL_VTE_CNTL",
6457 "name": "PA_CL_VS_OUT_CNTL",
6463 "name": "PA_CL_NANINF_CNTL",
6469 "name": "PA_SU_LINE_STIPPLE_CNTL",
6475 "name": "PA_SU_LINE_STIPPLE_SCALE"
6480 "name": "PA_SU_PRIM_FILTER_CNTL",
6486 "name": "PA_SU_POINT_SIZE",
6492 "name": "PA_SU_POINT_MINMAX",
6498 "name": "PA_SU_LINE_CNTL",
6504 "name": "PA_SC_LINE_STIPPLE",
6510 "name": "VGT_OUTPUT_PATH_CNTL",
6516 "name": "VGT_HOS_CNTL",
6522 "name": "VGT_HOS_MAX_TESS_LEVEL"
6527 "name": "VGT_HOS_MIN_TESS_LEVEL"
6532 "name": "VGT_HOS_REUSE_DEPTH",
6538 "name": "VGT_GROUP_PRIM_TYPE",
6544 "name": "VGT_GROUP_FIRST_DECR",
6550 "name": "VGT_GROUP_DECR",
6556 "name": "VGT_GROUP_VECT_0_CNTL",
6562 "name": "VGT_GROUP_VECT_1_CNTL",
6568 "name": "VGT_GROUP_VECT_0_FMT_CNTL",
6574 "name": "VGT_GROUP_VECT_1_FMT_CNTL",
6580 "name": "VGT_GS_MODE",
6586 "name": "PA_SC_MODE_CNTL_0",
6592 "name": "PA_SC_MODE_CNTL_1",
6598 "name": "VGT_ENHANCE"
6603 "name": "VGT_GS_PER_ES",
6609 "name": "VGT_ES_PER_GS",
6615 "name": "VGT_GS_PER_VS",
6621 "name": "VGT_GSVS_RING_OFFSET_1",
6627 "name": "VGT_GSVS_RING_OFFSET_2",
6633 "name": "VGT_GSVS_RING_OFFSET_3",
6639 "name": "VGT_GS_OUT_PRIM_TYPE",
6645 "name": "IA_ENHANCE"
6650 "name": "VGT_DMA_SIZE"
6655 "name": "VGT_DMA_MAX_SIZE"
6660 "name": "VGT_DMA_INDEX_TYPE",
6666 "name": "VGT_PRIMITIVEID_EN",
6672 "name": "VGT_DMA_NUM_INSTANCES"
6677 "name": "VGT_PRIMITIVEID_RESET"
6682 "name": "VGT_EVENT_INITIATOR",
6688 "name": "VGT_MULTI_PRIM_IB_RESET_EN",
6694 "name": "VGT_INSTANCE_STEP_RATE_0"
6699 "name": "VGT_INSTANCE_STEP_RATE_1"
6704 "name": "IA_MULTI_VGT_PARAM",
6710 "name": "VGT_ESGS_RING_ITEMSIZE",
6716 "name": "VGT_GSVS_RING_ITEMSIZE",
6722 "name": "VGT_REUSE_OFF",
6728 "name": "VGT_VTX_CNT_EN",
6734 "name": "DB_HTILE_SURFACE",
6740 "name": "DB_SRESULTS_COMPARE_STATE0",
6746 "name": "DB_SRESULTS_COMPARE_STATE1",
6752 "name": "DB_PRELOAD_CONTROL",
6758 "name": "VGT_STRMOUT_BUFFER_SIZE_0"
6763 "name": "VGT_STRMOUT_VTX_STRIDE_0",
6769 "name": "VGT_STRMOUT_BUFFER_OFFSET_0"
6774 "name": "VGT_STRMOUT_BUFFER_SIZE_1"
6779 "name": "VGT_STRMOUT_VTX_STRIDE_1",
6785 "name": "VGT_STRMOUT_BUFFER_OFFSET_1"
6790 "name": "VGT_STRMOUT_BUFFER_SIZE_2"
6795 "name": "VGT_STRMOUT_VTX_STRIDE_2",
6801 "name": "VGT_STRMOUT_BUFFER_OFFSET_2"
6806 "name": "VGT_STRMOUT_BUFFER_SIZE_3"
6811 "name": "VGT_STRMOUT_VTX_STRIDE_3",
6817 "name": "VGT_STRMOUT_BUFFER_OFFSET_3"
6822 "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET"
6827 "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE"
6832 "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
6838 "name": "VGT_GS_MAX_VERT_OUT",
6844 "name": "VGT_SHADER_STAGES_EN",
6850 "name": "VGT_LS_HS_CONFIG",
6856 "name": "VGT_GS_VERT_ITEMSIZE",
6862 "name": "VGT_GS_VERT_ITEMSIZE_1",
6868 "name": "VGT_GS_VERT_ITEMSIZE_2",
6874 "name": "VGT_GS_VERT_ITEMSIZE_3",
6880 "name": "VGT_TF_PARAM",
6886 "name": "DB_ALPHA_TO_MASK",
6892 "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
6898 "name": "PA_SU_POLY_OFFSET_CLAMP"
6903 "name": "PA_SU_POLY_OFFSET_FRONT_SCALE"
6908 "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
6913 "name": "PA_SU_POLY_OFFSET_BACK_SCALE"
6918 "name": "PA_SU_POLY_OFFSET_BACK_OFFSET"
6923 "name": "VGT_GS_INSTANCE_CNT",
6929 "name": "VGT_STRMOUT_CONFIG",
6935 "name": "VGT_STRMOUT_BUFFER_CONFIG",
6941 "name": "PA_SC_CENTROID_PRIORITY_0",
6947 "name": "PA_SC_CENTROID_PRIORITY_1",
6953 "name": "PA_SC_LINE_CNTL",
6959 "name": "PA_SC_AA_CONFIG",
6965 "name": "PA_SU_VTX_CNTL",
6971 "name": "PA_CL_GB_VERT_CLIP_ADJ"
6976 "name": "PA_CL_GB_VERT_DISC_ADJ"
6981 "name": "PA_CL_GB_HORZ_CLIP_ADJ"
6986 "name": "PA_CL_GB_HORZ_DISC_ADJ"
6991 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
6997 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
7003 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
7009 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
7015 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
7021 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
7027 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
7033 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
7039 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
7045 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
7051 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
7057 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
7063 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
7069 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
7075 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
7081 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
7087 "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
7093 "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
7099 "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
7105 "name": "VGT_OUT_DEALLOC_CNTL",
7111 "name": "CB_COLOR0_BASE"
7116 "name": "CB_COLOR0_PITCH",
7122 "name": "CB_COLOR0_SLICE",
7128 "name": "CB_COLOR0_VIEW",
7134 "name": "CB_COLOR0_INFO",
7140 "name": "CB_COLOR0_ATTRIB",
7146 "name": "CB_COLOR0_CMASK"
7151 "name": "CB_COLOR0_CMASK_SLICE",
7157 "name": "CB_COLOR0_FMASK"
7162 "name": "CB_COLOR0_FMASK_SLICE",
7168 "name": "CB_COLOR0_CLEAR_WORD0"
7173 "name": "CB_COLOR0_CLEAR_WORD1"
7178 "name": "CB_COLOR1_BASE"
7183 "name": "CB_COLOR1_PITCH",
7189 "name": "CB_COLOR1_SLICE",
7195 "name": "CB_COLOR1_VIEW",
7201 "name": "CB_COLOR1_INFO",
7207 "name": "CB_COLOR1_ATTRIB",
7213 "name": "CB_COLOR1_CMASK"
7218 "name": "CB_COLOR1_CMASK_SLICE",
7224 "name": "CB_COLOR1_FMASK"
7229 "name": "CB_COLOR1_FMASK_SLICE",
7235 "name": "CB_COLOR1_CLEAR_WORD0"
7240 "name": "CB_COLOR1_CLEAR_WORD1"
7245 "name": "CB_COLOR2_BASE"
7250 "name": "CB_COLOR2_PITCH",
7256 "name": "CB_COLOR2_SLICE",
7262 "name": "CB_COLOR2_VIEW",
7268 "name": "CB_COLOR2_INFO",
7274 "name": "CB_COLOR2_ATTRIB",
7280 "name": "CB_COLOR2_CMASK"
7285 "name": "CB_COLOR2_CMASK_SLICE",
7291 "name": "CB_COLOR2_FMASK"
7296 "name": "CB_COLOR2_FMASK_SLICE",
7302 "name": "CB_COLOR2_CLEAR_WORD0"
7307 "name": "CB_COLOR2_CLEAR_WORD1"
7312 "name": "CB_COLOR3_BASE"
7317 "name": "CB_COLOR3_PITCH",
7323 "name": "CB_COLOR3_SLICE",
7329 "name": "CB_COLOR3_VIEW",
7335 "name": "CB_COLOR3_INFO",
7341 "name": "CB_COLOR3_ATTRIB",
7347 "name": "CB_COLOR3_CMASK"
7352 "name": "CB_COLOR3_CMASK_SLICE",
7358 "name": "CB_COLOR3_FMASK"
7363 "name": "CB_COLOR3_FMASK_SLICE",
7369 "name": "CB_COLOR3_CLEAR_WORD0"
7374 "name": "CB_COLOR3_CLEAR_WORD1"
7379 "name": "CB_COLOR4_BASE"
7384 "name": "CB_COLOR4_PITCH",
7390 "name": "CB_COLOR4_SLICE",
7396 "name": "CB_COLOR4_VIEW",
7402 "name": "CB_COLOR4_INFO",
7408 "name": "CB_COLOR4_ATTRIB",
7414 "name": "CB_COLOR4_CMASK"
7419 "name": "CB_COLOR4_CMASK_SLICE",
7425 "name": "CB_COLOR4_FMASK"
7430 "name": "CB_COLOR4_FMASK_SLICE",
7436 "name": "CB_COLOR4_CLEAR_WORD0"
7441 "name": "CB_COLOR4_CLEAR_WORD1"
7446 "name": "CB_COLOR5_BASE"
7451 "name": "CB_COLOR5_PITCH",
7457 "name": "CB_COLOR5_SLICE",
7463 "name": "CB_COLOR5_VIEW",
7469 "name": "CB_COLOR5_INFO",
7475 "name": "CB_COLOR5_ATTRIB",
7481 "name": "CB_COLOR5_CMASK"
7486 "name": "CB_COLOR5_CMASK_SLICE",
7492 "name": "CB_COLOR5_FMASK"
7497 "name": "CB_COLOR5_FMASK_SLICE",
7503 "name": "CB_COLOR5_CLEAR_WORD0"
7508 "name": "CB_COLOR5_CLEAR_WORD1"
7513 "name": "CB_COLOR6_BASE"
7518 "name": "CB_COLOR6_PITCH",
7524 "name": "CB_COLOR6_SLICE",
7530 "name": "CB_COLOR6_VIEW",
7536 "name": "CB_COLOR6_INFO",
7542 "name": "CB_COLOR6_ATTRIB",
7548 "name": "CB_COLOR6_CMASK"
7553 "name": "CB_COLOR6_CMASK_SLICE",
7559 "name": "CB_COLOR6_FMASK"
7564 "name": "CB_COLOR6_FMASK_SLICE",
7570 "name": "CB_COLOR6_CLEAR_WORD0"
7575 "name": "CB_COLOR6_CLEAR_WORD1"
7580 "name": "CB_COLOR7_BASE"
7585 "name": "CB_COLOR7_PITCH",
7591 "name": "CB_COLOR7_SLICE",
7597 "name": "CB_COLOR7_VIEW",
7603 "name": "CB_COLOR7_INFO",
7609 "name": "CB_COLOR7_ATTRIB",
7615 "name": "CB_COLOR7_CMASK"
7620 "name": "CB_COLOR7_CMASK_SLICE",
7626 "name": "CB_COLOR7_FMASK"
7631 "name": "CB_COLOR7_FMASK_SLICE",
7637 "name": "CB_COLOR7_CLEAR_WORD0"
7642 "name": "CB_COLOR7_CLEAR_WORD1"
7648 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
7649 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
7650 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
7651 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
7652 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
7653 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
7654 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
7655 {"bits": [30, 30], "name": "ENABLE"},
7656 {"bits": [31, 31], "name": "DISABLE_ROP3"}
7661 {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
7662 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
7663 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
7664 {"bits": [12, 14], "name": "NUM_SAMPLES"},
7665 {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
7666 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}
7671 {"bits": [0, 13], "name": "TILE_MAX"}
7676 {"bits": [0, 21], "name": "TILE_MAX"}
7681 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
7682 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
7683 {"bits": [7, 7], "name": "LINEAR_GENERAL"},
7684 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
7685 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
7686 {"bits": [13, 13], "name": "FAST_CLEAR"},
7687 {"bits": [14, 14], "name": "COMPRESSION"},
7688 {"bits": [15, 15], "name": "BLEND_CLAMP"},
7689 {"bits": [16, 16], "name": "BLEND_BYPASS"},
7690 {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
7691 {"bits": [18, 18], "name": "ROUND_MODE"},
7692 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
7693 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
7694 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
7695 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"}
7700 {"bits": [0, 10], "name": "TILE_MAX"},
7701 {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
7706 {"bits": [0, 10], "name": "SLICE_START"},
7707 {"bits": [13, 23], "name": "SLICE_MAX"}
7712 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
7713 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
7714 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
7719 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
7720 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
7721 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
7722 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
7723 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
7724 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
7725 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
7726 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
7731 {"bits": [0, 3], "name": "TARGET0_ENABLE"},
7732 {"bits": [4, 7], "name": "TARGET1_ENABLE"},
7733 {"bits": [8, 11], "name": "TARGET2_ENABLE"},
7734 {"bits": [12, 15], "name": "TARGET3_ENABLE"},
7735 {"bits": [16, 19], "name": "TARGET4_ENABLE"},
7736 {"bits": [20, 23], "name": "TARGET5_ENABLE"},
7737 {"bits": [24, 27], "name": "TARGET6_ENABLE"},
7738 {"bits": [28, 31], "name": "TARGET7_ENABLE"}
7743 {"bits": [1, 2], "name": "DPFP_RATE"},
7744 {"bits": [3, 3], "name": "SQC_BALANCE_DISABLE"},
7745 {"bits": [4, 4], "name": "HALF_LDS"},
7746 {"bits": [16, 31], "name": "INACTIVE_CUS"}
7751 {"bits": [16, 19], "name": "SQC0_BANK_DISABLE"},
7752 {"bits": [20, 23], "name": "SQC1_BANK_DISABLE"},
7753 {"bits": [24, 27], "name": "SQC2_BANK_DISABLE"},
7754 {"bits": [28, 31], "name": "SQC3_BANK_DISABLE"}
7759 {"bits": [0, 3], "name": "ON_DELAY"},
7760 {"bits": [4, 11], "name": "OFF_HYSTERESIS"},
7761 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"},
7762 {"bits": [25, 25], "name": "PERF_ENABLE"},
7763 {"bits": [26, 26], "name": "DBG_ENABLE"},
7764 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"},
7765 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"},
7766 {"bits": [29, 29], "name": "CORE_OVERRIDE"},
7767 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"},
7768 {"bits": [31, 31], "name": "REG_OVERRIDE"}
7773 {"bits": [0, 3], "name": "ON_DELAY"},
7774 {"bits": [4, 11], "name": "OFF_HYSTERESIS"},
7775 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"},
7776 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"},
7777 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"},
7778 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"},
7779 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"},
7780 {"bits": [29, 29], "name": "SU_CLK_OVERRIDE"},
7781 {"bits": [30, 30], "name": "CL_CLK_OVERRIDE"},
7782 {"bits": [31, 31], "name": "REG_CLK_OVERRIDE"}
7787 {"bits": [0, 3], "name": "ON_DELAY"},
7788 {"bits": [4, 11], "name": "OFF_HYSTERESIS"},
7789 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"},
7790 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"},
7791 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"},
7792 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"},
7793 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"},
7794 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"},
7795 {"bits": [30, 30], "name": "SOFT_OVERRIDE1"},
7796 {"bits": [31, 31], "name": "SOFT_OVERRIDE0"}
7801 {"bits": [0, 3], "name": "ON_DELAY"},
7802 {"bits": [4, 11], "name": "OFF_HYSTERESIS"},
7803 {"bits": [30, 30], "name": "CORE_OVERRIDE"},
7804 {"bits": [31, 31], "name": "REG_OVERRIDE"}
7809 {"bits": [0, 3], "name": "ON_DELAY"},
7810 {"bits": [4, 11], "name": "OFF_HYSTERESIS"},
7811 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"},
7812 {"bits": [25, 25], "name": "PERF_ENABLE"},
7813 {"bits": [26, 26], "name": "DBG_ENABLE"},
7814 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"},
7815 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"},
7816 {"bits": [29, 29], "name": "GS_OVERRIDE"},
7817 {"bits": [30, 30], "name": "CORE_OVERRIDE"},
7818 {"bits": [31, 31], "name": "REG_OVERRIDE"}
7823 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
7824 {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
7825 {"bits": [2, 2], "name": "FORCE_START_AT_000"},
7826 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
7827 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
7828 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
7829 {"bits": [6, 6], "name": "ORDER_MODE"},
7830 {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"},
7831 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
7832 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
7833 {"bits": [12, 12], "name": "DATA_ATC"},
7834 {"bits": [14, 14], "name": "RESTORE"}
7839 {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
7840 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
7845 {"bits": [0, 7], "name": "DATA"},
7846 {"bits": [8, 8], "name": "INST_ATC"}
7851 {"bits": [0, 5], "name": "VGPRS"},
7852 {"bits": [6, 9], "name": "SGPRS"},
7853 {"bits": [10, 11], "name": "PRIORITY"},
7854 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
7855 {"bits": [20, 20], "name": "PRIV"},
7856 {"bits": [21, 21], "name": "DX10_CLAMP"},
7857 {"bits": [22, 22], "name": "DEBUG_MODE"},
7858 {"bits": [23, 23], "name": "IEEE_MODE"},
7859 {"bits": [24, 24], "name": "BULKY"},
7860 {"bits": [25, 25], "name": "CDBG_USER"}
7865 {"bits": [0, 0], "name": "SCRATCH_EN"},
7866 {"bits": [1, 5], "name": "USER_SGPR"},
7867 {"bits": [6, 6], "name": "TRAP_PRESENT"},
7868 {"bits": [7, 7], "name": "TGID_X_EN"},
7869 {"bits": [8, 8], "name": "TGID_Y_EN"},
7870 {"bits": [9, 9], "name": "TGID_Z_EN"},
7871 {"bits": [10, 10], "name": "TG_SIZE_EN"},
7872 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
7873 {"bits": [13, 14], "name": "EXCP_EN_MSB"},
7874 {"bits": [15, 23], "name": "LDS_SIZE"},
7875 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
7880 {"bits": [0, 5], "name": "WAVES_PER_SH"},
7881 {"bits": [0, 5], "name": "WAVES_PER_SH_GFX6"},
7882 {"bits": [12, 15], "name": "TG_PER_CU"},
7883 {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
7884 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
7885 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
7886 {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
7891 {"bits": [0, 15], "name": "SH0_CU_EN"},
7892 {"bits": [16, 31], "name": "SH1_CU_EN"}
7897 {"bits": [0, 7], "name": "DATA"}
7902 {"bits": [0, 11], "name": "WAVES"},
7903 {"bits": [12, 24], "name": "WAVESIZE"}
7908 {"bits": [0, 3], "name": "DATA"}
7913 {"bits": [0, 7], "name": "MEM_ADDR_HI"},
7914 {"bits": [16, 17], "name": "CS_PS_SEL"},
7915 {"bits": [29, 31], "name": "COMMAND"}
7920 {"bits": [2, 31], "name": "MEM_ADDR_LO"}
7925 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
7926 {"bits": [6, 6], "name": "COHER_CNT_NEQ_ZERO"},
7927 {"bits": [7, 7], "name": "PFP_PARSING_PACKETS"},
7928 {"bits": [8, 8], "name": "ME_PARSING_PACKETS"},
7929 {"bits": [9, 9], "name": "RCIU_PFP_BUSY"},
7930 {"bits": [10, 10], "name": "RCIU_ME_BUSY"},
7931 {"bits": [12, 12], "name": "SEM_CMDFIFO_NOT_EMPTY"},
7932 {"bits": [13, 13], "name": "SEM_FAILED_AND_HOLDING"},
7933 {"bits": [14, 14], "name": "SEM_POLLING_FOR_PASS"},
7934 {"bits": [15, 15], "name": "GFX_CONTEXT_BUSY"},
7935 {"bits": [17, 17], "name": "ME_PARSER_BUSY"},
7936 {"bits": [18, 18], "name": "EOP_DONE_BUSY"},
7937 {"bits": [19, 19], "name": "STRM_OUT_BUSY"},
7938 {"bits": [20, 20], "name": "PIPE_STATS_BUSY"},
7939 {"bits": [21, 21], "name": "RCIU_CE_BUSY"},
7940 {"bits": [22, 22], "name": "CE_PARSING_PACKETS"}
7945 {"bits": [0, 10], "name": "CEQ_CNT_RING"},
7946 {"bits": [16, 26], "name": "CEQ_CNT_IB1"}
7951 {"bits": [0, 10], "name": "CEQ_CNT_IB2"}
7956 {"bits": [0, 7], "name": "IB1_BASE_HI"}
7961 {"bits": [2, 31], "name": "IB1_BASE_LO"}
7966 {"bits": [0, 19], "name": "IB1_BUFSZ"}
7971 {"bits": [0, 7], "name": "IB2_BASE_HI"}
7976 {"bits": [2, 31], "name": "IB2_BASE_LO"}
7981 {"bits": [0, 19], "name": "IB2_BUFSZ"}
7986 {"bits": [0, 7], "name": "INIT_BASE_HI"}
7991 {"bits": [5, 31], "name": "INIT_BASE_LO"}
7996 {"bits": [0, 11], "name": "INIT_BUFSZ"}
8001 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT1"},
8002 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT1"}
8007 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT2"},
8008 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT2"}
8013 {"bits": [0, 9], "name": "CEQ_RPTR_PRIMARY"},
8014 {"bits": [16, 25], "name": "CEQ_WPTR_PRIMARY"}
8019 {"bits": [0, 10], "name": "CMD_INDEX"},
8020 {"bits": [12, 13], "name": "CMD_ME_SEL"},
8021 {"bits": [16, 17], "name": "CMD_QUEUE_SEL"}
8026 {"bits": [0, 7], "name": "ACTIVE_HP3D_CONTEXTS"},
8027 {"bits": [8, 10], "name": "CURRENT_HP3D_CONTEXT"},
8028 {"bits": [20, 27], "name": "ACTIVE_GFX_CONTEXTS"},
8029 {"bits": [28, 30], "name": "CURRENT_GFX_CONTEXT"}
8034 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
8035 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
8036 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
8037 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
8038 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
8039 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
8040 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
8041 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
8042 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
8043 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
8044 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
8045 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
8046 {"bits": [16, 16], "name": "TC_VOL_ACTION_ENA"},
8047 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
8048 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
8049 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"},
8050 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
8051 {"bits": [23, 23], "name": "TC_ACTION_ENA"},
8052 {"bits": [25, 25], "name": "CB_ACTION_ENA"},
8053 {"bits": [26, 26], "name": "DB_ACTION_ENA"},
8054 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
8055 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
8056 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"}
8061 {"bits": [0, 5], "name": "START_DELAY_COUNT"}
8066 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
8067 {"bits": [24, 25], "name": "MEID"},
8068 {"bits": [30, 30], "name": "PHASE1_STATUS"},
8069 {"bits": [31, 31], "name": "STATUS"}
8074 {"bits": [0, 3], "name": "FETCH_BUFFER_DEPTH"}
8079 {"bits": [0, 3], "name": "BUFFER_SLOTS_ALLOCATED"},
8080 {"bits": [8, 13], "name": "BUFFER_REQUEST_COUNT"}
8085 {"bits": [4, 5], "name": "MIN_AVAILSZ"},
8086 {"bits": [16, 19], "name": "BUFFER_DEPTH"},
8087 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
8088 {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
8089 {"bits": [30, 31], "name": "PIO_COUNT"}
8094 {"bits": [0, 20], "name": "BYTE_COUNT"},
8095 {"bits": [21, 21], "name": "DIS_WC"},
8096 {"bits": [22, 23], "name": "SRC_SWAP"},
8097 {"bits": [24, 25], "name": "DST_SWAP"},
8098 {"bits": [26, 26], "name": "SAS"},
8099 {"bits": [27, 27], "name": "DAS"},
8100 {"bits": [28, 28], "name": "SAIC"},
8101 {"bits": [29, 29], "name": "DAIC"},
8102 {"bits": [30, 30], "name": "RAW_WAIT"}
8107 {"bits": [0, 7], "name": "DST_ADDR_HI"}
8112 {"bits": [0, 7], "name": "SRC_ADDR_HI"}
8117 {"bits": [0, 25], "name": "DMA_READ_TAG"},
8118 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
8123 {"bits": [0, 15], "name": "ADDR_HI"}
8128 {"bits": [0, 1], "name": "ADDR_SWAP"},
8129 {"bits": [2, 31], "name": "ADDR_LO"}
8134 {"bits": [0, 5], "name": "FREE_COUNT"},
8135 {"bits": [8, 13], "name": "FREE_COUNT_GDS"},
8136 {"bits": [16, 21], "name": "FREE_COUNT_PFP"}
8141 {"bits": [0, 19], "name": "IB1_OFFSET"}
8146 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}
8151 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}
8156 {"bits": [0, 19], "name": "IB2_OFFSET"}
8161 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
8166 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
8171 {"bits": [14, 14], "name": "CP_ECC_ERROR_INT_ASSERTED"},
8172 {"bits": [17, 17], "name": "WRM_POLL_TIMEOUT_INT_ASSERTED"},
8173 {"bits": [19, 19], "name": "CNTX_BUSY_INT_ASSERTED"},
8174 {"bits": [20, 20], "name": "CNTX_EMPTY_INT_ASSERTED"},
8175 {"bits": [22, 22], "name": "PRIV_INSTR_INT_ASSERTED"},
8176 {"bits": [23, 23], "name": "PRIV_REG_INT_ASSERTED"},
8177 {"bits": [24, 24], "name": "OPCODE_ERROR_INT_ASSERTED"},
8178 {"bits": [26, 26], "name": "TIME_STAMP_INT_ASSERTED"},
8179 {"bits": [27, 27], "name": "RESERVED_BIT_ERROR_INT_ASSERTED"},
8180 {"bits": [29, 29], "name": "GENERIC2_INT_ASSERTED"},
8181 {"bits": [30, 30], "name": "GENERIC1_INT_ASSERTED"},
8182 {"bits": [31, 31], "name": "GENERIC0_INT_ASSERTED"}
8187 {"bits": [0, 4], "name": "PACK_DELAY_CNT"}
8192 {"bits": [0, 9], "name": "MEQ_CNT"}
8197 {"bits": [0, 9], "name": "MEQ_RPTR"},
8198 {"bits": [16, 25], "name": "MEQ_WPTR"}
8203 {"bits": [0, 7], "name": "MEQ1_START"},
8204 {"bits": [8, 15], "name": "MEQ2_START"}
8209 {"bits": [4, 4], "name": "CE_INVALIDATE_ICACHE"},
8210 {"bits": [6, 6], "name": "PFP_INVALIDATE_ICACHE"},
8211 {"bits": [8, 8], "name": "ME_INVALIDATE_ICACHE"},
8212 {"bits": [24, 24], "name": "CE_HALT"},
8213 {"bits": [25, 25], "name": "CE_STEP"},
8214 {"bits": [26, 26], "name": "PFP_HALT"},
8215 {"bits": [27, 27], "name": "PFP_STEP"},
8216 {"bits": [28, 28], "name": "ME_HALT"},
8217 {"bits": [29, 29], "name": "ME_STEP"}
8222 {"bits": [0, 7], "name": "ME_MC_RADDR_HI"}
8227 {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"},
8228 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
8233 {"bits": [0, 7], "name": "ME_MC_WADDR_HI"}
8238 {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"},
8239 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
8244 {"bits": [0, 0], "name": "ME_CNTXSW_PREEMPTION"}
8249 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
8250 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
8251 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
8252 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
8257 {"bits": [31, 31], "name": "PERFMON_ENABLE"}
8262 {"bits": [0, 0], "name": "IB_EN"}
8267 {"bits": [0, 0], "name": "CONFIG_REG_EN"},
8268 {"bits": [1, 1], "name": "CNTX_REG_EN"},
8269 {"bits": [15, 15], "name": "UCONFIG_REG_EN"},
8270 {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
8271 {"bits": [24, 24], "name": "SH_CS_REG_EN"}
8276 {"bits": [0, 1], "name": "PIPE_STATS_ADDR_SWAP"},
8277 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
8282 {"bits": [0, 5], "name": "ROQ_IB1_START"},
8283 {"bits": [8, 13], "name": "ROQ_IB2_START"}
8288 {"bits": [0, 19], "name": "RB_RPTR"}
8293 {"bits": [0, 19], "name": "RB_OFFSET"}
8298 {"bits": [0, 27], "name": "PRE_WRITE_TIMER"},
8299 {"bits": [28, 31], "name": "PRE_WRITE_LIMIT"}
8304 {"bits": [0, 15], "name": "POLL_FREQUENCY"},
8305 {"bits": [16, 31], "name": "IDLE_POLL_COUNT"}
8310 {"bits": [0, 1], "name": "RINGID"}
8315 {"bits": [0, 7], "name": "RB1_START"},
8316 {"bits": [8, 15], "name": "RB2_START"},
8317 {"bits": [16, 23], "name": "R0_IB1_START"},
8318 {"bits": [24, 31], "name": "R1_IB1_START"}
8323 {"bits": [0, 10], "name": "ROQ_CNT_IB2"}
8328 {"bits": [0, 7], "name": "R2_IB1_START"},
8329 {"bits": [8, 15], "name": "R0_IB2_START"},
8330 {"bits": [16, 23], "name": "R1_IB2_START"},
8331 {"bits": [24, 31], "name": "R2_IB2_START"}
8336 {"bits": [0, 10], "name": "ROQ_CNT_RING"},
8337 {"bits": [16, 26], "name": "ROQ_CNT_IB1"}
8342 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT1"},
8343 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT1"}
8348 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT2"},
8349 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT2"}
8354 {"bits": [0, 9], "name": "ROQ_RPTR_PRIMARY"},
8355 {"bits": [16, 25], "name": "ROQ_WPTR_PRIMARY"}
8360 {"bits": [0, 7], "name": "SCRATCH_INDEX"}
8365 {"bits": [0, 7], "name": "SEM_ADDR_HI"},
8366 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
8367 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
8368 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
8369 {"bits": [29, 31], "name": "SEM_SELECT"}
8374 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},
8375 {"bits": [3, 31], "name": "SEM_ADDR_LO"}
8380 {"bits": [0, 0], "name": "RBIU_TO_DMA_NOT_RDY_TO_RCV"},
8381 {"bits": [2, 2], "name": "RBIU_TO_SEM_NOT_RDY_TO_RCV"},
8382 {"bits": [4, 4], "name": "RBIU_TO_MEMWR_NOT_RDY_TO_RCV"},
8383 {"bits": [10, 10], "name": "ME_HAS_ACTIVE_CE_BUFFER_FLAG"},
8384 {"bits": [11, 11], "name": "ME_HAS_ACTIVE_DE_BUFFER_FLAG"},
8385 {"bits": [12, 12], "name": "ME_STALLED_ON_TC_WR_CONFIRM"},
8386 {"bits": [13, 13], "name": "ME_STALLED_ON_ATOMIC_RTN_DATA"},
8387 {"bits": [14, 14], "name": "ME_WAITING_ON_MC_READ_DATA"},
8388 {"bits": [15, 15], "name": "ME_WAITING_ON_REG_READ_DATA"},
8389 {"bits": [16, 16], "name": "MIU_WAITING_ON_RDREQ_FREE"},
8390 {"bits": [17, 17], "name": "MIU_WAITING_ON_WRREQ_FREE"},
8391 {"bits": [23, 23], "name": "RCIU_WAITING_ON_GDS_FREE"},
8392 {"bits": [24, 24], "name": "RCIU_WAITING_ON_GRBM_FREE"},
8393 {"bits": [25, 25], "name": "RCIU_WAITING_ON_VGT_FREE"},
8394 {"bits": [26, 26], "name": "RCIU_STALLED_ON_ME_READ"},
8395 {"bits": [27, 27], "name": "RCIU_STALLED_ON_DMA_READ"},
8396 {"bits": [28, 28], "name": "RCIU_HALTED_BY_REG_VIOLATION"},
8397 {"bits": [28, 28], "name": "RCIU_STALLED_ON_APPEND_READ"}
8402 {"bits": [0, 0], "name": "PFP_TO_CSF_NOT_RDY_TO_RCV"},
8403 {"bits": [1, 1], "name": "PFP_TO_MEQ_NOT_RDY_TO_RCV"},
8404 {"bits": [2, 2], "name": "PFP_TO_RCIU_NOT_RDY_TO_RCV"},
8405 {"bits": [4, 4], "name": "PFP_TO_VGT_WRITES_PENDING"},
8406 {"bits": [5, 5], "name": "PFP_RCIU_READ_PENDING"},
8407 {"bits": [6, 6], "name": "PFP_MIU_READ_PENDING"},
8408 {"bits": [7, 7], "name": "PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV"},
8409 {"bits": [8, 8], "name": "PFP_WAITING_ON_BUFFER_DATA"},
8410 {"bits": [9, 9], "name": "ME_WAIT_ON_CE_COUNTER"},
8411 {"bits": [10, 10], "name": "ME_WAIT_ON_AVAIL_BUFFER"},
8412 {"bits": [11, 11], "name": "GFX_CNTX_NOT_AVAIL_TO_ME"},
8413 {"bits": [12, 12], "name": "ME_RCIU_NOT_RDY_TO_RCV"},
8414 {"bits": [13, 13], "name": "ME_TO_CONST_NOT_RDY_TO_RCV"},
8415 {"bits": [14, 14], "name": "ME_WAITING_DATA_FROM_PFP"},
8416 {"bits": [15, 15], "name": "ME_WAITING_ON_PARTIAL_FLUSH"},
8417 {"bits": [16, 16], "name": "MEQ_TO_ME_NOT_RDY_TO_RCV"},
8418 {"bits": [17, 17], "name": "STQ_TO_ME_NOT_RDY_TO_RCV"},
8419 {"bits": [18, 18], "name": "ME_WAITING_DATA_FROM_STQ"},
8420 {"bits": [19, 19], "name": "PFP_STALLED_ON_TC_WR_CONFIRM"},
8421 {"bits": [20, 20], "name": "PFP_STALLED_ON_ATOMIC_RTN_DATA"},
8422 {"bits": [21, 21], "name": "EOPD_FIFO_NEEDS_SC_EOP_DONE"},
8423 {"bits": [22, 22], "name": "EOPD_FIFO_NEEDS_WR_CONFIRM"},
8424 {"bits": [23, 23], "name": "STRMO_WR_OF_PRIM_DATA_PENDING"},
8425 {"bits": [24, 24], "name": "PIPE_STATS_WR_DATA_PENDING"},
8426 {"bits": [25, 25], "name": "APPEND_RDY_WAIT_ON_CS_DONE"},
8427 {"bits": [26, 26], "name": "APPEND_RDY_WAIT_ON_PS_DONE"},
8428 {"bits": [27, 27], "name": "APPEND_WAIT_ON_WR_CONFIRM"},
8429 {"bits": [28, 28], "name": "APPEND_ACTIVE_PARTITION"},
8430 {"bits": [29, 29], "name": "APPEND_WAITING_TO_SEND_MEMWRITE"},
8431 {"bits": [30, 30], "name": "SURF_SYNC_NEEDS_IDLE_CNTXS"},
8432 {"bits": [31, 31], "name": "SURF_SYNC_NEEDS_ALL_CLEAN"}
8437 {"bits": [0, 0], "name": "CE_TO_CSF_NOT_RDY_TO_RCV"},
8438 {"bits": [1, 1], "name": "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV"},
8439 {"bits": [2, 2], "name": "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER"},
8440 {"bits": [3, 3], "name": "CE_TO_RAM_INIT_NOT_RDY"},
8441 {"bits": [4, 4], "name": "CE_TO_RAM_DUMP_NOT_RDY"},
8442 {"bits": [5, 5], "name": "CE_TO_RAM_WRITE_NOT_RDY"},
8443 {"bits": [6, 6], "name": "CE_TO_INC_FIFO_NOT_RDY_TO_RCV"},
8444 {"bits": [7, 7], "name": "CE_TO_WR_FIFO_NOT_RDY_TO_RCV"},
8445 {"bits": [8, 8], "name": "CE_TO_MIU_WRITE_NOT_RDY_TO_RCV"},
8446 {"bits": [10, 10], "name": "CE_WAITING_ON_BUFFER_DATA"},
8447 {"bits": [11, 11], "name": "CE_WAITING_ON_CE_BUFFER_FLAG"},
8448 {"bits": [12, 12], "name": "CE_WAITING_ON_DE_COUNTER"},
8449 {"bits": [13, 13], "name": "CE_WAITING_ON_DE_COUNTER_UNDERFLOW"},
8450 {"bits": [14, 14], "name": "TCIU_WAITING_ON_FREE"},
8451 {"bits": [15, 15], "name": "TCIU_WAITING_ON_TAGS"}
8456 {"bits": [7, 7], "name": "MIU_RDREQ_BUSY"},
8457 {"bits": [8, 8], "name": "MIU_WRREQ_BUSY"},
8458 {"bits": [9, 9], "name": "ROQ_RING_BUSY"},
8459 {"bits": [10, 10], "name": "ROQ_INDIRECT1_BUSY"},
8460 {"bits": [11, 11], "name": "ROQ_INDIRECT2_BUSY"},
8461 {"bits": [12, 12], "name": "ROQ_STATE_BUSY"},
8462 {"bits": [13, 13], "name": "DC_BUSY"},
8463 {"bits": [15, 15], "name": "PFP_BUSY"},
8464 {"bits": [16, 16], "name": "MEQ_BUSY"},
8465 {"bits": [17, 17], "name": "ME_BUSY"},
8466 {"bits": [18, 18], "name": "QUERY_BUSY"},
8467 {"bits": [19, 19], "name": "SEMAPHORE_BUSY"},
8468 {"bits": [20, 20], "name": "INTERRUPT_BUSY"},
8469 {"bits": [21, 21], "name": "SURFACE_SYNC_BUSY"},
8470 {"bits": [22, 22], "name": "DMA_BUSY"},
8471 {"bits": [23, 23], "name": "RCIU_BUSY"},
8472 {"bits": [24, 24], "name": "SCRATCH_RAM_BUSY"},
8473 {"bits": [25, 25], "name": "CPC_CPG_BUSY"},
8474 {"bits": [26, 26], "name": "CE_BUSY"},
8475 {"bits": [27, 27], "name": "TCIU_BUSY"},
8476 {"bits": [28, 28], "name": "ROQ_CE_RING_BUSY"},
8477 {"bits": [29, 29], "name": "ROQ_CE_INDIRECT1_BUSY"},
8478 {"bits": [30, 30], "name": "ROQ_CE_INDIRECT2_BUSY"},
8479 {"bits": [31, 31], "name": "CP_BUSY"}
8484 {"bits": [0, 8], "name": "STQ_CNT"}
8489 {"bits": [0, 9], "name": "STQ_RPTR"}
8494 {"bits": [0, 7], "name": "STQ0_START"},
8495 {"bits": [8, 15], "name": "STQ1_START"},
8496 {"bits": [16, 23], "name": "STQ2_START"}
8501 {"bits": [0, 1], "name": "STREAM_OUT_ADDR_SWAP"},
8502 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
8507 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
8512 {"bits": [0, 7], "name": "ST_BASE_HI"}
8517 {"bits": [2, 31], "name": "ST_BASE_LO"}
8522 {"bits": [0, 19], "name": "ST_BUFSZ"}
8527 {"bits": [0, 3], "name": "VMID"}
8532 {"bits": [0, 2], "name": "SRC_STATE_ID"}
8537 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
8538 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
8539 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
8540 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
8541 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
8542 {"bits": [16, 16], "name": "OFFSET_ROUND"}
8547 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
8548 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
8549 {"bits": [4, 6], "name": "SAMPLE_RATE"},
8550 {"bits": [8, 11], "name": "ZPASS_ENABLE"},
8551 {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
8552 {"bits": [16, 19], "name": "SFAIL_ENABLE"},
8553 {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
8554 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
8555 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
8560 {"bits": [0, 0], "name": "STENCIL_ENABLE"},
8561 {"bits": [1, 1], "name": "Z_ENABLE"},
8562 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
8563 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
8564 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
8565 {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
8566 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
8567 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
8568 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
8569 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
8574 {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"},
8575 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
8576 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
8577 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
8578 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
8579 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
8580 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
8585 {"bits": [0, 10], "name": "PITCH_TILE_MAX"},
8586 {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"}
8591 {"bits": [0, 21], "name": "SLICE_TILE_MAX"}
8596 {"bits": [0, 10], "name": "SLICE_START"},
8597 {"bits": [13, 23], "name": "SLICE_MAX"},
8598 {"bits": [24, 24], "name": "Z_READ_ONLY"},
8599 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}
8604 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
8605 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
8606 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
8607 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
8608 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
8609 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
8610 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
8611 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
8612 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
8613 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
8614 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
8615 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
8620 {"bits": [0, 0], "name": "LINEAR"},
8621 {"bits": [1, 1], "name": "FULL_CACHE"},
8622 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"},
8623 {"bits": [3, 3], "name": "PRELOAD"},
8624 {"bits": [4, 9], "name": "PREFETCH_WIDTH"},
8625 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"},
8626 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"}
8631 {"bits": [0, 7], "name": "START_X"},
8632 {"bits": [8, 15], "name": "START_Y"},
8633 {"bits": [16, 23], "name": "MAX_X"},
8634 {"bits": [24, 31], "name": "MAX_Y"}
8639 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
8640 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
8641 {"bits": [2, 2], "name": "DEPTH_COPY"},
8642 {"bits": [3, 3], "name": "STENCIL_COPY"},
8643 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
8644 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
8645 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
8646 {"bits": [7, 7], "name": "COPY_CENTROID"},
8647 {"bits": [8, 11], "name": "COPY_SAMPLE"}
8652 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
8653 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
8654 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
8655 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
8656 {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
8657 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
8658 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
8659 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
8660 {"bits": [11, 11], "name": "FORCE_Z_READ"},
8661 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
8662 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
8663 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
8664 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
8665 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
8666 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
8667 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
8668 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
8669 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
8670 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
8671 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
8672 {"bits": [29, 29], "name": "FORCE_Z_VALID"},
8673 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
8674 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
8679 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
8680 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
8681 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
8682 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
8683 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
8684 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
8685 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
8686 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
8687 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
8688 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
8689 {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
8690 {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
8691 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
8692 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
8693 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}
8698 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
8699 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
8700 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
8701 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
8702 {"bits": [6, 6], "name": "KILL_ENABLE"},
8703 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
8704 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
8705 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
8706 {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
8707 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
8708 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
8709 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}
8714 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
8715 {"bits": [4, 11], "name": "COMPAREVALUE0"},
8716 {"bits": [12, 19], "name": "COMPAREMASK0"},
8717 {"bits": [24, 24], "name": "ENABLE0"}
8722 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
8723 {"bits": [4, 11], "name": "COMPAREVALUE1"},
8724 {"bits": [12, 19], "name": "COMPAREMASK1"},
8725 {"bits": [24, 24], "name": "ENABLE1"}
8730 {"bits": [0, 7], "name": "STENCILTESTVAL"},
8731 {"bits": [8, 15], "name": "STENCILMASK"},
8732 {"bits": [16, 23], "name": "STENCILWRITEMASK"},
8733 {"bits": [24, 31], "name": "STENCILOPVAL"}
8738 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
8739 {"bits": [8, 15], "name": "STENCILMASK_BF"},
8740 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
8741 {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
8746 {"bits": [0, 7], "name": "CLEAR"}
8751 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
8752 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
8753 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
8754 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
8755 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
8756 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
8761 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
8762 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
8763 {"bits": [20, 22], "name": "TILE_MODE_INDEX"},
8764 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
8765 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
8770 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
8771 {"bits": [2, 3], "name": "NUM_SAMPLES"},
8772 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
8773 {"bits": [20, 22], "name": "TILE_MODE_INDEX"},
8774 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
8775 {"bits": [28, 28], "name": "READ_SIZE"},
8776 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
8777 {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
8782 {"bits": [0, 17], "name": "DEBUG_INDEX"}
8787 {"bits": [0, 2], "name": "NUM_PIPES"},
8788 {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"},
8789 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"},
8790 {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"},
8791 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"},
8792 {"bits": [20, 22], "name": "NUM_GPUS"},
8793 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"},
8794 {"bits": [28, 29], "name": "ROW_SIZE"},
8795 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"}
8800 {"bits": [0, 1], "enum_ref": "GB_TILE_MODE0__MICRO_TILE_MODE", "name": "MICRO_TILE_MODE"},
8801 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
8802 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
8803 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
8804 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
8805 {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
8810 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
8811 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
8812 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
8813 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
8814 {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
8819 {"bits": [0, 7], "name": "READ_TIMEOUT"}
8824 {"bits": [1, 1], "name": "IGNORE_RDY"},
8825 {"bits": [5, 5], "name": "IGNORE_FAO"},
8826 {"bits": [6, 6], "name": "DISABLE_READ_TIMEOUT"},
8827 {"bits": [7, 7], "name": "SNAPSHOT_FREE_CNTRS"},
8828 {"bits": [8, 11], "name": "HYSTERESIS_GUI_ACTIVE"},
8829 {"bits": [12, 12], "name": "GFX_CLOCK_DOMAIN_OVERRIDE"}
8834 {"bits": [0, 5], "name": "GRBM_DEBUG_INDEX"}
8839 {"bits": [0, 0], "name": "CPF_RDY"},
8840 {"bits": [1, 1], "name": "CPG_RDY"},
8841 {"bits": [1, 1], "name": "SRBM_RDY"},
8842 {"bits": [3, 3], "name": "WD_ME0PIPE0_RDY"},
8843 {"bits": [4, 4], "name": "WD_ME0PIPE1_RDY"},
8844 {"bits": [6, 6], "name": "SE0SPI_ME0PIPE0_RDY0"},
8845 {"bits": [7, 7], "name": "SE0SPI_ME0PIPE1_RDY0"},
8846 {"bits": [8, 8], "name": "SE1SPI_ME0PIPE0_RDY0"},
8847 {"bits": [9, 9], "name": "GDS_RDY"},
8848 {"bits": [9, 9], "name": "SE1SPI_ME0PIPE1_RDY0"},
8849 {"bits": [10, 10], "name": "SE2SPI_ME0PIPE0_RDY0"},
8850 {"bits": [11, 11], "name": "SE2SPI_ME0PIPE1_RDY0"},
8851 {"bits": [12, 12], "name": "SE3SPI_ME0PIPE0_RDY0"},
8852 {"bits": [13, 13], "name": "SE3SPI_ME0PIPE1_RDY0"},
8853 {"bits": [14, 14], "name": "SE0SPI_ME0PIPE0_RDY1"},
8854 {"bits": [15, 15], "name": "SE0SPI_ME0PIPE1_RDY1"},
8855 {"bits": [16, 16], "name": "SE1SPI_ME0PIPE0_RDY1"},
8856 {"bits": [17, 17], "name": "SE1SPI_ME0PIPE1_RDY1"},
8857 {"bits": [18, 18], "name": "SE2SPI_ME0PIPE0_RDY1"},
8858 {"bits": [19, 19], "name": "SE2SPI_ME0PIPE1_RDY1"},
8859 {"bits": [20, 20], "name": "SE3SPI_ME0PIPE0_RDY1"},
8860 {"bits": [21, 21], "name": "SE3SPI_ME0PIPE1_RDY1"}
8865 {"bits": [0, 3], "name": "PREFIX_DELAY_CNT"},
8866 {"bits": [8, 12], "name": "POST_DELAY_CNT"}
8871 {"bits": [0, 7], "name": "INSTANCE_INDEX"},
8872 {"bits": [8, 15], "name": "SH_INDEX"},
8873 {"bits": [16, 23], "name": "SE_INDEX"},
8874 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"},
8875 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
8876 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
8881 {"bits": [0, 0], "name": "RDERR_INT_ENABLE"},
8882 {"bits": [19, 19], "name": "GUI_IDLE_INT_ENABLE"}
8887 {"bits": [0, 5], "name": "PERF_SEL"},
8888 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
8889 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
8890 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"},
8891 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
8892 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
8893 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
8894 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
8895 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
8896 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
8897 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
8898 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
8899 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
8900 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"},
8901 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
8902 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
8903 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
8904 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"},
8905 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"}
8910 {"bits": [0, 3], "name": "REQ_TYPE"},
8911 {"bits": [4, 7], "name": "RSP_TYPE"}
8916 {"bits": [2, 17], "name": "READ_ADDRESS"},
8917 {"bits": [20, 21], "name": "READ_PIPEID"},
8918 {"bits": [22, 23], "name": "READ_MEID"},
8919 {"bits": [31, 31], "name": "READ_ERROR"}
8924 {"bits": [0, 5], "name": "PERF_SEL"},
8925 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
8926 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
8927 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
8928 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
8929 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
8930 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
8931 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
8932 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
8933 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"},
8934 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
8935 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}
8940 {"bits": [0, 5], "name": "SKEW_TOP_THRESHOLD"},
8941 {"bits": [6, 11], "name": "SKEW_COUNT"}
8946 {"bits": [0, 0], "name": "SOFT_RESET_CP"},
8947 {"bits": [2, 2], "name": "SOFT_RESET_RLC"},
8948 {"bits": [16, 16], "name": "SOFT_RESET_GFX"},
8949 {"bits": [17, 17], "name": "SOFT_RESET_CPF"},
8950 {"bits": [18, 18], "name": "SOFT_RESET_CPC"},
8951 {"bits": [19, 19], "name": "SOFT_RESET_CPG"}
8956 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
8957 {"bits": [5, 5], "name": "SRBM_RQ_PENDING"},
8958 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
8959 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
8960 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
8961 {"bits": [12, 12], "name": "DB_CLEAN"},
8962 {"bits": [13, 13], "name": "CB_CLEAN"},
8963 {"bits": [14, 14], "name": "TA_BUSY"},
8964 {"bits": [15, 15], "name": "GDS_BUSY"},
8965 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"},
8966 {"bits": [17, 17], "name": "VGT_BUSY"},
8967 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"},
8968 {"bits": [19, 19], "name": "IA_BUSY"},
8969 {"bits": [20, 20], "name": "SX_BUSY"},
8970 {"bits": [21, 21], "name": "WD_BUSY"},
8971 {"bits": [22, 22], "name": "SPI_BUSY"},
8972 {"bits": [23, 23], "name": "BCI_BUSY"},
8973 {"bits": [24, 24], "name": "SC_BUSY"},
8974 {"bits": [25, 25], "name": "PA_BUSY"},
8975 {"bits": [26, 26], "name": "DB_BUSY"},
8976 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
8977 {"bits": [29, 29], "name": "CP_BUSY"},
8978 {"bits": [30, 30], "name": "CB_BUSY"},
8979 {"bits": [31, 31], "name": "GUI_ACTIVE"}
8984 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
8985 {"bits": [0, 0], "name": "RLC_RQ_PENDING"},
8986 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
8987 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
8988 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
8989 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
8990 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
8991 {"bits": [8, 8], "name": "RLC_BUSY"},
8992 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
8993 {"bits": [9, 9], "name": "TC_BUSY"},
8994 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
8995 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
8996 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
8997 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
8998 {"bits": [28, 28], "name": "CPF_BUSY"},
8999 {"bits": [29, 29], "name": "CPC_BUSY"},
9000 {"bits": [30, 30], "name": "CPG_BUSY"}
9005 {"bits": [1, 1], "name": "DB_CLEAN"},
9006 {"bits": [2, 2], "name": "CB_CLEAN"},
9007 {"bits": [22, 22], "name": "BCI_BUSY"},
9008 {"bits": [23, 23], "name": "VGT_BUSY"},
9009 {"bits": [24, 24], "name": "PA_BUSY"},
9010 {"bits": [25, 25], "name": "TA_BUSY"},
9011 {"bits": [26, 26], "name": "SX_BUSY"},
9012 {"bits": [27, 27], "name": "SPI_BUSY"},
9013 {"bits": [29, 29], "name": "SC_BUSY"},
9014 {"bits": [30, 30], "name": "DB_BUSY"},
9015 {"bits": [31, 31], "name": "CB_BUSY"}
9020 {"bits": [0, 7], "name": "WAIT_IDLE_CLOCKS"}
9025 {"bits": [0, 0], "name": "IA_BUSY"},
9026 {"bits": [1, 1], "name": "IA_DMA_BUSY"},
9027 {"bits": [2, 2], "name": "IA_DMA_REQ_BUSY"},
9028 {"bits": [3, 3], "name": "IA_GRP_BUSY"},
9029 {"bits": [4, 4], "name": "IA_ADC_BUSY"}
9034 {"bits": [0, 5], "name": "IA_DEBUG_INDX"},
9035 {"bits": [6, 6], "name": "IA_DEBUG_SEL_BUS_B"}
9040 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
9041 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
9042 {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
9043 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
9044 {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
9045 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}
9050 {"bits": [0, 7], "name": "PERF_SEL"},
9051 {"bits": [10, 19], "name": "PERF_SEL1"},
9052 {"bits": [20, 23], "name": "CNTR_MODE"},
9053 {"bits": [24, 27], "name": "PERF_MODE1"},
9054 {"bits": [28, 31], "name": "PERF_MODE"}
9059 {"bits": [0, 7], "name": "PERF_SEL"},
9060 {"bits": [28, 31], "name": "PERF_MODE"}
9065 {"bits": [0, 0], "name": "ENABLE"},
9066 {"bits": [1, 4], "name": "VMID"}
9071 {"bits": [0, 0], "name": "UCP_ENA_0"},
9072 {"bits": [1, 1], "name": "UCP_ENA_1"},
9073 {"bits": [2, 2], "name": "UCP_ENA_2"},
9074 {"bits": [3, 3], "name": "UCP_ENA_3"},
9075 {"bits": [4, 4], "name": "UCP_ENA_4"},
9076 {"bits": [5, 5], "name": "UCP_ENA_5"},
9077 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
9078 {"bits": [14, 15], "name": "PS_UCP_MODE"},
9079 {"bits": [16, 16], "name": "CLIP_DISABLE"},
9080 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
9081 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
9082 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
9083 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
9084 {"bits": [21, 21], "name": "VTX_KILL_OR"},
9085 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
9086 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
9087 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
9088 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
9089 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}
9094 {"bits": [31, 31], "name": "CL_BUSY"}
9099 {"bits": [0, 0], "name": "CLIP_VTX_REORDER_ENA"},
9100 {"bits": [1, 2], "name": "NUM_CLIP_SEQ"},
9101 {"bits": [3, 3], "name": "CLIPPED_PRIM_SEQ_STALL"},
9102 {"bits": [4, 4], "name": "VE_NAN_PROC_DISABLE"},
9103 {"bits": [5, 5], "name": "XTRA_DEBUG_REG_SEL"},
9104 {"bits": [28, 28], "name": "ECO_SPARE3"},
9105 {"bits": [29, 29], "name": "ECO_SPARE2"},
9106 {"bits": [30, 30], "name": "ECO_SPARE1"},
9107 {"bits": [31, 31], "name": "ECO_SPARE0"}
9112 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
9113 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
9114 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
9115 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
9116 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
9117 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
9118 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
9119 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
9120 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
9121 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
9122 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
9123 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
9124 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
9125 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
9126 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
9127 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
9132 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
9133 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
9134 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
9135 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
9136 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
9137 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
9138 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
9139 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
9140 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
9141 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
9142 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
9143 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
9144 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
9145 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
9146 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
9147 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
9148 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
9149 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
9150 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
9151 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
9152 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
9153 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
9154 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
9155 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
9156 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
9157 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"}
9162 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
9163 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
9164 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
9165 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
9166 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
9167 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
9168 {"bits": [8, 8], "name": "VTX_XY_FMT"},
9169 {"bits": [9, 9], "name": "VTX_Z_FMT"},
9170 {"bits": [10, 10], "name": "VTX_W0_FMT"},
9171 {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
9176 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
9177 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
9178 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
9179 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
9180 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}
9185 {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
9186 {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
9191 {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
9192 {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
9197 {"bits": [0, 3], "name": "S0_X"},
9198 {"bits": [4, 7], "name": "S0_Y"},
9199 {"bits": [8, 11], "name": "S1_X"},
9200 {"bits": [12, 15], "name": "S1_Y"},
9201 {"bits": [16, 19], "name": "S2_X"},
9202 {"bits": [20, 23], "name": "S2_Y"},
9203 {"bits": [24, 27], "name": "S3_X"},
9204 {"bits": [28, 31], "name": "S3_Y"}
9209 {"bits": [0, 3], "name": "S4_X"},
9210 {"bits": [4, 7], "name": "S4_Y"},
9211 {"bits": [8, 11], "name": "S5_X"},
9212 {"bits": [12, 15], "name": "S5_Y"},
9213 {"bits": [16, 19], "name": "S6_X"},
9214 {"bits": [20, 23], "name": "S6_Y"},
9215 {"bits": [24, 27], "name": "S7_X"},
9216 {"bits": [28, 31], "name": "S7_Y"}
9221 {"bits": [0, 3], "name": "S8_X"},
9222 {"bits": [4, 7], "name": "S8_Y"},
9223 {"bits": [8, 11], "name": "S9_X"},
9224 {"bits": [12, 15], "name": "S9_Y"},
9225 {"bits": [16, 19], "name": "S10_X"},
9226 {"bits": [20, 23], "name": "S10_Y"},
9227 {"bits": [24, 27], "name": "S11_X"},
9228 {"bits": [28, 31], "name": "S11_Y"}
9233 {"bits": [0, 3], "name": "S12_X"},
9234 {"bits": [4, 7], "name": "S12_Y"},
9235 {"bits": [8, 11], "name": "S13_X"},
9236 {"bits": [12, 15], "name": "S13_Y"},
9237 {"bits": [16, 19], "name": "S14_X"},
9238 {"bits": [20, 23], "name": "S14_Y"},
9239 {"bits": [24, 27], "name": "S15_X"},
9240 {"bits": [28, 31], "name": "S15_Y"}
9245 {"bits": [0, 3], "name": "DISTANCE_0"},
9246 {"bits": [4, 7], "name": "DISTANCE_1"},
9247 {"bits": [8, 11], "name": "DISTANCE_2"},
9248 {"bits": [12, 15], "name": "DISTANCE_3"},
9249 {"bits": [16, 19], "name": "DISTANCE_4"},
9250 {"bits": [20, 23], "name": "DISTANCE_5"},
9251 {"bits": [24, 27], "name": "DISTANCE_6"},
9252 {"bits": [28, 31], "name": "DISTANCE_7"}
9257 {"bits": [0, 3], "name": "DISTANCE_8"},
9258 {"bits": [4, 7], "name": "DISTANCE_9"},
9259 {"bits": [8, 11], "name": "DISTANCE_10"},
9260 {"bits": [12, 15], "name": "DISTANCE_11"},
9261 {"bits": [16, 19], "name": "DISTANCE_12"},
9262 {"bits": [20, 23], "name": "DISTANCE_13"},
9263 {"bits": [24, 27], "name": "DISTANCE_14"},
9264 {"bits": [28, 31], "name": "DISTANCE_15"}
9269 {"bits": [0, 14], "name": "BR_X"},
9270 {"bits": [16, 30], "name": "BR_Y"}
9275 {"bits": [0, 14], "name": "TL_X"},
9276 {"bits": [16, 30], "name": "TL_Y"}
9281 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
9286 {"bits": [0, 5], "name": "SC_DEBUG_INDX"}
9291 {"bits": [0, 3], "name": "ER_TRI"},
9292 {"bits": [4, 7], "name": "ER_POINT"},
9293 {"bits": [8, 11], "name": "ER_RECT"},
9294 {"bits": [12, 17], "name": "ER_LINE_LR"},
9295 {"bits": [18, 23], "name": "ER_LINE_RL"},
9296 {"bits": [24, 27], "name": "ER_LINE_TB"},
9297 {"bits": [28, 31], "name": "ER_LINE_BT"}
9302 {"bits": [0, 0], "name": "ENABLE_PA_SC_OUT_OF_ORDER"},
9303 {"bits": [1, 1], "name": "DISABLE_SC_DB_TILE_FIX"},
9304 {"bits": [2, 2], "name": "DISABLE_AA_MASK_FULL_FIX"},
9305 {"bits": [3, 3], "name": "ENABLE_1XMSAA_SAMPLE_LOCATIONS"},
9306 {"bits": [4, 4], "name": "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID"},
9307 {"bits": [5, 5], "name": "DISABLE_SCISSOR_FIX"},
9308 {"bits": [6, 7], "name": "DISABLE_PW_BUBBLE_COLLAPSE"},
9309 {"bits": [8, 8], "name": "SEND_UNLIT_STILES_TO_PACKER"},
9310 {"bits": [9, 9], "name": "DISABLE_DUALGRAD_PERF_OPTIMIZATION"},
9311 {"bits": [10, 10], "name": "DISABLE_SC_PROCESS_RESET_PRIM"},
9312 {"bits": [11, 11], "name": "DISABLE_SC_PROCESS_RESET_SUPERTILE"},
9313 {"bits": [12, 12], "name": "DISABLE_SC_PROCESS_RESET_TILE"},
9314 {"bits": [13, 13], "name": "DISABLE_PA_SC_GUIDANCE"},
9315 {"bits": [14, 14], "name": "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS"},
9316 {"bits": [15, 15], "name": "ENABLE_MULTICYCLE_BUBBLE_FREEZE"},
9317 {"bits": [16, 16], "name": "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE"},
9318 {"bits": [17, 17], "name": "ENABLE_OUT_OF_ORDER_POLY_MODE"},
9319 {"bits": [18, 18], "name": "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST"},
9320 {"bits": [19, 19], "name": "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING"},
9321 {"bits": [20, 20], "name": "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY"},
9322 {"bits": [21, 21], "name": "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING"},
9323 {"bits": [22, 22], "name": "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING"},
9324 {"bits": [23, 23], "name": "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS"},
9325 {"bits": [24, 24], "name": "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID"},
9326 {"bits": [30, 30], "name": "ECO_SPARE1"},
9327 {"bits": [31, 31], "name": "ECO_SPARE0"}
9332 {"bits": [0, 7], "name": "DEPTH"}
9337 {"bits": [0, 5], "name": "SC_FRONTEND_PRIM_FIFO_SIZE"},
9338 {"bits": [6, 14], "name": "SC_BACKEND_PRIM_FIFO_SIZE"},
9339 {"bits": [15, 20], "name": "SC_HIZ_TILE_FIFO_SIZE"},
9340 {"bits": [23, 31], "name": "SC_EARLYZ_TILE_FIFO_SIZE"}
9345 {"bits": [0, 15], "name": "FORCE_EOV_MAX_CLK_CNT"},
9346 {"bits": [16, 31], "name": "FORCE_EOV_MAX_REZ_CNT"}
9351 {"bits": [0, 14], "name": "TL_X"},
9352 {"bits": [16, 30], "name": "TL_Y"},
9353 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
9358 {"bits": [0, 5], "name": "SC_DB_TILE_IF_FIFO_SIZE"},
9359 {"bits": [6, 11], "name": "SC_DB_QUAD_IF_FIFO_SIZE"},
9360 {"bits": [12, 17], "name": "SC_SPI_IF_FIFO_SIZE"},
9361 {"bits": [18, 23], "name": "SC_BCI_IF_FIFO_SIZE"}
9366 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
9367 {"bits": [10, 10], "name": "LAST_PIXEL"},
9368 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
9369 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}
9374 {"bits": [0, 15], "name": "LINE_PATTERN"},
9375 {"bits": [16, 23], "name": "REPEAT_COUNT"},
9376 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
9377 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
9382 {"bits": [0, 3], "name": "CURRENT_PTR"},
9383 {"bits": [8, 15], "name": "CURRENT_COUNT"}
9388 {"bits": [0, 0], "name": "MSAA_ENABLE"},
9389 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
9390 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
9391 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}
9396 {"bits": [0, 0], "name": "WALK_SIZE"},
9397 {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
9398 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
9399 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
9400 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
9401 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
9402 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
9403 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
9404 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
9405 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
9406 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
9407 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
9408 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
9409 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
9410 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
9411 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
9412 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
9413 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
9414 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
9415 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
9416 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
9417 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
9418 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
9419 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
9424 {"bits": [0, 8], "name": "PERF_SEL"},
9425 {"bits": [10, 19], "name": "PERF_SEL1"},
9426 {"bits": [20, 23], "name": "CNTR_MODE"}
9431 {"bits": [0, 8], "name": "PERF_SEL"}
9436 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
9437 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
9438 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
9439 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
9440 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
9441 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
9442 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
9443 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
9444 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
9445 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
9446 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
9447 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
9448 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
9449 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
9450 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
9455 {"bits": [0, 15], "name": "BR_X"},
9456 {"bits": [16, 31], "name": "BR_Y"}
9461 {"bits": [0, 15], "name": "TL_X"},
9462 {"bits": [16, 31], "name": "TL_Y"}
9467 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
9468 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
9473 {"bits": [31, 31], "name": "SU_BUSY"}
9478 {"bits": [0, 4], "name": "SU_DEBUG_INDX"}
9483 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
9484 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
9489 {"bits": [0, 15], "name": "WIDTH"}
9494 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
9495 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
9496 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
9497 {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
9502 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
9507 {"bits": [0, 15], "name": "PERFCOUNTER_HI"}
9512 {"bits": [0, 7], "name": "PERF_SEL"},
9513 {"bits": [10, 19], "name": "PERF_SEL1"},
9514 {"bits": [20, 23], "name": "CNTR_MODE"}
9519 {"bits": [0, 7], "name": "PERF_SEL"},
9520 {"bits": [20, 23], "name": "CNTR_MODE"}
9525 {"bits": [0, 15], "name": "MIN_SIZE"},
9526 {"bits": [16, 31], "name": "MAX_SIZE"}
9531 {"bits": [0, 15], "name": "HEIGHT"},
9532 {"bits": [16, 31], "name": "WIDTH"}
9537 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
9538 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
9543 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
9544 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
9545 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
9546 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
9547 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
9548 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
9549 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
9550 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
9551 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
9552 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
9553 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
9558 {"bits": [0, 0], "name": "CULL_FRONT"},
9559 {"bits": [1, 1], "name": "CULL_BACK"},
9560 {"bits": [2, 2], "name": "FACE"},
9561 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
9562 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
9563 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
9564 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
9565 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
9566 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
9567 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
9568 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
9569 {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
9570 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}
9575 {"bits": [0, 0], "name": "PIX_CENTER"},
9576 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
9577 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
9582 {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
9583 {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
9588 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
9589 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
9590 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
9591 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
9592 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
9593 {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
9594 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
9599 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
9600 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
9601 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
9602 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
9603 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},
9604 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}
9609 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
9610 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
9611 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
9612 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
9613 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
9614 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
9615 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
9620 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
9621 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
9622 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
9623 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
9624 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
9625 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
9626 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
9627 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
9628 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
9629 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
9630 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
9631 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
9632 {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
9633 {"bits": [13, 13], "name": "ANCILLARY_ENA"},
9634 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
9635 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
9640 {"bits": [0, 5], "name": "OFFSET"},
9641 {"bits": [8, 9], "name": "DEFAULT_VAL"},
9642 {"bits": [10, 10], "name": "FLAT_SHADE"},
9643 {"bits": [13, 16], "name": "CYL_WRAP"},
9644 {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
9645 {"bits": [18, 18], "name": "DUP"}
9650 {"bits": [0, 5], "name": "OFFSET"},
9651 {"bits": [8, 9], "name": "DEFAULT_VAL"},
9652 {"bits": [10, 10], "name": "FLAT_SHADE"},
9653 {"bits": [18, 18], "name": "DUP"}
9658 {"bits": [0, 5], "name": "NUM_INTERP"},
9659 {"bits": [6, 6], "name": "PARAM_GEN"},
9660 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"}
9665 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
9666 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
9667 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
9668 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
9669 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
9670 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
9671 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
9672 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
9677 {"bits": [0, 7], "name": "MEM_BASE"}
9682 {"bits": [0, 5], "name": "VGPRS"},
9683 {"bits": [6, 9], "name": "SGPRS"},
9684 {"bits": [10, 11], "name": "PRIORITY"},
9685 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
9686 {"bits": [20, 20], "name": "PRIV"},
9687 {"bits": [21, 21], "name": "DX10_CLAMP"},
9688 {"bits": [22, 22], "name": "DEBUG_MODE"},
9689 {"bits": [23, 23], "name": "IEEE_MODE"},
9690 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
9691 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
9692 {"bits": [27, 29], "name": "CACHE_CTL"},
9693 {"bits": [30, 30], "name": "CDBG_USER"}
9698 {"bits": [0, 5], "name": "VGPRS"},
9699 {"bits": [6, 9], "name": "SGPRS"},
9700 {"bits": [10, 11], "name": "PRIORITY"},
9701 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
9702 {"bits": [20, 20], "name": "PRIV"},
9703 {"bits": [21, 21], "name": "DX10_CLAMP"},
9704 {"bits": [22, 22], "name": "DEBUG_MODE"},
9705 {"bits": [23, 23], "name": "IEEE_MODE"},
9706 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
9707 {"bits": [25, 27], "name": "CACHE_CTL"},
9708 {"bits": [28, 28], "name": "CDBG_USER"}
9713 {"bits": [0, 5], "name": "VGPRS"},
9714 {"bits": [6, 9], "name": "SGPRS"},
9715 {"bits": [10, 11], "name": "PRIORITY"},
9716 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
9717 {"bits": [20, 20], "name": "PRIV"},
9718 {"bits": [21, 21], "name": "DX10_CLAMP"},
9719 {"bits": [22, 22], "name": "DEBUG_MODE"},
9720 {"bits": [23, 23], "name": "IEEE_MODE"},
9721 {"bits": [24, 26], "name": "CACHE_CTL"},
9722 {"bits": [27, 27], "name": "CDBG_USER"}
9727 {"bits": [0, 5], "name": "VGPRS"},
9728 {"bits": [6, 9], "name": "SGPRS"},
9729 {"bits": [10, 11], "name": "PRIORITY"},
9730 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
9731 {"bits": [20, 20], "name": "PRIV"},
9732 {"bits": [21, 21], "name": "DX10_CLAMP"},
9733 {"bits": [22, 22], "name": "DEBUG_MODE"},
9734 {"bits": [23, 23], "name": "IEEE_MODE"},
9735 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
9736 {"bits": [26, 28], "name": "CACHE_CTL"},
9737 {"bits": [29, 29], "name": "CDBG_USER"}
9742 {"bits": [0, 5], "name": "VGPRS"},
9743 {"bits": [6, 9], "name": "SGPRS"},
9744 {"bits": [10, 11], "name": "PRIORITY"},
9745 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
9746 {"bits": [20, 20], "name": "PRIV"},
9747 {"bits": [21, 21], "name": "DX10_CLAMP"},
9748 {"bits": [22, 22], "name": "DEBUG_MODE"},
9749 {"bits": [23, 23], "name": "IEEE_MODE"},
9750 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
9751 {"bits": [25, 27], "name": "CACHE_CTL"},
9752 {"bits": [28, 28], "name": "CDBG_USER"}
9757 {"bits": [0, 0], "name": "SCRATCH_EN"},
9758 {"bits": [1, 5], "name": "USER_SGPR"},
9759 {"bits": [6, 6], "name": "TRAP_PRESENT"},
9760 {"bits": [7, 7], "name": "OC_LDS_EN"},
9761 {"bits": [8, 14], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
9762 {"bits": [20, 28], "name": "LDS_SIZE"}
9767 {"bits": [0, 0], "name": "SCRATCH_EN"},
9768 {"bits": [1, 5], "name": "USER_SGPR"},
9769 {"bits": [6, 6], "name": "TRAP_PRESENT"},
9770 {"bits": [7, 13], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
9775 {"bits": [0, 0], "name": "SCRATCH_EN"},
9776 {"bits": [1, 5], "name": "USER_SGPR"},
9777 {"bits": [6, 6], "name": "TRAP_PRESENT"},
9778 {"bits": [7, 7], "name": "OC_LDS_EN"},
9779 {"bits": [8, 8], "name": "TG_SIZE_EN"},
9780 {"bits": [9, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
9785 {"bits": [0, 0], "name": "SCRATCH_EN"},
9786 {"bits": [1, 5], "name": "USER_SGPR"},
9787 {"bits": [6, 6], "name": "TRAP_PRESENT"},
9788 {"bits": [7, 15], "name": "LDS_SIZE"},
9789 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
9794 {"bits": [0, 0], "name": "SCRATCH_EN"},
9795 {"bits": [1, 5], "name": "USER_SGPR"},
9796 {"bits": [6, 6], "name": "TRAP_PRESENT"},
9797 {"bits": [7, 7], "name": "WAVE_CNT_EN"},
9798 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
9799 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
9804 {"bits": [0, 0], "name": "SCRATCH_EN"},
9805 {"bits": [1, 5], "name": "USER_SGPR"},
9806 {"bits": [6, 6], "name": "TRAP_PRESENT"},
9807 {"bits": [7, 7], "name": "OC_LDS_EN"},
9808 {"bits": [8, 8], "name": "SO_BASE0_EN"},
9809 {"bits": [9, 9], "name": "SO_BASE1_EN"},
9810 {"bits": [10, 10], "name": "SO_BASE2_EN"},
9811 {"bits": [11, 11], "name": "SO_BASE3_EN"},
9812 {"bits": [12, 12], "name": "SO_EN"},
9813 {"bits": [13, 19], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
9818 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
9819 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
9820 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
9821 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}
9826 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
9831 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
9832 {"bits": [6, 6], "name": "VS_HALF_PACK"}
9837 {"bits": [0, 0], "name": "INST_INVALIDATE"},
9838 {"bits": [1, 1], "name": "DATA_INVALIDATE"},
9839 {"bits": [2, 2], "name": "INVALIDATE_VOLATILE"}
9844 {"bits": [0, 1], "name": "INST_CACHE_SIZE"},
9845 {"bits": [2, 3], "name": "DATA_CACHE_SIZE"},
9846 {"bits": [4, 5], "name": "MISS_FIFO_DEPTH"},
9847 {"bits": [6, 6], "name": "HIT_FIFO_DEPTH"},
9848 {"bits": [7, 7], "name": "FORCE_ALWAYS_MISS"},
9849 {"bits": [8, 8], "name": "FORCE_IN_ORDER"},
9850 {"bits": [9, 9], "name": "IDENTITY_HASH_BANK"},
9851 {"bits": [10, 10], "name": "IDENTITY_HASH_SET"},
9852 {"bits": [11, 11], "name": "PER_VMID_INV_DISABLE"}
9857 {"bits": [0, 7], "name": "INST_SEC"},
9858 {"bits": [8, 15], "name": "INST_DED"},
9859 {"bits": [16, 23], "name": "DATA_SEC"},
9860 {"bits": [24, 31], "name": "DATA_DED"}
9865 {"bits": [0, 15], "name": "FORCE_CU_ON_SH0"},
9866 {"bits": [16, 31], "name": "FORCE_CU_ON_SH1"}
9871 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"},
9872 {"bits": [16, 29], "name": "STRIDE"},
9873 {"bits": [30, 30], "name": "CACHE_SWIZZLE"},
9874 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"}
9879 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
9880 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
9881 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
9882 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
9883 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"},
9884 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"},
9885 {"bits": [19, 20], "name": "ELEMENT_SIZE"},
9886 {"bits": [21, 22], "name": "INDEX_STRIDE"},
9887 {"bits": [23, 23], "name": "ADD_TID_ENABLE"},
9888 {"bits": [24, 24], "name": "ATC"},
9889 {"bits": [25, 25], "name": "HASH_ENABLE"},
9890 {"bits": [26, 26], "name": "HEAP"},
9891 {"bits": [27, 29], "name": "MTYPE"},
9892 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"}
9897 {"bits": [0, 7], "name": "UNUSED"},
9898 {"bits": [8, 8], "name": "DEBUG_EN"},
9899 {"bits": [9, 9], "name": "DISABLE_SCA_BYPASS"},
9900 {"bits": [10, 10], "name": "DISABLE_IB_DEP_CHECK"},
9901 {"bits": [11, 11], "name": "ENABLE_SOFT_CLAUSE"},
9902 {"bits": [12, 12], "name": "EARLY_TA_DONE_DISABLE"},
9903 {"bits": [13, 13], "name": "DUA_FLAT_LOCK_ENABLE"},
9904 {"bits": [14, 14], "name": "DUA_LDS_BYPASS_DISABLE"},
9905 {"bits": [15, 15], "name": "DUA_FLAT_LDS_PINGPONG_DISABLE"}
9910 {"bits": [0, 0], "name": "BUSY"},
9911 {"bits": [1, 1], "name": "INTERRUPT_MSG_BUSY"},
9912 {"bits": [4, 15], "name": "WAVE_LEVEL_SH0"},
9913 {"bits": [16, 27], "name": "WAVE_LEVEL_SH1"}
9918 {"bits": [0, 5], "name": "LDS_DED"},
9919 {"bits": [8, 12], "name": "SGPR_DED"},
9920 {"bits": [16, 24], "name": "VGPR_DED"}
9925 {"bits": [0, 3], "name": "WAVE_ID"},
9926 {"bits": [4, 5], "name": "SIMD_ID"},
9927 {"bits": [6, 8], "name": "SOURCE"},
9928 {"bits": [9, 12], "name": "VM_ID"}
9933 {"bits": [0, 3], "name": "INTERRUPT_FIFO_SIZE"},
9934 {"bits": [8, 11], "name": "TTRACE_FIFO_SIZE"},
9935 {"bits": [16, 17], "name": "EXPORT_BUF_SIZE"},
9936 {"bits": [18, 19], "name": "VMEM_DATA_FIFO_SIZE"}
9941 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"},
9942 {"bits": [8, 19], "name": "MIN_LOD"},
9943 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"},
9944 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"},
9945 {"bits": [30, 31], "name": "MTYPE"}
9950 {"bits": [0, 13], "name": "WIDTH"},
9951 {"bits": [14, 27], "name": "HEIGHT"},
9952 {"bits": [28, 30], "name": "PERF_MOD"},
9953 {"bits": [31, 31], "name": "INTERLACED"}
9958 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
9959 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
9960 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
9961 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
9962 {"bits": [12, 15], "name": "BASE_LEVEL"},
9963 {"bits": [16, 19], "name": "LAST_LEVEL"},
9964 {"bits": [20, 24], "name": "TILING_INDEX"},
9965 {"bits": [25, 25], "name": "POW2_PAD"},
9966 {"bits": [26, 26], "name": "MTYPE"},
9967 {"bits": [27, 27], "name": "ATC"},
9968 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"}
9973 {"bits": [0, 12], "name": "DEPTH"},
9974 {"bits": [13, 26], "name": "PITCH"}
9979 {"bits": [0, 12], "name": "BASE_ARRAY"},
9980 {"bits": [13, 25], "name": "LAST_ARRAY"}
9985 {"bits": [0, 11], "name": "MIN_LOD_WARN"},
9986 {"bits": [12, 19], "name": "COUNTER_BANK_ID"},
9987 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"},
9988 {"bits": [21, 31], "name": "UNUNSED"}
9993 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"},
9994 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"},
9995 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"},
9996 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"},
9997 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"},
9998 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"},
9999 {"bits": [16, 18], "name": "ANISO_THRESHOLD"},
10000 {"bits": [19, 19], "name": "MC_COORD_TRUNC"},
10001 {"bits": [20, 20], "name": "FORCE_DEGAMMA"},
10002 {"bits": [21, 26], "name": "ANISO_BIAS"},
10003 {"bits": [27, 27], "name": "TRUNC_COORD"},
10004 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"},
10005 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"}
10010 {"bits": [0, 11], "name": "MIN_LOD"},
10011 {"bits": [12, 23], "name": "MAX_LOD"},
10012 {"bits": [24, 27], "name": "PERF_MIP"},
10013 {"bits": [28, 31], "name": "PERF_Z"}
10018 {"bits": [0, 13], "name": "LOD_BIAS"},
10019 {"bits": [14, 19], "name": "LOD_BIAS_SEC"},
10020 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"},
10021 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"},
10022 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"},
10023 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"},
10024 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"},
10025 {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"},
10026 {"bits": [30, 30], "name": "FILTER_PREC_FIX"}
10031 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"},
10032 {"bits": [29, 29], "name": "UPGRADED_DEPTH"},
10033 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"}
10038 {"bits": [0, 3], "name": "WAVE_ID"},
10039 {"bits": [4, 5], "name": "SIMD_ID"},
10040 {"bits": [6, 11], "name": "THREAD_ID"},
10041 {"bits": [12, 12], "name": "AUTO_INCR"},
10042 {"bits": [13, 13], "name": "FORCE_READ"},
10043 {"bits": [14, 14], "name": "READ_TIMEOUT"},
10044 {"bits": [15, 15], "name": "UNINDEXED"},
10045 {"bits": [16, 31], "name": "INDEX"}
10050 {"bits": [0, 0], "name": "THREAD_TRACE"},
10051 {"bits": [1, 1], "name": "WLT"},
10052 {"bits": [2, 2], "name": "THREAD_TRACE_BUF_FULL"},
10053 {"bits": [3, 3], "name": "REG_TIMESTAMP"},
10054 {"bits": [4, 4], "name": "CMD_TIMESTAMP"},
10055 {"bits": [5, 5], "name": "HOST_CMD_OVERFLOW"},
10056 {"bits": [6, 6], "name": "HOST_REG_OVERFLOW"},
10057 {"bits": [7, 7], "name": "IMMED_OVERFLOW"},
10058 {"bits": [25, 25], "name": "SE_ID"},
10059 {"bits": [26, 27], "name": "ENCODING"}
10064 {"bits": [0, 0], "name": "START"},
10065 {"bits": [1, 1], "name": "LOAD"},
10066 {"bits": [2, 2], "name": "CLEAR"}
10071 {"bits": [0, 8], "name": "PERF_SEL"},
10072 {"bits": [12, 15], "name": "SQC_BANK_MASK"},
10073 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"},
10074 {"bits": [20, 23], "name": "SPM_MODE"},
10075 {"bits": [24, 27], "name": "SIMD_MASK"},
10076 {"bits": [28, 31], "name": "PERF_MODE"}
10081 {"bits": [0, 0], "name": "PS_EN"},
10082 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
10083 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
10084 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
10085 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
10086 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
10087 {"bits": [6, 6], "name": "CS_EN"},
10088 {"bits": [8, 12], "name": "CNTR_RATE"},
10089 {"bits": [13, 13], "name": "DISABLE_FLUSH"}
10094 {"bits": [0, 13], "name": "MIN_POWER"},
10095 {"bits": [16, 29], "name": "MAX_POWER"},
10096 {"bits": [30, 31], "name": "PHASE_OFFSET"}
10101 {"bits": [0, 13], "name": "MAX_POWER_DELTA"},
10102 {"bits": [16, 25], "name": "SHORT_TERM_INTERVAL_SIZE"},
10103 {"bits": [27, 30], "name": "LONG_TERM_INTERVAL_RATIO"},
10104 {"bits": [31, 31], "name": "USE_REF_CLOCK"}
10109 {"bits": [0, 6], "name": "RET"},
10110 {"bits": [7, 9], "name": "RUI"},
10111 {"bits": [10, 20], "name": "RNG"}
10116 {"bits": [0, 5], "name": "SRBM_CREDITS"},
10117 {"bits": [8, 11], "name": "CMD_CREDITS"},
10118 {"bits": [28, 28], "name": "REG_BUSY"},
10119 {"bits": [29, 29], "name": "SRBM_OVERFLOW"},
10120 {"bits": [30, 30], "name": "IMMED_OVERFLOW"},
10121 {"bits": [31, 31], "name": "CMD_OVERFLOW"}
10126 {"bits": [0, 5], "name": "LDS_SEC"},
10127 {"bits": [8, 12], "name": "SGPR_SEC"},
10128 {"bits": [16, 24], "name": "VGPR_SEC"}
10133 {"bits": [31, 31], "name": "RESET_BUFFER"}
10138 {"bits": [0, 2], "name": "HIWATER"}
10143 {"bits": [0, 4], "name": "CU_SEL"},
10144 {"bits": [5, 5], "name": "SH_SEL"},
10145 {"bits": [7, 7], "name": "REG_STALL_EN"},
10146 {"bits": [12, 13], "name": "VM_ID_MASK"},
10147 {"bits": [14, 14], "name": "SPI_STALL_EN"},
10148 {"bits": [15, 15], "name": "SQ_STALL_EN"},
10149 {"bits": [16, 31], "name": "RANDOM_SEED"},
10150 {"bits": [16, 31], "name": "RANDOM_SEED"}
10155 {"bits": [0, 2], "name": "MASK_PS"},
10156 {"bits": [3, 5], "name": "MASK_VS"},
10157 {"bits": [6, 8], "name": "MASK_GS"},
10158 {"bits": [9, 11], "name": "MASK_ES"},
10159 {"bits": [12, 14], "name": "MASK_HS"},
10160 {"bits": [15, 17], "name": "MASK_LS"},
10161 {"bits": [18, 20], "name": "MASK_CS"},
10162 {"bits": [21, 22], "name": "MODE"},
10163 {"bits": [23, 24], "name": "CAPTURE_MODE"},
10164 {"bits": [25, 25], "name": "AUTOFLUSH_EN"},
10165 {"bits": [26, 26], "name": "PRIV"},
10166 {"bits": [27, 28], "name": "ISSUE_MASK"},
10167 {"bits": [29, 29], "name": "TEST_MODE"},
10168 {"bits": [30, 30], "name": "INTERRUPT_EN"},
10169 {"bits": [31, 31], "name": "WRAP"}
10174 {"bits": [0, 15], "name": "SH0_MASK"},
10175 {"bits": [16, 31], "name": "SH1_MASK"}
10180 {"bits": [0, 21], "name": "SIZE"}
10185 {"bits": [0, 2], "name": "FINISH_PENDING"},
10186 {"bits": [16, 18], "name": "FINISH_DONE"},
10187 {"bits": [29, 29], "name": "NEW_BUF"},
10188 {"bits": [30, 30], "name": "BUSY"},
10189 {"bits": [31, 31], "name": "FULL"}
10194 {"bits": [0, 15], "name": "TOKEN_MASK"},
10195 {"bits": [16, 23], "name": "REG_MASK"},
10196 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"}
10201 {"bits": [0, 29], "name": "WPTR"},
10202 {"bits": [30, 31], "name": "READ_OFFSET"}
10207 {"bits": [0, 5], "name": "VGPR_BASE"},
10208 {"bits": [8, 13], "name": "VGPR_SIZE"},
10209 {"bits": [16, 21], "name": "SGPR_BASE"},
10210 {"bits": [24, 27], "name": "SGPR_SIZE"}
10215 {"bits": [0, 3], "name": "WAVE_ID"},
10216 {"bits": [4, 5], "name": "SIMD_ID"},
10217 {"bits": [6, 7], "name": "PIPE_ID"},
10218 {"bits": [8, 11], "name": "CU_ID"},
10219 {"bits": [12, 12], "name": "SH_ID"},
10220 {"bits": [13, 13], "name": "SE_ID"},
10221 {"bits": [16, 19], "name": "TG_ID"},
10222 {"bits": [20, 23], "name": "VM_ID"},
10223 {"bits": [24, 26], "name": "QUEUE_ID"},
10224 {"bits": [27, 29], "name": "STATE_ID"},
10225 {"bits": [30, 31], "name": "ME_ID"}
10230 {"bits": [0, 2], "name": "IBUF_ST"},
10231 {"bits": [3, 3], "name": "PC_INVALID"},
10232 {"bits": [4, 4], "name": "NEED_NEXT_DW"},
10233 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"},
10234 {"bits": [8, 9], "name": "IBUF_RPTR"},
10235 {"bits": [10, 11], "name": "IBUF_WPTR"},
10236 {"bits": [16, 18], "name": "INST_STR_ST"},
10237 {"bits": [19, 21], "name": "MISC_CNT"},
10238 {"bits": [22, 23], "name": "ECC_ST"},
10239 {"bits": [24, 24], "name": "IS_HYB"},
10240 {"bits": [25, 26], "name": "HYB_CNT"},
10241 {"bits": [27, 27], "name": "KILL"},
10242 {"bits": [28, 28], "name": "NEED_KILL_IFETCH"}
10247 {"bits": [0, 3], "name": "VM_CNT"},
10248 {"bits": [4, 6], "name": "EXP_CNT"},
10249 {"bits": [8, 12], "name": "LGKM_CNT"},
10250 {"bits": [13, 15], "name": "VALU_CNT"}
10255 {"bits": [0, 7], "name": "LDS_BASE"},
10256 {"bits": [12, 20], "name": "LDS_SIZE"}
10261 {"bits": [0, 3], "name": "FP_ROUND"},
10262 {"bits": [4, 7], "name": "FP_DENORM"},
10263 {"bits": [8, 8], "name": "DX10_CLAMP"},
10264 {"bits": [9, 9], "name": "IEEE"},
10265 {"bits": [10, 10], "name": "LOD_CLAMPED"},
10266 {"bits": [11, 11], "name": "DEBUG_EN"},
10267 {"bits": [12, 18], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
10268 {"bits": [28, 28], "name": "VSKIP"},
10269 {"bits": [29, 31], "name": "CSP"}
10274 {"bits": [0, 7], "name": "PC_HI"}
10279 {"bits": [0, 0], "name": "SCC"},
10280 {"bits": [1, 2], "name": "SPI_PRIO"},
10281 {"bits": [3, 4], "name": "WAVE_PRIO"},
10282 {"bits": [5, 5], "name": "PRIV"},
10283 {"bits": [6, 6], "name": "TRAP_EN"},
10284 {"bits": [7, 7], "name": "TTRACE_EN"},
10285 {"bits": [8, 8], "name": "EXPORT_RDY"},
10286 {"bits": [9, 9], "name": "EXECZ"},
10287 {"bits": [10, 10], "name": "VCCZ"},
10288 {"bits": [11, 11], "name": "IN_TG"},
10289 {"bits": [12, 12], "name": "IN_BARRIER"},
10290 {"bits": [13, 13], "name": "HALT"},
10291 {"bits": [14, 14], "name": "TRAP"},
10292 {"bits": [15, 15], "name": "TTRACE_CU_EN"},
10293 {"bits": [16, 16], "name": "VALID"},
10294 {"bits": [17, 17], "name": "ECC_ERR"},
10295 {"bits": [18, 18], "name": "SKIP_EXPORT"},
10296 {"bits": [19, 19], "name": "PERF_EN"},
10297 {"bits": [20, 20], "name": "COND_DBG_USER"},
10298 {"bits": [21, 21], "name": "COND_DBG_SYS"},
10299 {"bits": [22, 22], "name": "DATA_ATC"},
10300 {"bits": [23, 23], "name": "INST_ATC"},
10301 {"bits": [24, 26], "name": "DISPATCH_CACHE_CTRL"},
10302 {"bits": [27, 27], "name": "MUST_EXPORT"}
10307 {"bits": [0, 7], "name": "ADDR_HI"}
10312 {"bits": [0, 6], "enum_ref": "EXCP_EN", "name": "EXCP"},
10313 {"bits": [16, 21], "name": "EXCP_CYCLE"},
10314 {"bits": [29, 31], "name": "DP_RATE"}
10319 {"bits": [0, 1], "name": "CACHE_INVALIDATION"},
10320 {"bits": [5, 5], "name": "VS_NO_EXTRA_BUFFER"},
10321 {"bits": [6, 7], "name": "AUTO_INVLD_EN"},
10322 {"bits": [9, 9], "name": "USE_GS_DONE"},
10323 {"bits": [11, 11], "name": "DIS_RANGE_FULL_INVLD"},
10324 {"bits": [12, 12], "name": "GS_LATE_ALLOC_EN"},
10325 {"bits": [13, 13], "name": "STREAMOUT_FULL_FLUSH"},
10326 {"bits": [16, 20], "name": "ES_LIMIT"}
10331 {"bits": [0, 0], "name": "VGT_BUSY"},
10332 {"bits": [1, 1], "name": "VGT_OUT_INDX_BUSY"},
10333 {"bits": [2, 2], "name": "VGT_OUT_BUSY"},
10334 {"bits": [3, 3], "name": "VGT_PT_BUSY"},
10335 {"bits": [4, 4], "name": "VGT_TE_BUSY"},
10336 {"bits": [5, 5], "name": "VGT_VR_BUSY"},
10337 {"bits": [6, 6], "name": "VGT_PI_BUSY"},
10338 {"bits": [7, 7], "name": "VGT_GS_BUSY"},
10339 {"bits": [8, 8], "name": "VGT_HS_BUSY"},
10340 {"bits": [9, 9], "name": "VGT_TE11_BUSY"}
10345 {"bits": [0, 5], "name": "VGT_DEBUG_INDX"},
10346 {"bits": [6, 6], "name": "VGT_DEBUG_SEL_BUS_B"}
10351 {"bits": [0, 7], "name": "BASE_ADDR"}
10356 {"bits": [0, 8], "name": "DMA_DATA_FIFO_DEPTH"}
10361 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
10362 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
10363 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
10364 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
10365 {"bits": [8, 8], "name": "ATC"},
10366 {"bits": [9, 9], "name": "NOT_EOP"},
10367 {"bits": [10, 10], "name": "REQ_PATH"}
10372 {"bits": [0, 5], "name": "DMA_REQ_FIFO_DEPTH"}
10377 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
10378 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
10379 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
10380 {"bits": [5, 5], "name": "NOT_EOP"},
10381 {"bits": [6, 6], "name": "USE_OPAQUE"}
10386 {"bits": [0, 5], "name": "DRAW_INIT_FIFO_DEPTH"}
10391 {"bits": [0, 14], "name": "ITEMSIZE"}
10396 {"bits": [0, 10], "name": "ES_PER_GS"}
10401 {"bits": [0, 27], "name": "ADDRESS_LOW"}
10406 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
10407 {"bits": [18, 26], "name": "ADDRESS_HI"},
10408 {"bits": [27, 27], "name": "EXTENDED_EVENT"}
10413 {"bits": [0, 6], "name": "VS_DEALLOC_TBL_DEPTH"},
10414 {"bits": [7, 7], "name": "RESERVED_0"},
10415 {"bits": [8, 21], "name": "CLIPP_FIFO_DEPTH"},
10416 {"bits": [22, 31], "name": "RESERVED_1"}
10421 {"bits": [0, 3], "name": "DECR"}
10426 {"bits": [0, 3], "name": "FIRST_DECR"}
10431 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
10432 {"bits": [14, 14], "name": "RETAIN_ORDER"},
10433 {"bits": [15, 15], "name": "RETAIN_QUADS"},
10434 {"bits": [16, 18], "name": "PRIM_ORDER"}
10439 {"bits": [0, 0], "name": "COMP_X_EN"},
10440 {"bits": [1, 1], "name": "COMP_Y_EN"},
10441 {"bits": [2, 2], "name": "COMP_Z_EN"},
10442 {"bits": [3, 3], "name": "COMP_W_EN"},
10443 {"bits": [8, 15], "name": "STRIDE"},
10444 {"bits": [16, 23], "name": "SHIFT"}
10449 {"bits": [0, 3], "name": "X_CONV"},
10450 {"bits": [4, 7], "name": "X_OFFSET"},
10451 {"bits": [8, 11], "name": "Y_CONV"},
10452 {"bits": [12, 15], "name": "Y_OFFSET"},
10453 {"bits": [16, 19], "name": "Z_CONV"},
10454 {"bits": [20, 23], "name": "Z_OFFSET"},
10455 {"bits": [24, 27], "name": "W_CONV"},
10456 {"bits": [28, 31], "name": "W_OFFSET"}
10461 {"bits": [0, 14], "name": "OFFSET"}
10466 {"bits": [0, 0], "name": "ENABLE"},
10467 {"bits": [2, 8], "name": "CNT"}
10472 {"bits": [0, 10], "name": "MAX_VERT_OUT"}
10477 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
10478 {"bits": [3, 3], "name": "RESERVED_0"},
10479 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
10480 {"bits": [6, 10], "name": "RESERVED_1"},
10481 {"bits": [11, 11], "name": "GS_C_PACK_EN"},
10482 {"bits": [12, 12], "name": "RESERVED_2"},
10483 {"bits": [13, 13], "name": "ES_PASSTHRU"},
10484 {"bits": [14, 14], "name": "COMPUTE_MODE"},
10485 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"},
10486 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"},
10487 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
10488 {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
10489 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
10490 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
10491 {"bits": [21, 22], "name": "ONCHIP"}
10496 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
10497 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
10498 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
10499 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
10500 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
10505 {"bits": [0, 10], "name": "GS_PER_ES"}
10510 {"bits": [0, 3], "name": "GS_PER_VS"}
10515 {"bits": [0, 4], "name": "VERT_REUSE"}
10520 {"bits": [0, 1], "name": "TESS_MODE"}
10525 {"bits": [0, 7], "name": "REUSE_DEPTH"}
10530 {"bits": [0, 6], "name": "OFFCHIP_BUFFERING"},
10531 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
10536 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
10541 {"bits": [0, 2], "name": "SRC_STATE_ID"},
10542 {"bits": [16, 18], "name": "DST_STATE_ID"}
10547 {"bits": [0, 7], "name": "NUM_PATCHES"},
10548 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
10549 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
10554 {"bits": [0, 1], "name": "MC_TIME_STAMP_RES"}
10559 {"bits": [0, 0], "name": "RESET_EN"}
10564 {"bits": [0, 2], "name": "PATH_SELECT"}
10569 {"bits": [0, 6], "name": "DEALLOC_DIST"}
10574 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"}
10579 {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
10580 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}
10585 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
10590 {"bits": [0, 0], "name": "REUSE_OFF"}
10595 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
10596 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
10597 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
10598 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
10599 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
10600 {"bits": [8, 8], "name": "DYNAMIC_HS"}
10605 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
10606 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
10607 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
10608 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
10613 {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
10614 {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
10615 {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
10616 {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
10617 {"bits": [4, 6], "name": "RAST_STREAM"},
10618 {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
10619 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
10624 {"bits": [0, 8], "name": "VERTEX_STRIDE"}
10629 {"bits": [0, 9], "name": "STRIDE"}
10634 {"bits": [0, 0], "name": "DUAL_CORE_EN"},
10635 {"bits": [1, 6], "name": "MAX_LS_HS_THDGRP"},
10636 {"bits": [7, 7], "name": "ADC_EVENT_FILTER_DISABLE"}
10641 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
10642 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
10643 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
10644 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
10645 {"bits": [9, 9], "name": "DEPRECATED"},
10646 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
10647 {"bits": [14, 14], "name": "DISABLE_DONUTS"},
10648 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}
10653 {"bits": [0, 15], "name": "SIZE"}
10658 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
10663 {"bits": [0, 0], "name": "VTX_CNT_EN"}
10668 {"bits": [0, 9], "name": "PRIM_COUNT"}