Lines Matching refs:bits
9394 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
9395 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
9396 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
9397 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
9398 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
9399 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
9400 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
9401 {"bits": [30, 30], "name": "ENABLE"},
9402 {"bits": [31, 31], "name": "DISABLE_ROP3"}
9407 {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
9408 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
9409 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
9410 {"bits": [12, 14], "name": "NUM_SAMPLES"},
9411 {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
9412 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}
9417 {"bits": [0, 13], "name": "TILE_MAX"}
9422 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
9423 {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
9424 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
9425 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
9426 {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
9427 {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
9428 {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
9429 {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
9430 {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"}
9435 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
9436 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
9437 {"bits": [7, 7], "name": "LINEAR_GENERAL"},
9438 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
9439 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
9440 {"bits": [13, 13], "name": "FAST_CLEAR"},
9441 {"bits": [14, 14], "name": "COMPRESSION"},
9442 {"bits": [15, 15], "name": "BLEND_CLAMP"},
9443 {"bits": [16, 16], "name": "BLEND_BYPASS"},
9444 {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
9445 {"bits": [18, 18], "name": "ROUND_MODE"},
9446 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
9447 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
9448 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
9449 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
9450 {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
9451 {"bits": [28, 28], "name": "DCC_ENABLE"},
9452 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"}
9457 {"bits": [0, 10], "name": "TILE_MAX"},
9458 {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
9463 {"bits": [0, 21], "name": "TILE_MAX"}
9468 {"bits": [0, 10], "name": "SLICE_START"},
9469 {"bits": [13, 23], "name": "SLICE_MAX"}
9474 {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
9475 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
9476 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
9477 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
9482 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
9483 {"bits": [1, 1], "name": "OVERWRITE_COMBINER_MRT_SHARING_DISABLE"},
9484 {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"}
9489 {"bits": [0, 8], "name": "PERF_SEL"},
9490 {"bits": [10, 18], "name": "PERF_SEL1"},
9491 {"bits": [20, 23], "name": "CNTR_MODE"},
9492 {"bits": [24, 27], "name": "PERF_MODE1"},
9493 {"bits": [28, 31], "name": "PERF_MODE"}
9498 {"bits": [0, 8], "name": "PERF_SEL2"},
9499 {"bits": [10, 18], "name": "PERF_SEL3"},
9500 {"bits": [24, 27], "name": "PERF_MODE3"},
9501 {"bits": [28, 31], "name": "PERF_MODE2"}
9506 {"bits": [0, 8], "name": "PERF_SEL"},
9507 {"bits": [28, 31], "name": "PERF_MODE"}
9512 {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
9513 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
9514 {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
9515 {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
9516 {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
9517 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
9518 {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
9519 {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
9520 {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
9521 {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
9522 {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
9523 {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
9528 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
9529 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
9530 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
9531 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
9532 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
9533 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
9534 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
9535 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
9540 {"bits": [0, 3], "name": "TARGET0_ENABLE"},
9541 {"bits": [4, 7], "name": "TARGET1_ENABLE"},
9542 {"bits": [8, 11], "name": "TARGET2_ENABLE"},
9543 {"bits": [12, 15], "name": "TARGET3_ENABLE"},
9544 {"bits": [16, 19], "name": "TARGET4_ENABLE"},
9545 {"bits": [20, 23], "name": "TARGET5_ENABLE"},
9546 {"bits": [24, 27], "name": "TARGET6_ENABLE"},
9547 {"bits": [28, 31], "name": "TARGET7_ENABLE"}
9552 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
9553 {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
9554 {"bits": [2, 2], "name": "FORCE_START_AT_000"},
9555 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
9556 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
9557 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
9558 {"bits": [6, 6], "name": "ORDER_MODE"},
9559 {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"},
9560 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
9561 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
9562 {"bits": [12, 12], "name": "DATA_ATC"},
9563 {"bits": [14, 14], "name": "RESTORE"}
9568 {"bits": [0, 1], "name": "SEND_SEID"},
9569 {"bits": [2, 2], "name": "RESERVED2"},
9570 {"bits": [3, 3], "name": "RESERVED3"},
9571 {"bits": [4, 4], "name": "RESERVED4"},
9572 {"bits": [5, 16], "name": "WAVE_ID_BASE"}
9577 {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
9578 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
9583 {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
9588 {"bits": [0, 7], "name": "DATA"},
9589 {"bits": [8, 8], "name": "INST_ATC"}
9594 {"bits": [0, 5], "name": "VGPRS"},
9595 {"bits": [6, 9], "name": "SGPRS"},
9596 {"bits": [10, 11], "name": "PRIORITY"},
9597 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
9598 {"bits": [20, 20], "name": "PRIV"},
9599 {"bits": [21, 21], "name": "DX10_CLAMP"},
9600 {"bits": [22, 22], "name": "DEBUG_MODE"},
9601 {"bits": [23, 23], "name": "IEEE_MODE"},
9602 {"bits": [24, 24], "name": "BULKY"},
9603 {"bits": [25, 25], "name": "CDBG_USER"}
9608 {"bits": [0, 0], "name": "SCRATCH_EN"},
9609 {"bits": [1, 5], "name": "USER_SGPR"},
9610 {"bits": [6, 6], "name": "TRAP_PRESENT"},
9611 {"bits": [7, 7], "name": "TGID_X_EN"},
9612 {"bits": [8, 8], "name": "TGID_Y_EN"},
9613 {"bits": [9, 9], "name": "TGID_Z_EN"},
9614 {"bits": [10, 10], "name": "TG_SIZE_EN"},
9615 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
9616 {"bits": [13, 14], "name": "EXCP_EN_MSB"},
9617 {"bits": [15, 23], "name": "LDS_SIZE"},
9618 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
9623 {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
9628 {"bits": [0, 29], "name": "PAYLOAD"},
9629 {"bits": [30, 30], "name": "IS_EVENT"},
9630 {"bits": [31, 31], "name": "IS_STATE"}
9635 {"bits": [0, 9], "name": "WAVES_PER_SH"},
9636 {"bits": [12, 15], "name": "TG_PER_CU"},
9637 {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
9638 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
9639 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
9640 {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
9645 {"bits": [0, 15], "name": "SH0_CU_EN"},
9646 {"bits": [16, 31], "name": "SH1_CU_EN"}
9651 {"bits": [0, 7], "name": "DATA"}
9656 {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
9661 {"bits": [0, 11], "name": "WAVES"},
9662 {"bits": [12, 24], "name": "WAVESIZE"}
9667 {"bits": [0, 3], "name": "DATA"}
9672 {"bits": [0, 15], "name": "ADDR"}
9677 {"bits": [0, 0], "name": "ATC"},
9678 {"bits": [1, 2], "name": "MTYPE"}
9683 {"bits": [0, 5], "name": "PERF_SEL"},
9684 {"bits": [10, 15], "name": "PERF_SEL1"},
9685 {"bits": [20, 23], "name": "CNTR_MODE"}
9690 {"bits": [0, 5], "name": "PERF_SEL2"},
9691 {"bits": [10, 15], "name": "PERF_SEL3"}
9696 {"bits": [0, 5], "name": "PERF_SEL"}
9701 {"bits": [0, 15], "name": "MEM_ADDR_HI"},
9702 {"bits": [16, 16], "name": "CS_PS_SEL"},
9703 {"bits": [25, 25], "name": "CACHE_POLICY"},
9704 {"bits": [27, 28], "name": "MTYPE"},
9705 {"bits": [29, 31], "name": "COMMAND"}
9710 {"bits": [2, 31], "name": "MEM_ADDR_LO"}
9715 {"bits": [0, 15], "name": "IB1_BASE_HI"}
9720 {"bits": [2, 31], "name": "IB1_BASE_LO"}
9725 {"bits": [0, 19], "name": "IB1_BUFSZ"}
9730 {"bits": [0, 15], "name": "IB2_BASE_HI"}
9735 {"bits": [2, 31], "name": "IB2_BASE_LO"}
9740 {"bits": [0, 19], "name": "IB2_BUFSZ"}
9745 {"bits": [0, 15], "name": "INIT_BASE_HI"}
9750 {"bits": [5, 31], "name": "INIT_BASE_LO"}
9755 {"bits": [0, 11], "name": "INIT_BUFSZ"}
9760 {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
9765 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
9766 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
9767 {"bits": [2, 2], "name": "TC_SD_ACTION_ENA"},
9768 {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
9769 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
9770 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
9771 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
9772 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
9773 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
9774 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
9775 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
9776 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
9777 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
9778 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
9779 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
9780 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
9781 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"},
9782 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
9783 {"bits": [23, 23], "name": "TC_ACTION_ENA"},
9784 {"bits": [25, 25], "name": "CB_ACTION_ENA"},
9785 {"bits": [26, 26], "name": "DB_ACTION_ENA"},
9786 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
9787 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
9788 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
9789 {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"},
9790 {"bits": [31, 31], "name": "SH_SD_ACTION_ENA"}
9795 {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
9800 {"bits": [0, 5], "name": "START_DELAY_COUNT"}
9805 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
9806 {"bits": [24, 25], "name": "MEID"},
9807 {"bits": [30, 30], "name": "PHASE1_STATUS"},
9808 {"bits": [31, 31], "name": "STATUS"}
9813 {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
9814 {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
9815 {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
9816 {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
9817 {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
9818 {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
9819 {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
9820 {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
9821 {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
9822 {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
9823 {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
9824 {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
9825 {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
9826 {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
9827 {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
9828 {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
9829 {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
9830 {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
9831 {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
9832 {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
9833 {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
9834 {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
9835 {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
9836 {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
9837 {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
9838 {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
9839 {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
9840 {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
9845 {"bits": [0, 5], "name": "FREE_COUNT"}
9850 {"bits": [0, 3], "name": "COUNT"}
9855 {"bits": [0, 8], "name": "SCRATCH_INDEX"}
9860 {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
9861 {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
9862 {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
9863 {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
9864 {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
9865 {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
9866 {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
9867 {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
9868 {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
9869 {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
9870 {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
9871 {"bits": [22, 22], "name": "ATCL2IU_WAITING_ON_FREE"},
9872 {"bits": [23, 23], "name": "ATCL2IU_WAITING_ON_TAGS"},
9873 {"bits": [24, 24], "name": "ATCL1_WAITING_ON_TRANS"}
9878 {"bits": [0, 0], "name": "MEC1_BUSY"},
9879 {"bits": [1, 1], "name": "MEC2_BUSY"},
9880 {"bits": [2, 2], "name": "DC0_BUSY"},
9881 {"bits": [3, 3], "name": "DC1_BUSY"},
9882 {"bits": [4, 4], "name": "RCIU1_BUSY"},
9883 {"bits": [5, 5], "name": "RCIU2_BUSY"},
9884 {"bits": [6, 6], "name": "ROQ1_BUSY"},
9885 {"bits": [7, 7], "name": "ROQ2_BUSY"},
9886 {"bits": [10, 10], "name": "TCIU_BUSY"},
9887 {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
9888 {"bits": [12, 12], "name": "QU_BUSY"},
9889 {"bits": [13, 13], "name": "ATCL2IU_BUSY"},
9890 {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
9891 {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
9892 {"bits": [31, 31], "name": "CPC_BUSY"}
9897 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
9898 {"bits": [1, 1], "name": "CSF_RING_BUSY"},
9899 {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
9900 {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
9901 {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
9902 {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
9903 {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
9904 {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
9905 {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
9906 {"bits": [9, 9], "name": "OUTSTANDING_READ_TAGS"},
9907 {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
9908 {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
9909 {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
9910 {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
9911 {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
9912 {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
9913 {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
9914 {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
9915 {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
9916 {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
9917 {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
9918 {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
9919 {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
9920 {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
9921 {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
9922 {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
9923 {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
9924 {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
9925 {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
9926 {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
9927 {"bits": [31, 31], "name": "HQD_IB_BUSY"}
9932 {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
9933 {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
9934 {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
9935 {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
9936 {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
9937 {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
9938 {"bits": [7, 7], "name": "ATCL2IU_WAITING_ON_FREE"},
9939 {"bits": [8, 8], "name": "ATCL2IU_WAITING_ON_TAGS"},
9940 {"bits": [9, 9], "name": "ATCL1_WAITING_ON_TRANS"}
9945 {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
9946 {"bits": [1, 1], "name": "CSF_BUSY"},
9947 {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
9948 {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
9949 {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
9950 {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
9951 {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
9952 {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
9953 {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
9954 {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
9955 {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
9956 {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
9957 {"bits": [14, 14], "name": "TCIU_BUSY"},
9958 {"bits": [15, 15], "name": "HQD_BUSY"},
9959 {"bits": [16, 16], "name": "PRT_BUSY"},
9960 {"bits": [17, 17], "name": "ATCL2IU_BUSY"},
9961 {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
9962 {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
9963 {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
9964 {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
9965 {"bits": [31, 31], "name": "CPF_BUSY"}
9970 {"bits": [4, 5], "name": "MIN_AVAILSZ"},
9971 {"bits": [16, 19], "name": "BUFFER_DEPTH"},
9972 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
9973 {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
9974 {"bits": [30, 31], "name": "PIO_COUNT"}
9979 {"bits": [0, 20], "name": "BYTE_COUNT"},
9980 {"bits": [21, 21], "name": "DIS_WC"},
9981 {"bits": [22, 23], "name": "SRC_SWAP"},
9982 {"bits": [24, 25], "name": "DST_SWAP"},
9983 {"bits": [26, 26], "name": "SAS"},
9984 {"bits": [27, 27], "name": "DAS"},
9985 {"bits": [28, 28], "name": "SAIC"},
9986 {"bits": [29, 29], "name": "DAIC"},
9987 {"bits": [30, 30], "name": "RAW_WAIT"}
9992 {"bits": [10, 11], "name": "SRC_MTYPE"},
9993 {"bits": [12, 12], "name": "SRC_ATC"},
9994 {"bits": [13, 13], "name": "SRC_CACHE_POLICY"},
9995 {"bits": [20, 21], "name": "DST_SELECT"},
9996 {"bits": [22, 23], "name": "DST_MTYPE"},
9997 {"bits": [24, 24], "name": "DST_ATC"},
9998 {"bits": [25, 25], "name": "DST_CACHE_POLICY"},
9999 {"bits": [29, 30], "name": "SRC_SELECT"}
10004 {"bits": [0, 15], "name": "DST_ADDR_HI"}
10009 {"bits": [0, 15], "name": "SRC_ADDR_HI"}
10014 {"bits": [0, 25], "name": "DMA_READ_TAG"},
10015 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
10020 {"bits": [0, 15], "name": "COUNT"}
10025 {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
10026 {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
10027 {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
10028 {"bits": [8, 8], "name": "MODE"}
10033 {"bits": [0, 15], "name": "MIN"},
10034 {"bits": [16, 31], "name": "MAX"}
10039 {"bits": [0, 15], "name": "ADDR_HI"}
10044 {"bits": [2, 31], "name": "ADDR_LO"}
10049 {"bits": [0, 27], "name": "CNTX_ID"}
10054 {"bits": [0, 15], "name": "CNTX_ID"},
10055 {"bits": [16, 17], "name": "DST_SEL"},
10056 {"bits": [24, 26], "name": "INT_SEL"},
10057 {"bits": [29, 31], "name": "DATA_SEL"}
10062 {"bits": [0, 6], "name": "WBINV_TC_OP"},
10063 {"bits": [12, 17], "name": "WBINV_ACTION_ENA"},
10064 {"bits": [25, 25], "name": "CACHE_CONTROL"},
10065 {"bits": [27, 28], "name": "MTYPE"}
10070 {"bits": [0, 19], "name": "IB1_OFFSET"}
10075 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}
10080 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}
10085 {"bits": [0, 19], "name": "IB2_OFFSET"}
10090 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
10095 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
10100 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
10105 {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
10106 {"bits": [20, 21], "name": "MTYPE"},
10107 {"bits": [22, 22], "name": "CACHE_POLICY"}
10112 {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"},
10113 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
10118 {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
10119 {"bits": [20, 21], "name": "MTYPE"},
10120 {"bits": [22, 22], "name": "CACHE_POLICY"}
10125 {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"},
10126 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
10131 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
10132 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
10133 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
10134 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
10139 {"bits": [31, 31], "name": "PERFMON_ENABLE"}
10144 {"bits": [0, 1], "name": "STATUS"}
10149 {"bits": [0, 7], "name": "IB_EN"}
10154 {"bits": [0, 0], "name": "CONFIG_REG_EN"},
10155 {"bits": [1, 1], "name": "CNTX_REG_EN"},
10156 {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
10157 {"bits": [24, 24], "name": "SH_CS_REG_EN"}
10162 {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
10167 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
10172 {"bits": [25, 25], "name": "CACHE_CONTROL"},
10173 {"bits": [27, 28], "name": "MTYPE"}
10178 {"bits": [0, 0], "name": "NOT_VISIBLE"}
10183 {"bits": [0, 19], "name": "RB_OFFSET"}
10188 {"bits": [0, 1], "name": "RINGID"}
10193 {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
10194 {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
10195 {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
10196 {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
10197 {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
10198 {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
10199 {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
10200 {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
10205 {"bits": [0, 7], "name": "SCRATCH_INDEX"}
10210 {"bits": [0, 15], "name": "SEM_ADDR_HI"},
10211 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
10212 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
10213 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
10214 {"bits": [29, 31], "name": "SEM_SELECT"}
10219 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},
10220 {"bits": [3, 31], "name": "SEM_ADDR_LO"}
10225 {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
10230 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
10235 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
10240 {"bits": [0, 15], "name": "ST_BASE_HI"}
10245 {"bits": [2, 31], "name": "ST_BASE_LO"}
10250 {"bits": [0, 19], "name": "ST_BUFSZ"}
10255 {"bits": [0, 3], "name": "VMID"}
10260 {"bits": [0, 2], "name": "SRC_STATE_ID"}
10265 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
10266 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
10267 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
10268 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
10269 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
10270 {"bits": [16, 16], "name": "OFFSET_ROUND"}
10275 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
10276 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
10277 {"bits": [4, 6], "name": "SAMPLE_RATE"},
10278 {"bits": [8, 11], "name": "ZPASS_ENABLE"},
10279 {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
10280 {"bits": [16, 19], "name": "SFAIL_ENABLE"},
10281 {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
10282 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
10283 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
10288 {"bits": [0, 0], "name": "STENCIL_ENABLE"},
10289 {"bits": [1, 1], "name": "Z_ENABLE"},
10290 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
10291 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
10292 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
10293 {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
10294 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
10295 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
10296 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
10297 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
10302 {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"},
10303 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
10304 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
10305 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
10306 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
10307 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
10308 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
10313 {"bits": [0, 10], "name": "PITCH_TILE_MAX"},
10314 {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"}
10319 {"bits": [0, 21], "name": "SLICE_TILE_MAX"}
10324 {"bits": [0, 10], "name": "SLICE_START"},
10325 {"bits": [13, 23], "name": "SLICE_MAX"},
10326 {"bits": [24, 24], "name": "Z_READ_ONLY"},
10327 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}
10332 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
10333 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
10334 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
10335 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
10336 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
10337 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
10338 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
10339 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
10340 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
10341 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
10342 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
10343 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
10348 {"bits": [0, 0], "name": "LINEAR"},
10349 {"bits": [1, 1], "name": "FULL_CACHE"},
10350 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"},
10351 {"bits": [3, 3], "name": "PRELOAD"},
10352 {"bits": [4, 9], "name": "PREFETCH_WIDTH"},
10353 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"},
10354 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
10355 {"bits": [17, 17], "name": "TC_COMPATIBLE"}
10360 {"bits": [0, 9], "name": "PERF_SEL"},
10361 {"bits": [10, 19], "name": "PERF_SEL1"},
10362 {"bits": [20, 23], "name": "CNTR_MODE"},
10363 {"bits": [24, 27], "name": "PERF_MODE1"},
10364 {"bits": [28, 31], "name": "PERF_MODE"}
10369 {"bits": [0, 9], "name": "PERF_SEL2"},
10370 {"bits": [10, 19], "name": "PERF_SEL3"},
10371 {"bits": [24, 27], "name": "PERF_MODE3"},
10372 {"bits": [28, 31], "name": "PERF_MODE2"}
10377 {"bits": [0, 7], "name": "START_X"},
10378 {"bits": [8, 15], "name": "START_Y"},
10379 {"bits": [16, 23], "name": "MAX_X"},
10380 {"bits": [24, 31], "name": "MAX_Y"}
10385 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
10386 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
10387 {"bits": [2, 2], "name": "DEPTH_COPY"},
10388 {"bits": [3, 3], "name": "STENCIL_COPY"},
10389 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
10390 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
10391 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
10392 {"bits": [7, 7], "name": "COPY_CENTROID"},
10393 {"bits": [8, 11], "name": "COPY_SAMPLE"},
10394 {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"}
10399 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
10400 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
10401 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
10402 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
10403 {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
10404 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
10405 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
10406 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
10407 {"bits": [11, 11], "name": "FORCE_Z_READ"},
10408 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
10409 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
10410 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
10411 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
10412 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
10413 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
10414 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
10415 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
10416 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
10417 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
10418 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
10419 {"bits": [29, 29], "name": "FORCE_Z_VALID"},
10420 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
10421 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
10426 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
10427 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
10428 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
10429 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
10430 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
10431 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
10432 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
10433 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
10434 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
10435 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
10436 {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
10437 {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
10438 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
10439 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
10440 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}
10445 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
10446 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
10447 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
10448 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
10449 {"bits": [6, 6], "name": "KILL_ENABLE"},
10450 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
10451 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
10452 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
10453 {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
10454 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
10455 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
10456 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
10457 {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"}
10462 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
10463 {"bits": [4, 11], "name": "COMPAREVALUE0"},
10464 {"bits": [12, 19], "name": "COMPAREMASK0"},
10465 {"bits": [24, 24], "name": "ENABLE0"}
10470 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
10471 {"bits": [4, 11], "name": "COMPAREVALUE1"},
10472 {"bits": [12, 19], "name": "COMPAREMASK1"},
10473 {"bits": [24, 24], "name": "ENABLE1"}
10478 {"bits": [0, 7], "name": "STENCILTESTVAL"},
10479 {"bits": [8, 15], "name": "STENCILMASK"},
10480 {"bits": [16, 23], "name": "STENCILWRITEMASK"},
10481 {"bits": [24, 31], "name": "STENCILOPVAL"}
10486 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
10487 {"bits": [8, 15], "name": "STENCILMASK_BF"},
10488 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
10489 {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
10494 {"bits": [0, 7], "name": "CLEAR"}
10499 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
10500 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
10501 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
10502 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
10503 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
10504 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
10509 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
10510 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
10511 {"bits": [20, 22], "name": "TILE_MODE_INDEX"},
10512 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
10513 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"},
10514 {"bits": [30, 30], "name": "CLEAR_DISALLOWED"}
10519 {"bits": [0, 30], "name": "COUNT_HI"}
10524 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
10525 {"bits": [2, 3], "name": "NUM_SAMPLES"},
10526 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
10527 {"bits": [20, 22], "name": "TILE_MODE_INDEX"},
10528 {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
10529 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
10530 {"bits": [28, 28], "name": "READ_SIZE"},
10531 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
10532 {"bits": [30, 30], "name": "CLEAR_DISALLOWED"},
10533 {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
10538 {"bits": [0, 2], "name": "NUM_PIPES"},
10539 {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"},
10540 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"},
10541 {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"},
10542 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"},
10543 {"bits": [20, 22], "name": "NUM_GPUS"},
10544 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"},
10545 {"bits": [28, 29], "name": "ROW_SIZE"},
10546 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"}
10551 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
10552 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
10553 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
10554 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
10559 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
10560 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
10561 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
10562 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
10563 {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
10568 {"bits": [0, 15], "name": "BASE"},
10569 {"bits": [16, 31], "name": "UNUSED"}
10574 {"bits": [0, 5], "name": "AINC"},
10575 {"bits": [6, 7], "name": "UNUSED1"},
10576 {"bits": [8, 9], "name": "DMODE"},
10577 {"bits": [10, 31], "name": "UNUSED2"}
10582 {"bits": [0, 0], "name": "COMPLETE"},
10583 {"bits": [1, 31], "name": "UNUSED"}
10588 {"bits": [0, 7], "name": "OFFSET0"},
10589 {"bits": [8, 31], "name": "UNUSED"}
10594 {"bits": [0, 7], "name": "OFFSET1"},
10595 {"bits": [8, 31], "name": "UNUSED"}
10600 {"bits": [0, 7], "name": "OP"},
10601 {"bits": [8, 31], "name": "UNUSED"}
10606 {"bits": [0, 15], "name": "SIZE"},
10607 {"bits": [16, 31], "name": "UNUSED"}
10612 {"bits": [0, 0], "name": "FLAG"},
10613 {"bits": [1, 12], "name": "COUNTER"},
10614 {"bits": [13, 13], "name": "TYPE"},
10615 {"bits": [14, 14], "name": "DED"},
10616 {"bits": [15, 15], "name": "RELEASE_ALL"},
10617 {"bits": [16, 27], "name": "HEAD_QUEUE"},
10618 {"bits": [28, 28], "name": "HEAD_VALID"},
10619 {"bits": [29, 29], "name": "HEAD_FLAG"},
10620 {"bits": [30, 31], "name": "UNUSED1"}
10625 {"bits": [0, 15], "name": "RESOURCE_CNT"},
10626 {"bits": [16, 31], "name": "UNUSED"}
10631 {"bits": [0, 5], "name": "INDEX"},
10632 {"bits": [6, 31], "name": "UNUSED"}
10637 {"bits": [0, 15], "name": "DS_ADDRESS"},
10638 {"bits": [16, 19], "name": "CRAWLER"},
10639 {"bits": [20, 21], "name": "CRAWLER_TYPE"},
10640 {"bits": [22, 29], "name": "UNUSED"},
10641 {"bits": [30, 30], "name": "NO_ALLOC"},
10642 {"bits": [31, 31], "name": "ENABLE"}
10647 {"bits": [0, 3], "name": "INDEX"},
10648 {"bits": [4, 31], "name": "UNUSED"}
10653 {"bits": [0, 30], "name": "VALUE"},
10654 {"bits": [31, 31], "name": "INCDEC"}
10659 {"bits": [0, 7], "name": "INSTANCE_INDEX"},
10660 {"bits": [8, 15], "name": "SH_INDEX"},
10661 {"bits": [16, 23], "name": "SE_INDEX"},
10662 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"},
10663 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
10664 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
10669 {"bits": [0, 5], "name": "PERF_SEL"},
10670 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
10671 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
10672 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"},
10673 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
10674 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
10675 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
10676 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
10677 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
10678 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
10679 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
10680 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
10681 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
10682 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"},
10683 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
10684 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
10685 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
10686 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"},
10687 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"}
10692 {"bits": [0, 5], "name": "PERF_SEL"},
10693 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
10694 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
10695 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
10696 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
10697 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
10698 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
10699 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
10700 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
10701 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"},
10702 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
10703 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}
10708 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
10709 {"bits": [5, 5], "name": "SRBM_RQ_PENDING"},
10710 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
10711 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
10712 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
10713 {"bits": [12, 12], "name": "DB_CLEAN"},
10714 {"bits": [13, 13], "name": "CB_CLEAN"},
10715 {"bits": [14, 14], "name": "TA_BUSY"},
10716 {"bits": [15, 15], "name": "GDS_BUSY"},
10717 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"},
10718 {"bits": [17, 17], "name": "VGT_BUSY"},
10719 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"},
10720 {"bits": [19, 19], "name": "IA_BUSY"},
10721 {"bits": [20, 20], "name": "SX_BUSY"},
10722 {"bits": [21, 21], "name": "WD_BUSY"},
10723 {"bits": [22, 22], "name": "SPI_BUSY"},
10724 {"bits": [23, 23], "name": "BCI_BUSY"},
10725 {"bits": [24, 24], "name": "SC_BUSY"},
10726 {"bits": [25, 25], "name": "PA_BUSY"},
10727 {"bits": [26, 26], "name": "DB_BUSY"},
10728 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
10729 {"bits": [29, 29], "name": "CP_BUSY"},
10730 {"bits": [30, 30], "name": "CB_BUSY"},
10731 {"bits": [31, 31], "name": "GUI_ACTIVE"}
10736 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
10737 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
10738 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
10739 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
10740 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
10741 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
10742 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
10743 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
10744 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
10745 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
10746 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
10747 {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
10748 {"bits": [24, 24], "name": "RLC_BUSY"},
10749 {"bits": [25, 25], "name": "TC_BUSY"},
10750 {"bits": [26, 26], "name": "TCC_CC_RESIDENT"},
10751 {"bits": [28, 28], "name": "CPF_BUSY"},
10752 {"bits": [29, 29], "name": "CPC_BUSY"},
10753 {"bits": [30, 30], "name": "CPG_BUSY"}
10758 {"bits": [1, 1], "name": "DB_CLEAN"},
10759 {"bits": [2, 2], "name": "CB_CLEAN"},
10760 {"bits": [22, 22], "name": "BCI_BUSY"},
10761 {"bits": [23, 23], "name": "VGT_BUSY"},
10762 {"bits": [24, 24], "name": "PA_BUSY"},
10763 {"bits": [25, 25], "name": "TA_BUSY"},
10764 {"bits": [26, 26], "name": "SX_BUSY"},
10765 {"bits": [27, 27], "name": "SPI_BUSY"},
10766 {"bits": [29, 29], "name": "SC_BUSY"},
10767 {"bits": [30, 30], "name": "DB_BUSY"},
10768 {"bits": [31, 31], "name": "CB_BUSY"}
10773 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
10774 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
10775 {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
10776 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
10777 {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
10778 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
10779 {"bits": [28, 31], "name": "MAX_PRIMGRP_IN_WAVE"}
10784 {"bits": [0, 0], "name": "UCP_ENA_0"},
10785 {"bits": [1, 1], "name": "UCP_ENA_1"},
10786 {"bits": [2, 2], "name": "UCP_ENA_2"},
10787 {"bits": [3, 3], "name": "UCP_ENA_3"},
10788 {"bits": [4, 4], "name": "UCP_ENA_4"},
10789 {"bits": [5, 5], "name": "UCP_ENA_5"},
10790 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
10791 {"bits": [14, 15], "name": "PS_UCP_MODE"},
10792 {"bits": [16, 16], "name": "CLIP_DISABLE"},
10793 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
10794 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
10795 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
10796 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
10797 {"bits": [21, 21], "name": "VTX_KILL_OR"},
10798 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
10799 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
10800 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
10801 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
10802 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}
10807 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
10808 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
10809 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
10810 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
10811 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
10812 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
10813 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
10814 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
10815 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
10816 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
10817 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
10818 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
10819 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
10820 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
10821 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
10822 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
10827 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
10828 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
10829 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
10830 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
10831 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
10832 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
10833 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
10834 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
10835 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
10836 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
10837 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
10838 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
10839 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
10840 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
10841 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
10842 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
10843 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
10844 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
10845 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
10846 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
10847 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
10848 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
10849 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
10850 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
10851 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
10852 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
10853 {"bits": [26, 26], "name": "USE_VTX_LINE_WIDTH"}
10858 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
10859 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
10860 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
10861 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
10862 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
10863 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
10864 {"bits": [8, 8], "name": "VTX_XY_FMT"},
10865 {"bits": [9, 9], "name": "VTX_Z_FMT"},
10866 {"bits": [10, 10], "name": "VTX_W0_FMT"},
10867 {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
10872 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
10873 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
10874 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
10875 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
10876 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}
10881 {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
10882 {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
10887 {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
10888 {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
10893 {"bits": [0, 3], "name": "S0_X"},
10894 {"bits": [4, 7], "name": "S0_Y"},
10895 {"bits": [8, 11], "name": "S1_X"},
10896 {"bits": [12, 15], "name": "S1_Y"},
10897 {"bits": [16, 19], "name": "S2_X"},
10898 {"bits": [20, 23], "name": "S2_Y"},
10899 {"bits": [24, 27], "name": "S3_X"},
10900 {"bits": [28, 31], "name": "S3_Y"}
10905 {"bits": [0, 3], "name": "S4_X"},
10906 {"bits": [4, 7], "name": "S4_Y"},
10907 {"bits": [8, 11], "name": "S5_X"},
10908 {"bits": [12, 15], "name": "S5_Y"},
10909 {"bits": [16, 19], "name": "S6_X"},
10910 {"bits": [20, 23], "name": "S6_Y"},
10911 {"bits": [24, 27], "name": "S7_X"},
10912 {"bits": [28, 31], "name": "S7_Y"}
10917 {"bits": [0, 3], "name": "S8_X"},
10918 {"bits": [4, 7], "name": "S8_Y"},
10919 {"bits": [8, 11], "name": "S9_X"},
10920 {"bits": [12, 15], "name": "S9_Y"},
10921 {"bits": [16, 19], "name": "S10_X"},
10922 {"bits": [20, 23], "name": "S10_Y"},
10923 {"bits": [24, 27], "name": "S11_X"},
10924 {"bits": [28, 31], "name": "S11_Y"}
10929 {"bits": [0, 3], "name": "S12_X"},
10930 {"bits": [4, 7], "name": "S12_Y"},
10931 {"bits": [8, 11], "name": "S13_X"},
10932 {"bits": [12, 15], "name": "S13_Y"},
10933 {"bits": [16, 19], "name": "S14_X"},
10934 {"bits": [20, 23], "name": "S14_Y"},
10935 {"bits": [24, 27], "name": "S15_X"},
10936 {"bits": [28, 31], "name": "S15_Y"}
10941 {"bits": [0, 3], "name": "DISTANCE_0"},
10942 {"bits": [4, 7], "name": "DISTANCE_1"},
10943 {"bits": [8, 11], "name": "DISTANCE_2"},
10944 {"bits": [12, 15], "name": "DISTANCE_3"},
10945 {"bits": [16, 19], "name": "DISTANCE_4"},
10946 {"bits": [20, 23], "name": "DISTANCE_5"},
10947 {"bits": [24, 27], "name": "DISTANCE_6"},
10948 {"bits": [28, 31], "name": "DISTANCE_7"}
10953 {"bits": [0, 3], "name": "DISTANCE_8"},
10954 {"bits": [4, 7], "name": "DISTANCE_9"},
10955 {"bits": [8, 11], "name": "DISTANCE_10"},
10956 {"bits": [12, 15], "name": "DISTANCE_11"},
10957 {"bits": [16, 19], "name": "DISTANCE_12"},
10958 {"bits": [20, 23], "name": "DISTANCE_13"},
10959 {"bits": [24, 27], "name": "DISTANCE_14"},
10960 {"bits": [28, 31], "name": "DISTANCE_15"}
10965 {"bits": [0, 14], "name": "BR_X"},
10966 {"bits": [16, 30], "name": "BR_Y"}
10971 {"bits": [0, 14], "name": "TL_X"},
10972 {"bits": [16, 30], "name": "TL_Y"}
10977 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
10982 {"bits": [0, 3], "name": "ER_TRI"},
10983 {"bits": [4, 7], "name": "ER_POINT"},
10984 {"bits": [8, 11], "name": "ER_RECT"},
10985 {"bits": [12, 17], "name": "ER_LINE_LR"},
10986 {"bits": [18, 23], "name": "ER_LINE_RL"},
10987 {"bits": [24, 27], "name": "ER_LINE_TB"},
10988 {"bits": [28, 31], "name": "ER_LINE_BT"}
10993 {"bits": [0, 14], "name": "TL_X"},
10994 {"bits": [16, 30], "name": "TL_Y"},
10995 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
11000 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
11001 {"bits": [10, 10], "name": "LAST_PIXEL"},
11002 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
11003 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}
11008 {"bits": [0, 15], "name": "LINE_PATTERN"},
11009 {"bits": [16, 23], "name": "REPEAT_COUNT"},
11010 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
11011 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
11016 {"bits": [0, 3], "name": "CURRENT_PTR"},
11017 {"bits": [8, 15], "name": "CURRENT_COUNT"}
11022 {"bits": [0, 0], "name": "MSAA_ENABLE"},
11023 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
11024 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
11025 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}
11030 {"bits": [0, 0], "name": "WALK_SIZE"},
11031 {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
11032 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
11033 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
11034 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
11035 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
11036 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
11037 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
11038 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
11039 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
11040 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
11041 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
11042 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
11043 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
11044 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
11045 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
11046 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
11047 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
11048 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
11049 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
11050 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
11051 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
11052 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
11053 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
11058 {"bits": [0, 13], "name": "X_COORD"}
11063 {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
11064 {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
11069 {"bits": [0, 13], "name": "Y_COORD"}
11074 {"bits": [0, 9], "name": "PERF_SEL"}
11079 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
11080 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
11081 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
11082 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
11083 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
11084 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
11085 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
11086 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
11087 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
11088 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
11089 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
11090 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
11091 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
11092 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
11093 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
11098 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
11099 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
11100 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
11105 {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
11106 {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
11111 {"bits": [0, 15], "name": "X"},
11112 {"bits": [16, 31], "name": "Y"}
11117 {"bits": [0, 15], "name": "BR_X"},
11118 {"bits": [16, 31], "name": "BR_Y"}
11123 {"bits": [0, 15], "name": "TL_X"},
11124 {"bits": [16, 31], "name": "TL_Y"}
11129 {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"}
11134 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
11135 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
11140 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
11141 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
11146 {"bits": [0, 15], "name": "WIDTH"}
11151 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
11152 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
11153 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
11154 {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
11159 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
11164 {"bits": [0, 15], "name": "PERFCOUNTER_HI"}
11169 {"bits": [0, 9], "name": "PERF_SEL"},
11170 {"bits": [10, 19], "name": "PERF_SEL1"},
11171 {"bits": [20, 23], "name": "CNTR_MODE"}
11176 {"bits": [0, 9], "name": "PERF_SEL2"},
11177 {"bits": [10, 19], "name": "PERF_SEL3"}
11182 {"bits": [0, 9], "name": "PERF_SEL"},
11183 {"bits": [20, 23], "name": "CNTR_MODE"}
11188 {"bits": [0, 15], "name": "MIN_SIZE"},
11189 {"bits": [16, 31], "name": "MAX_SIZE"}
11194 {"bits": [0, 15], "name": "HEIGHT"},
11195 {"bits": [16, 31], "name": "WIDTH"}
11200 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
11201 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
11206 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
11207 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
11208 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
11209 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
11210 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
11211 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
11212 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
11213 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
11214 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
11215 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
11216 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
11221 {"bits": [0, 0], "name": "CULL_FRONT"},
11222 {"bits": [1, 1], "name": "CULL_BACK"},
11223 {"bits": [2, 2], "name": "FACE"},
11224 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
11225 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
11226 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
11227 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
11228 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
11229 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
11230 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
11231 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
11232 {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
11233 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}
11238 {"bits": [0, 0], "name": "PIX_CENTER"},
11239 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
11240 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
11245 {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
11250 {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
11255 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
11256 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
11261 {"bits": [0, 7], "name": "PERFMON_SAMPLE_DELAY"},
11262 {"bits": [8, 31], "name": "RESERVED"}
11267 {"bits": [0, 11], "name": "RESERVED1"},
11268 {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
11269 {"bits": [14, 15], "name": "RESERVED"},
11270 {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
11275 {"bits": [0, 15], "name": "RING_BASE_HI"},
11276 {"bits": [16, 31], "name": "RESERVED"}
11281 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
11282 {"bits": [8, 10], "name": "RESERVED1"},
11283 {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
11284 {"bits": [16, 20], "name": "SE0_NUM_LINE"},
11285 {"bits": [21, 25], "name": "SE1_NUM_LINE"},
11286 {"bits": [26, 30], "name": "SE2_NUM_LINE"},
11287 {"bits": [31, 31], "name": "RESERVED"}
11292 {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
11293 {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
11298 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
11299 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
11300 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
11301 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
11302 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
11303 {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
11304 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
11309 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
11310 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
11311 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
11312 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
11313 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},
11314 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}
11319 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
11320 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
11321 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
11322 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
11323 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
11324 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
11325 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
11330 {"bits": [0, 7], "name": "PERF_SEL"}
11335 {"bits": [0, 3], "name": "BIN0_MIN"},
11336 {"bits": [4, 7], "name": "BIN0_MAX"},
11337 {"bits": [8, 11], "name": "BIN1_MIN"},
11338 {"bits": [12, 15], "name": "BIN1_MAX"},
11339 {"bits": [16, 19], "name": "BIN2_MIN"},
11340 {"bits": [20, 23], "name": "BIN2_MAX"},
11341 {"bits": [24, 27], "name": "BIN3_MIN"},
11342 {"bits": [28, 31], "name": "BIN3_MAX"}
11347 {"bits": [0, 5], "name": "OFFSET"},
11348 {"bits": [8, 9], "name": "DEFAULT_VAL"},
11349 {"bits": [10, 10], "name": "FLAT_SHADE"},
11350 {"bits": [13, 16], "name": "CYL_WRAP"},
11351 {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
11352 {"bits": [18, 18], "name": "DUP"},
11353 {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
11354 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
11355 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
11356 {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
11357 {"bits": [24, 24], "name": "ATTR0_VALID"},
11358 {"bits": [25, 25], "name": "ATTR1_VALID"}
11363 {"bits": [0, 5], "name": "OFFSET"},
11364 {"bits": [8, 9], "name": "DEFAULT_VAL"},
11365 {"bits": [10, 10], "name": "FLAT_SHADE"},
11366 {"bits": [18, 18], "name": "DUP"},
11367 {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
11368 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
11369 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
11370 {"bits": [24, 24], "name": "ATTR0_VALID"},
11371 {"bits": [25, 25], "name": "ATTR1_VALID"}
11376 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
11377 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
11378 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
11379 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
11380 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
11381 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
11382 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
11383 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
11384 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
11385 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
11386 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
11387 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
11388 {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
11389 {"bits": [13, 13], "name": "ANCILLARY_ENA"},
11390 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
11391 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
11396 {"bits": [0, 5], "name": "NUM_INTERP"},
11397 {"bits": [6, 6], "name": "PARAM_GEN"},
11398 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"}
11403 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
11404 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
11405 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
11406 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
11407 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
11408 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
11409 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
11410 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
11415 {"bits": [0, 5], "name": "LIMIT"}
11420 {"bits": [0, 5], "name": "VGPRS"},
11421 {"bits": [6, 9], "name": "SGPRS"},
11422 {"bits": [10, 11], "name": "PRIORITY"},
11423 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11424 {"bits": [20, 20], "name": "PRIV"},
11425 {"bits": [21, 21], "name": "DX10_CLAMP"},
11426 {"bits": [22, 22], "name": "DEBUG_MODE"},
11427 {"bits": [23, 23], "name": "IEEE_MODE"},
11428 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
11429 {"bits": [25, 27], "name": "CACHE_CTL"},
11430 {"bits": [28, 28], "name": "CDBG_USER"}
11435 {"bits": [0, 5], "name": "VGPRS"},
11436 {"bits": [6, 9], "name": "SGPRS"},
11437 {"bits": [10, 11], "name": "PRIORITY"},
11438 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11439 {"bits": [20, 20], "name": "PRIV"},
11440 {"bits": [21, 21], "name": "DX10_CLAMP"},
11441 {"bits": [22, 22], "name": "DEBUG_MODE"},
11442 {"bits": [23, 23], "name": "IEEE_MODE"},
11443 {"bits": [24, 26], "name": "CACHE_CTL"},
11444 {"bits": [27, 27], "name": "CDBG_USER"}
11449 {"bits": [0, 5], "name": "VGPRS"},
11450 {"bits": [6, 9], "name": "SGPRS"},
11451 {"bits": [10, 11], "name": "PRIORITY"},
11452 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11453 {"bits": [20, 20], "name": "PRIV"},
11454 {"bits": [21, 21], "name": "DX10_CLAMP"},
11455 {"bits": [22, 22], "name": "DEBUG_MODE"},
11456 {"bits": [23, 23], "name": "IEEE_MODE"},
11457 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
11458 {"bits": [26, 28], "name": "CACHE_CTL"},
11459 {"bits": [29, 29], "name": "CDBG_USER"}
11464 {"bits": [0, 5], "name": "VGPRS"},
11465 {"bits": [6, 9], "name": "SGPRS"},
11466 {"bits": [10, 11], "name": "PRIORITY"},
11467 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11468 {"bits": [20, 20], "name": "PRIV"},
11469 {"bits": [21, 21], "name": "DX10_CLAMP"},
11470 {"bits": [22, 22], "name": "DEBUG_MODE"},
11471 {"bits": [23, 23], "name": "IEEE_MODE"},
11472 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
11473 {"bits": [25, 27], "name": "CACHE_CTL"},
11474 {"bits": [28, 28], "name": "CDBG_USER"}
11479 {"bits": [0, 5], "name": "VGPRS"},
11480 {"bits": [6, 9], "name": "SGPRS"},
11481 {"bits": [10, 11], "name": "PRIORITY"},
11482 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11483 {"bits": [20, 20], "name": "PRIV"},
11484 {"bits": [21, 21], "name": "DX10_CLAMP"},
11485 {"bits": [22, 22], "name": "DEBUG_MODE"},
11486 {"bits": [23, 23], "name": "IEEE_MODE"},
11487 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
11488 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
11489 {"bits": [27, 29], "name": "CACHE_CTL"},
11490 {"bits": [30, 30], "name": "CDBG_USER"}
11495 {"bits": [0, 0], "name": "SCRATCH_EN"},
11496 {"bits": [1, 5], "name": "USER_SGPR"},
11497 {"bits": [6, 6], "name": "TRAP_PRESENT"},
11498 {"bits": [7, 7], "name": "OC_LDS_EN"},
11499 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
11500 {"bits": [20, 28], "name": "LDS_SIZE"}
11505 {"bits": [0, 0], "name": "SCRATCH_EN"},
11506 {"bits": [1, 5], "name": "USER_SGPR"},
11507 {"bits": [6, 6], "name": "TRAP_PRESENT"},
11508 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11513 {"bits": [0, 0], "name": "SCRATCH_EN"},
11514 {"bits": [1, 5], "name": "USER_SGPR"},
11515 {"bits": [6, 6], "name": "TRAP_PRESENT"},
11516 {"bits": [7, 7], "name": "OC_LDS_EN"},
11517 {"bits": [8, 8], "name": "TG_SIZE_EN"},
11518 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11523 {"bits": [0, 0], "name": "SCRATCH_EN"},
11524 {"bits": [1, 5], "name": "USER_SGPR"},
11525 {"bits": [6, 6], "name": "TRAP_PRESENT"},
11526 {"bits": [7, 15], "name": "LDS_SIZE"},
11527 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11532 {"bits": [0, 0], "name": "SCRATCH_EN"},
11533 {"bits": [1, 5], "name": "USER_SGPR"},
11534 {"bits": [6, 6], "name": "TRAP_PRESENT"},
11535 {"bits": [7, 7], "name": "WAVE_CNT_EN"},
11536 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
11537 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11542 {"bits": [0, 0], "name": "SCRATCH_EN"},
11543 {"bits": [1, 5], "name": "USER_SGPR"},
11544 {"bits": [6, 6], "name": "TRAP_PRESENT"},
11545 {"bits": [7, 7], "name": "OC_LDS_EN"},
11546 {"bits": [8, 8], "name": "SO_BASE0_EN"},
11547 {"bits": [9, 9], "name": "SO_BASE1_EN"},
11548 {"bits": [10, 10], "name": "SO_BASE2_EN"},
11549 {"bits": [11, 11], "name": "SO_BASE3_EN"},
11550 {"bits": [12, 12], "name": "SO_EN"},
11551 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
11552 {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"}
11557 {"bits": [0, 15], "name": "CU_EN"},
11558 {"bits": [16, 21], "name": "WAVE_LIMIT"},
11559 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
11560 {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
11565 {"bits": [0, 5], "name": "WAVE_LIMIT"},
11566 {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
11567 {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"}
11572 {"bits": [0, 15], "name": "CU_EN"},
11573 {"bits": [16, 21], "name": "WAVE_LIMIT"},
11574 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
11579 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
11580 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
11581 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
11582 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}
11587 {"bits": [0, 7], "name": "MEM_BASE"}
11592 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
11597 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
11598 {"bits": [6, 6], "name": "VS_HALF_PACK"}
11603 {"bits": [0, 0], "name": "TARGET_INST"},
11604 {"bits": [1, 1], "name": "TARGET_DATA"},
11605 {"bits": [2, 2], "name": "INVALIDATE"},
11606 {"bits": [3, 3], "name": "WRITEBACK"},
11607 {"bits": [4, 4], "name": "VOL"},
11608 {"bits": [16, 16], "name": "COMPLETE"}
11613 {"bits": [0, 0], "name": "DWB"},
11614 {"bits": [1, 1], "name": "DIRTY"}
11619 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"},
11620 {"bits": [16, 29], "name": "STRIDE"},
11621 {"bits": [30, 30], "name": "CACHE_SWIZZLE"},
11622 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"}
11627 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
11628 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
11629 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
11630 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
11631 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"},
11632 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"},
11633 {"bits": [19, 20], "name": "ELEMENT_SIZE"},
11634 {"bits": [21, 22], "name": "INDEX_STRIDE"},
11635 {"bits": [23, 23], "name": "ADD_TID_ENABLE"},
11636 {"bits": [24, 24], "name": "ATC"},
11637 {"bits": [25, 25], "name": "HASH_ENABLE"},
11638 {"bits": [26, 26], "name": "HEAP"},
11639 {"bits": [27, 29], "name": "MTYPE"},
11640 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"}
11645 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"},
11646 {"bits": [8, 19], "name": "MIN_LOD"},
11647 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"},
11648 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"},
11649 {"bits": [30, 31], "name": "MTYPE"}
11654 {"bits": [0, 13], "name": "WIDTH"},
11655 {"bits": [14, 27], "name": "HEIGHT"},
11656 {"bits": [28, 30], "name": "PERF_MOD"},
11657 {"bits": [31, 31], "name": "INTERLACED"}
11662 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
11663 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
11664 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
11665 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
11666 {"bits": [12, 15], "name": "BASE_LEVEL"},
11667 {"bits": [16, 19], "name": "LAST_LEVEL"},
11668 {"bits": [20, 24], "name": "TILING_INDEX"},
11669 {"bits": [25, 25], "name": "POW2_PAD"},
11670 {"bits": [26, 26], "name": "MTYPE"},
11671 {"bits": [27, 27], "name": "ATC"},
11672 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"}
11677 {"bits": [0, 12], "name": "DEPTH"},
11678 {"bits": [13, 26], "name": "PITCH"}
11683 {"bits": [0, 12], "name": "BASE_ARRAY"},
11684 {"bits": [13, 25], "name": "LAST_ARRAY"}
11689 {"bits": [0, 11], "name": "MIN_LOD_WARN"},
11690 {"bits": [12, 19], "name": "COUNTER_BANK_ID"},
11691 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"},
11692 {"bits": [21, 21], "name": "COMPRESSION_EN"},
11693 {"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"},
11694 {"bits": [23, 23], "name": "COLOR_TRANSFORM"},
11695 {"bits": [24, 27], "name": "LOST_ALPHA_BITS"},
11696 {"bits": [28, 31], "name": "LOST_COLOR_BITS"}
11701 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"},
11702 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"},
11703 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"},
11704 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"},
11705 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"},
11706 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"},
11707 {"bits": [16, 18], "name": "ANISO_THRESHOLD"},
11708 {"bits": [19, 19], "name": "MC_COORD_TRUNC"},
11709 {"bits": [20, 20], "name": "FORCE_DEGAMMA"},
11710 {"bits": [21, 26], "name": "ANISO_BIAS"},
11711 {"bits": [27, 27], "name": "TRUNC_COORD"},
11712 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"},
11713 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"},
11714 {"bits": [31, 31], "name": "COMPAT_MODE"}
11719 {"bits": [0, 11], "name": "MIN_LOD"},
11720 {"bits": [12, 23], "name": "MAX_LOD"},
11721 {"bits": [24, 27], "name": "PERF_MIP"},
11722 {"bits": [28, 31], "name": "PERF_Z"}
11727 {"bits": [0, 13], "name": "LOD_BIAS"},
11728 {"bits": [14, 19], "name": "LOD_BIAS_SEC"},
11729 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"},
11730 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"},
11731 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"},
11732 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"},
11733 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"},
11734 {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"},
11735 {"bits": [30, 30], "name": "FILTER_PREC_FIX"},
11736 {"bits": [31, 31], "name": "ANISO_OVERRIDE"}
11741 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"},
11742 {"bits": [29, 29], "name": "UPGRADED_DEPTH"},
11743 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"}
11748 {"bits": [0, 8], "name": "PERF_SEL"},
11749 {"bits": [12, 15], "name": "SQC_BANK_MASK"},
11750 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"},
11751 {"bits": [20, 23], "name": "SPM_MODE"},
11752 {"bits": [24, 27], "name": "SIMD_MASK"},
11753 {"bits": [28, 31], "name": "PERF_MODE"}
11758 {"bits": [0, 0], "name": "PS_EN"},
11759 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
11760 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
11761 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
11762 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
11763 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
11764 {"bits": [6, 6], "name": "CS_EN"},
11765 {"bits": [8, 12], "name": "CNTR_RATE"},
11766 {"bits": [13, 13], "name": "DISABLE_FLUSH"}
11771 {"bits": [0, 0], "name": "FORCE_EN"}
11776 {"bits": [0, 15], "name": "SH0_MASK"},
11777 {"bits": [16, 31], "name": "SH1_MASK"}
11782 {"bits": [0, 3], "name": "ADDR_HI"}
11787 {"bits": [31, 31], "name": "RESET_BUFFER"}
11792 {"bits": [0, 2], "name": "HIWATER"}
11797 {"bits": [0, 4], "name": "CU_SEL"},
11798 {"bits": [5, 5], "name": "SH_SEL"},
11799 {"bits": [7, 7], "name": "REG_STALL_EN"},
11800 {"bits": [8, 11], "name": "SIMD_EN"},
11801 {"bits": [12, 13], "name": "VM_ID_MASK"},
11802 {"bits": [14, 14], "name": "SPI_STALL_EN"},
11803 {"bits": [15, 15], "name": "SQ_STALL_EN"},
11804 {"bits": [16, 31], "name": "RANDOM_SEED"}
11809 {"bits": [0, 2], "name": "MASK_PS"},
11810 {"bits": [3, 5], "name": "MASK_VS"},
11811 {"bits": [6, 8], "name": "MASK_GS"},
11812 {"bits": [9, 11], "name": "MASK_ES"},
11813 {"bits": [12, 14], "name": "MASK_HS"},
11814 {"bits": [15, 17], "name": "MASK_LS"},
11815 {"bits": [18, 20], "name": "MASK_CS"},
11816 {"bits": [21, 22], "name": "MODE"},
11817 {"bits": [23, 24], "name": "CAPTURE_MODE"},
11818 {"bits": [25, 25], "name": "AUTOFLUSH_EN"},
11819 {"bits": [26, 26], "name": "PRIV"},
11820 {"bits": [27, 28], "name": "ISSUE_MASK"},
11821 {"bits": [29, 29], "name": "TEST_MODE"},
11822 {"bits": [30, 30], "name": "INTERRUPT_EN"},
11823 {"bits": [31, 31], "name": "WRAP"}
11828 {"bits": [0, 21], "name": "SIZE"}
11833 {"bits": [0, 9], "name": "FINISH_PENDING"},
11834 {"bits": [16, 25], "name": "FINISH_DONE"},
11835 {"bits": [29, 29], "name": "NEW_BUF"},
11836 {"bits": [30, 30], "name": "BUSY"},
11837 {"bits": [31, 31], "name": "FULL"}
11842 {"bits": [0, 15], "name": "TOKEN_MASK"},
11843 {"bits": [16, 23], "name": "REG_MASK"},
11844 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"}
11849 {"bits": [0, 29], "name": "WPTR"},
11850 {"bits": [30, 31], "name": "READ_OFFSET"}
11855 {"bits": [0, 5], "name": "VGPR_BASE"},
11856 {"bits": [8, 13], "name": "VGPR_SIZE"},
11857 {"bits": [16, 21], "name": "SGPR_BASE"},
11858 {"bits": [24, 27], "name": "SGPR_SIZE"}
11863 {"bits": [0, 3], "name": "WAVE_ID"},
11864 {"bits": [4, 5], "name": "SIMD_ID"},
11865 {"bits": [6, 7], "name": "PIPE_ID"},
11866 {"bits": [8, 11], "name": "CU_ID"},
11867 {"bits": [12, 12], "name": "SH_ID"},
11868 {"bits": [13, 14], "name": "SE_ID"},
11869 {"bits": [16, 19], "name": "TG_ID"},
11870 {"bits": [20, 23], "name": "VM_ID"},
11871 {"bits": [24, 26], "name": "QUEUE_ID"},
11872 {"bits": [27, 29], "name": "STATE_ID"},
11873 {"bits": [30, 31], "name": "ME_ID"}
11878 {"bits": [0, 2], "name": "IBUF_ST"},
11879 {"bits": [3, 3], "name": "PC_INVALID"},
11880 {"bits": [4, 4], "name": "NEED_NEXT_DW"},
11881 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"},
11882 {"bits": [8, 9], "name": "IBUF_RPTR"},
11883 {"bits": [10, 11], "name": "IBUF_WPTR"},
11884 {"bits": [16, 19], "name": "INST_STR_ST"},
11885 {"bits": [20, 23], "name": "MISC_CNT"},
11886 {"bits": [24, 25], "name": "ECC_ST"},
11887 {"bits": [26, 26], "name": "IS_HYB"},
11888 {"bits": [27, 28], "name": "HYB_CNT"},
11889 {"bits": [29, 29], "name": "KILL"},
11890 {"bits": [30, 30], "name": "NEED_KILL_IFETCH"}
11895 {"bits": [0, 0], "name": "IXNACK"},
11896 {"bits": [1, 1], "name": "XNACK"},
11897 {"bits": [2, 2], "name": "TA_NEED_RESET"},
11898 {"bits": [4, 7], "name": "XCNT"},
11899 {"bits": [8, 11], "name": "QCNT"}
11904 {"bits": [0, 3], "name": "VM_CNT"},
11905 {"bits": [4, 6], "name": "EXP_CNT"},
11906 {"bits": [8, 11], "name": "LGKM_CNT"},
11907 {"bits": [12, 14], "name": "VALU_CNT"},
11908 {"bits": [15, 15], "name": "FIRST_REPLAY"},
11909 {"bits": [16, 19], "name": "RCNT"}
11914 {"bits": [0, 7], "name": "LDS_BASE"},
11915 {"bits": [12, 20], "name": "LDS_SIZE"}
11920 {"bits": [0, 3], "name": "FP_ROUND"},
11921 {"bits": [4, 7], "name": "FP_DENORM"},
11922 {"bits": [8, 8], "name": "DX10_CLAMP"},
11923 {"bits": [9, 9], "name": "IEEE"},
11924 {"bits": [10, 10], "name": "LOD_CLAMPED"},
11925 {"bits": [11, 11], "name": "DEBUG_EN"},
11926 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
11927 {"bits": [27, 27], "name": "GPR_IDX_EN"},
11928 {"bits": [28, 28], "name": "VSKIP"},
11929 {"bits": [29, 31], "name": "CSP"}
11934 {"bits": [0, 15], "name": "PC_HI"}
11939 {"bits": [0, 0], "name": "SCC"},
11940 {"bits": [1, 2], "name": "SPI_PRIO"},
11941 {"bits": [3, 4], "name": "USER_PRIO"},
11942 {"bits": [5, 5], "name": "PRIV"},
11943 {"bits": [6, 6], "name": "TRAP_EN"},
11944 {"bits": [7, 7], "name": "TTRACE_EN"},
11945 {"bits": [8, 8], "name": "EXPORT_RDY"},
11946 {"bits": [9, 9], "name": "EXECZ"},
11947 {"bits": [10, 10], "name": "VCCZ"},
11948 {"bits": [11, 11], "name": "IN_TG"},
11949 {"bits": [12, 12], "name": "IN_BARRIER"},
11950 {"bits": [13, 13], "name": "HALT"},
11951 {"bits": [14, 14], "name": "TRAP"},
11952 {"bits": [15, 15], "name": "TTRACE_CU_EN"},
11953 {"bits": [16, 16], "name": "VALID"},
11954 {"bits": [17, 17], "name": "ECC_ERR"},
11955 {"bits": [18, 18], "name": "SKIP_EXPORT"},
11956 {"bits": [19, 19], "name": "PERF_EN"},
11957 {"bits": [20, 20], "name": "COND_DBG_USER"},
11958 {"bits": [21, 21], "name": "COND_DBG_SYS"},
11959 {"bits": [22, 22], "name": "ALLOW_REPLAY"},
11960 {"bits": [23, 23], "name": "INST_ATC"},
11961 {"bits": [27, 27], "name": "MUST_EXPORT"}
11966 {"bits": [0, 7], "name": "ADDR_HI"}
11971 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
11972 {"bits": [10, 10], "name": "SAVECTX"},
11973 {"bits": [16, 21], "name": "EXCP_CYCLE"},
11974 {"bits": [29, 31], "name": "DP_RATE"}
11979 {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
11980 {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
11981 {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
11982 {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
11983 {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
11984 {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
11985 {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
11986 {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
11987 {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
11988 {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
11989 {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
11990 {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
11991 {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
11992 {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
11993 {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
11994 {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
11995 {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
12000 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
12001 {"bits": [4, 7], "name": "MRT1_EPSILON"},
12002 {"bits": [8, 11], "name": "MRT2_EPSILON"},
12003 {"bits": [12, 15], "name": "MRT3_EPSILON"},
12004 {"bits": [16, 19], "name": "MRT4_EPSILON"},
12005 {"bits": [20, 23], "name": "MRT5_EPSILON"},
12006 {"bits": [24, 27], "name": "MRT6_EPSILON"},
12007 {"bits": [28, 31], "name": "MRT7_EPSILON"}
12012 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
12013 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
12014 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
12015 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
12016 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
12017 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
12022 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"},
12023 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"},
12024 {"bits": [20, 23], "name": "CNTR_MODE"}
12029 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"},
12030 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"}
12035 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
12036 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
12037 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
12038 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
12039 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
12040 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
12041 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
12042 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
12047 {"bits": [0, 7], "name": "ADDRESS"}
12052 {"bits": [0, 9], "name": "PERF_SEL2"},
12053 {"bits": [10, 19], "name": "PERF_SEL3"},
12054 {"bits": [24, 27], "name": "PERF_MODE2"},
12055 {"bits": [28, 31], "name": "PERF_MODE3"}
12060 {"bits": [0, 9], "name": "PERF_SEL"},
12061 {"bits": [20, 23], "name": "CNTR_MODE"},
12062 {"bits": [28, 31], "name": "PERF_MODE"}
12067 {"bits": [0, 7], "name": "PERF_SEL"},
12068 {"bits": [10, 17], "name": "PERF_SEL1"},
12069 {"bits": [20, 23], "name": "CNTR_MODE"},
12070 {"bits": [24, 27], "name": "PERF_MODE1"},
12071 {"bits": [28, 31], "name": "PERF_MODE"}
12076 {"bits": [0, 7], "name": "PERF_SEL2"},
12077 {"bits": [10, 17], "name": "PERF_SEL3"},
12078 {"bits": [24, 27], "name": "PERF_MODE3"},
12079 {"bits": [28, 31], "name": "PERF_MODE2"}
12084 {"bits": [0, 7], "name": "BASE_ADDR"}
12089 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
12090 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
12091 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
12092 {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
12093 {"bits": [9, 9], "name": "NOT_EOP"},
12094 {"bits": [10, 10], "name": "REQ_PATH"},
12095 {"bits": [11, 12], "name": "MTYPE"}
12100 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
12101 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
12102 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
12103 {"bits": [5, 5], "name": "NOT_EOP"},
12104 {"bits": [6, 6], "name": "USE_OPAQUE"}
12109 {"bits": [0, 14], "name": "ITEMSIZE"}
12114 {"bits": [0, 10], "name": "ES_PER_GS"}
12119 {"bits": [0, 27], "name": "ADDRESS_LOW"}
12124 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
12125 {"bits": [18, 26], "name": "ADDRESS_HI"},
12126 {"bits": [27, 27], "name": "EXTENDED_EVENT"}
12131 {"bits": [0, 3], "name": "DECR"}
12136 {"bits": [0, 3], "name": "FIRST_DECR"}
12141 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
12142 {"bits": [14, 14], "name": "RETAIN_ORDER"},
12143 {"bits": [15, 15], "name": "RETAIN_QUADS"},
12144 {"bits": [16, 18], "name": "PRIM_ORDER"}
12149 {"bits": [0, 0], "name": "COMP_X_EN"},
12150 {"bits": [1, 1], "name": "COMP_Y_EN"},
12151 {"bits": [2, 2], "name": "COMP_Z_EN"},
12152 {"bits": [3, 3], "name": "COMP_W_EN"},
12153 {"bits": [8, 15], "name": "STRIDE"},
12154 {"bits": [16, 23], "name": "SHIFT"}
12159 {"bits": [0, 3], "name": "X_CONV"},
12160 {"bits": [4, 7], "name": "X_OFFSET"},
12161 {"bits": [8, 11], "name": "Y_CONV"},
12162 {"bits": [12, 15], "name": "Y_OFFSET"},
12163 {"bits": [16, 19], "name": "Z_CONV"},
12164 {"bits": [20, 23], "name": "Z_OFFSET"},
12165 {"bits": [24, 27], "name": "W_CONV"},
12166 {"bits": [28, 31], "name": "W_OFFSET"}
12171 {"bits": [0, 14], "name": "OFFSET"}
12176 {"bits": [0, 0], "name": "ENABLE"},
12177 {"bits": [2, 8], "name": "CNT"}
12182 {"bits": [0, 10], "name": "MAX_VERT_OUT"}
12187 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
12188 {"bits": [3, 3], "name": "RESERVED_0"},
12189 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
12190 {"bits": [6, 10], "name": "RESERVED_1"},
12191 {"bits": [11, 11], "name": "GS_C_PACK_EN"},
12192 {"bits": [12, 12], "name": "RESERVED_2"},
12193 {"bits": [13, 13], "name": "ES_PASSTHRU"},
12194 {"bits": [14, 14], "name": "RESERVED_3"},
12195 {"bits": [15, 15], "name": "RESERVED_4"},
12196 {"bits": [16, 16], "name": "RESERVED_5"},
12197 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
12198 {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
12199 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
12200 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
12201 {"bits": [21, 22], "name": "ONCHIP"}
12206 {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
12207 {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"}
12212 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
12213 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
12214 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
12215 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
12216 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
12221 {"bits": [0, 10], "name": "GS_PER_ES"}
12226 {"bits": [0, 3], "name": "GS_PER_VS"}
12231 {"bits": [0, 1], "name": "TESS_MODE"}
12236 {"bits": [0, 7], "name": "REUSE_DEPTH"}
12241 {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},
12242 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
12247 {"bits": [0, 7], "name": "NUM_PATCHES"},
12248 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
12249 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
12254 {"bits": [0, 0], "name": "RESET_EN"}
12259 {"bits": [0, 2], "name": "PATH_SELECT"}
12264 {"bits": [0, 6], "name": "DEALLOC_DIST"}
12269 {"bits": [0, 7], "name": "PERF_SEL"},
12270 {"bits": [28, 31], "name": "PERF_MODE"}
12275 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"}
12280 {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
12281 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}
12286 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
12291 {"bits": [0, 0], "name": "REUSE_OFF"}
12296 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
12297 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
12298 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
12299 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
12300 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
12301 {"bits": [8, 8], "name": "DYNAMIC_HS"},
12302 {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
12303 {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
12304 {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
12305 {"bits": [12, 12], "name": "VS_WAVE_ID_EN"}
12310 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
12311 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
12312 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
12313 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
12318 {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
12319 {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
12320 {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
12321 {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
12322 {"bits": [4, 6], "name": "RAST_STREAM"},
12323 {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
12324 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
12329 {"bits": [0, 8], "name": "VERTEX_STRIDE"}
12334 {"bits": [0, 9], "name": "STRIDE"}
12339 {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
12340 {"bits": [8, 15], "name": "ACCUM_TRI"},
12341 {"bits": [16, 23], "name": "ACCUM_QUAD"},
12342 {"bits": [24, 31], "name": "DONUT_SPLIT"}
12347 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
12348 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
12349 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
12350 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
12351 {"bits": [9, 9], "name": "DEPRECATED"},
12352 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
12353 {"bits": [14, 14], "name": "DISABLE_DONUTS"},
12354 {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
12355 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
12356 {"bits": [19, 20], "name": "MTYPE"}
12361 {"bits": [0, 15], "name": "SIZE"}
12366 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
12371 {"bits": [0, 0], "name": "VTX_CNT_EN"}