Cross Reference: /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/radv

Lines Matching refs:outinfo
2074       if (!nir[MESA_SHADER_TESS_CTRL] && infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
2279          return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2281          return &pipeline->gs_copy_shader->info.vs.outinfo;
2283       return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2285       return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2771       if (es_stage == MESA_SHADER_VERTEX && infos[es_stage].vs.outinfo.export_prim_id)
2783                                              infos[es_stage].vs.outinfo.export_prim_id);
2871             infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id = true;
2873             infos[MESA_SHADER_TESS_EVAL].tes.outinfo.export_prim_id = true;
2881             infos[MESA_SHADER_VERTEX].vs.outinfo.export_clip_dists = true;
2883             infos[MESA_SHADER_TESS_EVAL].tes.outinfo.export_clip_dists = true;
2886             infos[MESA_SHADER_GEOMETRY].vs.outinfo.export_clip_dists = true;
3583          if (infos[MESA_SHADER_GEOMETRY].vs.outinfo.export_clip_dists)
3584             info.vs.outinfo.export_clip_dists = true;
4373    const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4388    } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
4410    const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4412    clip_dist_mask = outinfo->clip_dist_mask;
4413    cull_dist_mask = outinfo->cull_dist_mask;
4417       outinfo->writes_primitive_shading_rate || pipeline->device->force_vrs != RADV_FORCE_VRS_NONE;
4418    bool misc_vec_ena = outinfo->writes_pointsize || outinfo->writes_layer ||
4419                        outinfo->writes_viewport_index || writes_primitive_shading_rate;
4423    nparams = MAX2(outinfo->param_exports, 1);
4427       spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
4435          S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
4437          S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
4439          S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
4443                           S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4444                              S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4445                              S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4454       radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, outinfo->writes_viewport_index);
4523    const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4525    clip_dist_mask = outinfo->clip_dist_mask;
4526    cull_dist_mask = outinfo->cull_dist_mask;
4530       outinfo->writes_primitive_shading_rate || pipeline->device->force_vrs != RADV_FORCE_VRS_NONE;
4531    bool misc_vec_ena = outinfo->writes_pointsize || outinfo->writes_layer ||
4532                        outinfo->writes_viewport_index || writes_primitive_shading_rate;
4533    bool es_enable_prim_id = outinfo->export_prim_id || (es && es->info.uses_prim_id);
4545    nparams = MAX2(outinfo->param_exports, 1);
4548       S_0286C4_VS_EXPORT_COUNT(nparams - 1) | S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
4555          S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
4557          S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
4559          S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
4563                           S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4564                              S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4565                              S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4575                              S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4634       if (outinfo->param_exports > 4)
4636       else if (outinfo->param_exports > 2)
4933    const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4939       unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4947       unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4957       unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4976       vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4982       vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4997       vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];