Lines Matching refs:infos
1826 nir_shader **nir, struct radv_shader_info *infos, struct gfx9_gs_info *out)
1828 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1834 es_info = has_tess ? &infos[MESA_SHADER_TESS_EVAL].tes.es_info
1835 : &infos[MESA_SHADER_VERTEX].vs.es_info;
1942 pipeline->device->physical_device->rad_info.chip_class, infos[es_stage].wave_size,
1944 infos[es_stage].workgroup_size = workgroup_size;
1945 infos[MESA_SHADER_GEOMETRY].workgroup_size = workgroup_size;
1990 nir_shader **nir, struct radv_shader_info *infos, struct gfx10_ngg_info *ngg)
1992 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
2064 ? &infos[MESA_SHADER_TESS_EVAL].so
2065 : &infos[MESA_SHADER_VERTEX].so;
2074 if (!nir[MESA_SHADER_TESS_CTRL] && infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
2118 wavesize = nir[MESA_SHADER_TESS_CTRL] ? infos[MESA_SHADER_TESS_EVAL].wave_size
2119 : infos[MESA_SHADER_VERTEX].wave_size;
2214 infos[MESA_SHADER_GEOMETRY].workgroup_size = workgroup_size;
2215 infos[es_stage].workgroup_size = workgroup_size;
2468 struct radv_shader_info infos[MESA_SHADER_STAGES])
2503 infos[MESA_SHADER_VERTEX].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2504 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2505 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2506 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2507 infos[MESA_SHADER_TESS_EVAL].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2508 infos[MESA_SHADER_TESS_EVAL].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2511 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2512 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2513 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2519 infos[MESA_SHADER_TESS_EVAL].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2520 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2523 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2529 infos[MESA_SHADER_VERTEX].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2530 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2533 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2744 struct radv_shader_info *infos, nir_shader **nir)
2759 infos[es_stage].has_ngg_culling = radv_consider_culling(
2760 device, nir[es_stage], ps_inputs_read, num_vertices_per_prim, &infos[es_stage]);
2763 infos[es_stage].has_ngg_early_prim_export = exec_list_is_singular(&impl->body);
2766 const struct gfx10_ngg_info *ngg_info = &infos[es_stage].ngg_info;
2771 if (es_stage == MESA_SHADER_VERTEX && infos[es_stage].vs.outinfo.export_prim_id)
2773 infos[es_stage].num_lds_blocks_when_not_culling =
2780 infos[es_stage].is_ngg_passthrough = infos[es_stage].is_ngg_passthrough &&
2781 !infos[es_stage].has_ngg_culling &&
2783 infos[es_stage].vs.outinfo.export_prim_id);
2792 struct radv_shader_info *infos, nir_shader **nir)
2804 infos[MESA_SHADER_VERTEX].vs.as_ls = true;
2809 infos[MESA_SHADER_TESS_EVAL].tes.as_es = true;
2811 infos[MESA_SHADER_VERTEX].vs.as_es = true;
2816 infos[MESA_SHADER_TESS_EVAL].is_ngg = true;
2818 infos[MESA_SHADER_VERTEX].is_ngg = true;
2830 infos[MESA_SHADER_TESS_EVAL].is_ngg = false;
2844 infos[MESA_SHADER_TESS_EVAL].is_ngg = false;
2846 infos[MESA_SHADER_VERTEX].is_ngg = false;
2855 if (nir[MESA_SHADER_TESS_CTRL] && infos[MESA_SHADER_TESS_EVAL].is_ngg) {
2856 infos[MESA_SHADER_TESS_EVAL].is_ngg_passthrough = true;
2857 } else if (nir[MESA_SHADER_VERTEX] && infos[MESA_SHADER_VERTEX].is_ngg) {
2858 infos[MESA_SHADER_VERTEX].is_ngg_passthrough = true;
2864 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2866 pipeline_key, &infos[MESA_SHADER_FRAGMENT]);
2869 if (infos[MESA_SHADER_FRAGMENT].ps.prim_id_input) {
2871 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id = true;
2873 infos[MESA_SHADER_TESS_EVAL].tes.outinfo.export_prim_id = true;
2879 if (!!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls) {
2881 infos[MESA_SHADER_VERTEX].vs.outinfo.export_clip_dists = true;
2883 infos[MESA_SHADER_TESS_EVAL].tes.outinfo.export_clip_dists = true;
2886 infos[MESA_SHADER_GEOMETRY].vs.outinfo.export_clip_dists = true;
2897 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2900 infos[MESA_SHADER_TESS_CTRL].vs.as_ls = true;
2904 &infos[MESA_SHADER_TESS_CTRL]);
2917 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2921 infos[MESA_SHADER_GEOMETRY].vs.as_es = infos[MESA_SHADER_VERTEX].vs.as_es;
2923 infos[MESA_SHADER_GEOMETRY].tes.as_es = infos[MESA_SHADER_TESS_EVAL].tes.as_es;
2925 infos[MESA_SHADER_GEOMETRY].is_ngg = infos[pre_stage].is_ngg;
2926 infos[MESA_SHADER_GEOMETRY].gs.es_type = pre_stage;
2930 &infos[MESA_SHADER_GEOMETRY]);
2940 radv_nir_shader_info_init(&infos[i]);
2941 radv_nir_shader_info_pass(pipeline->device, nir[i], pipeline_layout, pipeline_key, &infos[i]);
2969 infos[MESA_SHADER_COMPUTE].cs.subgroup_size = subgroup_size;
2974 infos[i].wave_size = radv_get_wave_size(pipeline->device, pStages[i], i, &infos[i]);
2975 infos[i].ballot_bit_size =
2976 radv_get_ballot_bit_size(pipeline->device, pStages[i], i, &infos[i]);
2982 infos[MESA_SHADER_FRAGMENT].workgroup_size = infos[MESA_SHADER_FRAGMENT].wave_size;
2988 infos[MESA_SHADER_COMPUTE].workgroup_size =
3038 gather_tess_info(struct radv_device *device, nir_shader **nir, struct radv_shader_info *infos,
3049 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs,
3050 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs,
3051 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs, device->tess_offchip_block_dw_size,
3057 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs, num_patches,
3058 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs,
3059 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs);
3061 infos[MESA_SHADER_TESS_CTRL].num_tess_patches = num_patches;
3062 infos[MESA_SHADER_TESS_CTRL].tcs.num_lds_blocks = tcs_lds_size;
3063 infos[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors =
3066 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read = nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
3067 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
3070 infos[MESA_SHADER_TESS_EVAL].num_tess_patches = num_patches;
3071 infos[MESA_SHADER_GEOMETRY].num_tess_patches = num_patches;
3072 infos[MESA_SHADER_VERTEX].num_tess_patches = num_patches;
3073 infos[MESA_SHADER_TESS_CTRL].tcs.tcs_vertices_out = tess_out_patch_size;
3074 infos[MESA_SHADER_VERTEX].tcs.tcs_vertices_out = tess_out_patch_size;
3086 infos[MESA_SHADER_VERTEX].vs.tcs_in_out_eq =
3092 if (infos[MESA_SHADER_VERTEX].vs.tcs_in_out_eq)
3093 infos[MESA_SHADER_VERTEX].vs.tcs_temp_only_input_mask =
3101 infos[MESA_SHADER_TESS_CTRL].vs.tcs_in_out_eq = infos[MESA_SHADER_VERTEX].vs.tcs_in_out_eq;
3102 infos[MESA_SHADER_TESS_CTRL].vs.tcs_temp_only_input_mask =
3103 infos[MESA_SHADER_VERTEX].vs.tcs_temp_only_input_mask;
3107 infos[s].workgroup_size =
3334 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
3426 radv_set_driver_locations(pipeline, nir, infos);
3444 gather_tess_info(device, nir, infos, pipeline_key);
3447 radv_fill_shader_info(pipeline, pipeline_layout, pStages, pipeline_key, infos, nir);
3449 bool pipeline_has_ngg = (nir[MESA_SHADER_VERTEX] && infos[MESA_SHADER_VERTEX].is_ngg) ||
3450 (nir[MESA_SHADER_TESS_EVAL] && infos[MESA_SHADER_TESS_EVAL].is_ngg);
3456 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
3458 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
3460 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
3462 gfx10_get_ngg_info(pipeline_key, pipeline, nir, infos, ngg_info);
3464 struct gfx9_gs_info *gs_info = &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
3466 gfx9_get_gs_info(pipeline_key, pipeline, nir, infos, gs_info);
3470 infos[hw_vs_api_stage].workgroup_size = infos[hw_vs_api_stage].wave_size;
3473 radv_determine_ngg_settings(pipeline, pipeline_key, infos, nir);
3480 assert(infos[i].wave_size && infos[i].workgroup_size);
3536 bool io_to_mem = radv_lower_io_to_mem(device, nir[i], &infos[i], pipeline_key);
3540 radv_lower_ngg(device, nir[i], &infos[i], pipeline_key);
3583 if (infos[MESA_SHADER_GEOMETRY].vs.outinfo.export_clip_dists)
3619 pipeline_key, infos + MESA_SHADER_FRAGMENT, keep_executable_info,
3634 &infos[MESA_SHADER_TESS_CTRL], keep_executable_info, keep_statistic_info,
3652 &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
3665 device, modules[i], &nir[i], 1, pipeline_layout, pipeline_key, infos + i,
Indexes created Thu Aug 20 00:25:57 UTC 2026