Lines Matching refs:qpu
37 #include "qpu/qpu_disasm.h"
158 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n);
161 if (!n->inst->qpu.sig.small_imm) {
163 state->last_rf[n->inst->qpu.raddr_b], n);
282 struct v3d_qpu_instr *inst = &qinst->qpu;
526 const struct v3d_qpu_instr *inst = &qinst->qpu;
566 const struct v3d_qpu_instr *inst = &qinst->qpu;
1030 if (prev_inst->inst->qpu.sig.thrsw)
1040 const struct v3d_qpu_instr *inst = &n->inst->qpu;
1145 if ((prev_inst->inst->qpu.sig.ldunifa ||
1146 prev_inst->inst->qpu.sig.ldunifarf) &&
1172 &prev_inst->inst->qpu, inst)) {
1224 if (chosen && chosen->inst->qpu.sig.ldvary) {
1298 v3d_qpu_dump(devinfo, &n->inst->qpu);
1308 v3d_qpu_dump(devinfo, &child->inst->qpu);
1359 const struct v3d_qpu_instr *before_inst = &before->inst->qpu;
1360 const struct v3d_qpu_instr *after_inst = &after->inst->qpu;
1452 update_scoreboard_for_chosen(scoreboard, &inst->qpu, c->devinfo);
1477 const struct v3d_qpu_instr *inst = &qinst->qpu;
1554 qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
1555 (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) ||
1556 v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) {
1560 if (slot > 0 && qinst->qpu.sig.ldvary)
1577 if (v3d_qpu_writes_unifa(c->devinfo, &qinst->qpu))
1605 if (qinst->qpu.sig.thrsw)
1618 if (qpu_inst_is_tlb(&qinst->qpu))
1624 if (qinst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH)
1637 if (v3d_qpu_writes_tmu(c->devinfo, &qinst->qpu) ||
1638 qinst->qpu.sig.wrtmuc) {
1647 if (v3d_qpu_waits_on_tmu(&qinst->qpu))
1653 if (v3d_qpu_writes_accum(c->devinfo, &qinst->qpu))
1659 if (qinst->qpu.alu.mul.op == V3D_QPU_M_MULTOP)
1665 if (v3d_qpu_writes_flags(&qinst->qpu))
1716 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
1717 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP);
1718 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP);
1736 struct v3d_qpu_sig sig = prev_inst->qpu.sig;
1756 merge_inst->qpu.sig.thrsw = true;
1779 second_inst->qpu.sig.thrsw = true;
1803 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH)
1806 if (inst->qpu.sig.thrsw)
1809 if (v3d_qpu_writes_unifa(c->devinfo, &inst->qpu))
1824 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);
1838 inst->qpu.branch.msfign == V3D_QPU_MSFIGN_NONE ||
1839 inst->qpu.branch.cond == V3D_QPU_BRANCH_COND_ALWAYS ||
1840 inst->qpu.branch.cond == V3D_QPU_BRANCH_COND_A0 ||
1841 inst->qpu.branch.cond == V3D_QPU_BRANCH_COND_NA0;
1854 assert(prev_inst->qpu.type != V3D_QPU_INSTR_TYPE_BRANCH);
1877 if (v3d_qpu_writes_flags(&prev_inst->qpu) &&
1878 inst->qpu.branch.cond != V3D_QPU_BRANCH_COND_ALWAYS) {
1888 if (prev_prev_inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
1889 prev_prev_inst->qpu.alu.add.op == V3D_QPU_A_SETMSF) {
2019 if (!prev || prev->qpu.type != V3D_QPU_INSTR_TYPE_ALU)
2022 if (prev->qpu.alu.add.op != V3D_QPU_A_NOP) {
2023 if (prev->qpu.alu.add.magic_write == ldvary_magic &&
2024 prev->qpu.alu.add.waddr == ldvary_index) {
2029 if (prev->qpu.alu.mul.op != V3D_QPU_M_NOP) {
2030 if (prev->qpu.alu.mul.magic_write == ldvary_magic &&
2031 prev->qpu.alu.mul.waddr == ldvary_index) {
2037 if (v3d_qpu_sig_writes_address(c->devinfo, &prev->qpu.sig))
2043 if (v3d_qpu_writes_flags(&prev->qpu))
2045 if (v3d_qpu_reads_flags(&prev->qpu))
2057 prev->qpu.sig.ldvary = true;
2058 prev->qpu.sig_magic = ldvary_magic;
2059 prev->qpu.sig_addr = ldvary_index;
2098 struct v3d_qpu_instr *inst = &qinst->qpu;
2130 inst, &merge->inst->qpu);
2139 v3d_qpu_dump(devinfo, &merge->inst->qpu);
2287 if (!v3d_qpu_is_nop(&inst->qpu))
2293 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH) {
2298 assert(branch && branch->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);
2310 branch->qpu.branch.offset =
2334 if (branch->qpu.branch.cond == V3D_QPU_BRANCH_COND_ALWAYS) {
2345 memcpy(&slot->qpu, &s_inst->qpu,
2346 sizeof(slot->qpu));
2351 branch->qpu.branch.offset +=
2392 v3d_qpu_dump(devinfo, &qinst->qpu);
2417 thrsw->qpu.sig.thrsw = true;