Lines Matching refs:regid
454 /* Represents half register in regid */
549 * + From the vert shader, we only need the output regid
565 uint8_t regid;
589 uint8_t regid;
879 uint8_t regid;
905 if (regid_ != regid(63, 0)) {
909 l->var[i].regid = regid_;
928 const unsigned default_regid = pack_vs_out ? regid(63, 0) : regid(0, 0);
962 ir3_link_add(l, k >= 0 ? vs->outputs[k].regid : default_regid,
973 uint32_t regid = so->outputs[j].regid;
975 regid |= HALF_REG_ID;
976 return regid;
978 return regid(63, 0);
995 return so->inputs[j].regid;
996 return regid(63, 0);