Lines Matching defs:iview
171 tu_cs_image_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
173 tu_cs_emit(cs, iview->PITCH);
174 tu_cs_emit(cs, iview->layer_size >> 6);
175 tu_cs_emit_qw(cs, iview->base_addr + iview->layer_size * layer);
179 tu_cs_image_stencil_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
181 tu_cs_emit(cs, iview->stencil_PITCH);
182 tu_cs_emit(cs, iview->stencil_layer_size >> 6);
183 tu_cs_emit_qw(cs, iview->stencil_base_addr + iview->stencil_layer_size * layer);
187 tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer, bool src)
189 tu_cs_emit_qw(cs, iview->base_addr + iview->layer_size * layer);
191 tu_cs_emit(cs, iview->PITCH << (src ? 9 : 0));
195 tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
197 tu_cs_emit_qw(cs, iview->ubwc_addr + iview->ubwc_layer_size * layer);
198 tu_cs_emit(cs, iview->FLAG_BUFFER_PITCH);
202 tu_image_view_init(struct tu_image_view *iview,
216 iview->image = image;
218 memset(iview->descriptor, 0, sizeof(iview->descriptor));
275 iview->descriptor[0] =
283 iview->descriptor[1] = A6XX_TEX_CONST_1_WIDTH(width) | A6XX_TEX_CONST_1_HEIGHT(height);
284 iview->descriptor[2] =
288 iview->descriptor[3] = A6XX_TEX_CONST_3_ARRAY_PITCH(layer_size);
289 iview->descriptor[4] = base_addr;
290 iview->descriptor[5] = (base_addr >> 32) | A6XX_TEX_CONST_5_DEPTH(depth);
293 iview->descriptor[3] |= A6XX_TEX_CONST_3_TILE_ALL;
301 iview->descriptor[0] |= A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X;
303 iview->descriptor[0] |= A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y;
308 iview->descriptor[3] |= A6XX_TEX_CONST_3_TILE_ALL;
310 iview->descriptor[3] |= A6XX_TEX_CONST_3_FLAG;
323 iview->descriptor[4] = base_addr[0];
324 iview->descriptor[5] |= base_addr[0] >> 32;
325 iview->descriptor[6] =
327 iview->descriptor[7] = base_addr[1];
328 iview->descriptor[8] = base_addr[1] >> 32;
329 iview->descriptor[9] = base_addr[2];
330 iview->descriptor[10] = base_addr[2] >> 32;
340 iview->descriptor[3] |= A6XX_TEX_CONST_3_FLAG;
341 iview->descriptor[7] = ubwc_addr;
342 iview->descriptor[8] = ubwc_addr >> 32;
343 iview->descriptor[9] |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
344 iview->descriptor[10] |=
351 iview->descriptor[3] |=
355 iview->SP_PS_2D_SRC_INFO = A6XX_SP_PS_2D_SRC_INFO(
367 iview->SP_PS_2D_SRC_SIZE =
371 iview->PITCH = A6XX_RB_DEPTH_BUFFER_PITCH(pitch).value;
372 iview->FLAG_BUFFER_PITCH = A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(
375 iview->base_addr = base_addr;
376 iview->ubwc_addr = ubwc_addr;
377 iview->layer_size = layer_size;
378 iview->ubwc_layer_size = layout->ubwc_layer_size;
392 memset(iview->storage_descriptor, 0, sizeof(iview->storage_descriptor));
394 iview->storage_descriptor[0] =
397 iview->storage_descriptor[1] =
400 iview->storage_descriptor[2] =
403 iview->storage_descriptor[3] = A6XX_IBO_3_ARRAY_PITCH(layer_size);
405 iview->storage_descriptor[4] = base_addr;
406 iview->storage_descriptor[5] = (base_addr >> 32) | A6XX_IBO_5_DEPTH(storage_depth);
409 iview->storage_descriptor[3] |= A6XX_IBO_3_FLAG | A6XX_IBO_3_UNK27;
410 iview->storage_descriptor[7] |= ubwc_addr;
411 iview->storage_descriptor[8] |= ubwc_addr >> 32;
412 iview->storage_descriptor[9] = A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
413 iview->storage_descriptor[10] =
417 iview->extent.width = width;
418 iview->extent.height = height;
419 iview->need_y2_align =
422 iview->ubwc_enabled = ubwc_enabled;
424 iview->RB_MRT_BUF_INFO = A6XX_RB_MRT_BUF_INFO(0,
429 iview->SP_FS_MRT_REG = A6XX_SP_FS_MRT_REG(0,
434 iview->RB_2D_DST_INFO = A6XX_RB_2D_DST_INFO(
441 iview->RB_BLIT_DST_INFO = A6XX_RB_BLIT_DST_INFO(
450 iview->stencil_base_addr = image->bo->iova + image->bo_offset +
452 iview->stencil_layer_size = fdl_layer_stride(layout, range->baseMipLevel);
453 iview->stencil_PITCH = A6XX_RB_STENCIL_BUFFER_PITCH(fdl_pitch(layout, range->baseMipLevel)).value;
837 TU_FROM_HANDLE(tu_image_view, iview, _iview);
839 if (!iview)
842 vk_object_free(&device->vk, pAllocator, iview);