Cross Reference: /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/genX

Lines Matching refs:GENX
219          anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
611    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
638    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
800    GENX(IA_VERTICES_COUNT_num),
801    GENX(IA_PRIMITIVES_COUNT_num),
802    GENX(VS_INVOCATION_COUNT_num),
803    GENX(GS_INVOCATION_COUNT_num),
804    GENX(GS_PRIMITIVES_COUNT_num),
805    GENX(CL_INVOCATION_COUNT_num),
806    GENX(CL_PRIMITIVES_COUNT_num),
807    GENX(PS_INVOCATION_COUNT_num),
808    GENX(HS_INVOCATION_COUNT_num),
809    GENX(DS_INVOCATION_COUNT_num),
810    GENX(CS_INVOCATION_COUNT_num),
831                mi_reg64(GENX(SO_NUM_PRIMS_WRITTEN0_num) + stream * 8));
833                mi_reg64(GENX(SO_PRIM_STORAGE_NEEDED0_num) + stream * 8));
854          anv_batch_emit(&cmd_buffer->batch, GENX(MI_REPORT_PERF_COUNT), rpc) {
910       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
926       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
984       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
999                                   GENX(MI_REPORT_PERF_COUNT_length),
1000                                   GENX(MI_REPORT_PERF_COUNT),
1005                                       GENX(MI_REPORT_PERF_COUNT_MemoryAddress_start) / 8);
1014                                GENX(MI_STORE_REGISTER_MEM_length),
1015                                GENX(MI_STORE_REGISTER_MEM),
1021                                       GENX(MI_STORE_REGISTER_MEM_MemoryAddress_start) / 8);
1025                                   GENX(MI_STORE_REGISTER_MEM_length),
1026                                   GENX(MI_STORE_REGISTER_MEM),
1032                                          GENX(MI_STORE_REGISTER_MEM_MemoryAddress_start) / 8);
1046       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1088       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1106       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1117       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1136                                   GENX(MI_REPORT_PERF_COUNT_length),
1137                                   GENX(MI_REPORT_PERF_COUNT),
1142                                       GENX(MI_REPORT_PERF_COUNT_MemoryAddress_start) / 8);
1151                                GENX(MI_STORE_REGISTER_MEM_length),
1152                                GENX(MI_STORE_REGISTER_MEM),
1158                                       GENX(MI_STORE_REGISTER_MEM_MemoryAddress_start) / 8);
1162                                   GENX(MI_STORE_REGISTER_MEM_length),
1163                                   GENX(MI_STORE_REGISTER_MEM),
1169                                          GENX(MI_STORE_REGISTER_MEM_MemoryAddress_start) / 8);
1181                          GENX(MI_STORE_DATA_IMM_length),
1182                          GENX(MI_STORE_DATA_IMM),
1187                                 GENX(MI_STORE_DATA_IMM_Address_start) / 8);
1195       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1252       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1302    anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {