Cross Reference: /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/genX

Lines Matching refs:GENX
89       unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;
95       struct GENX(SLICE_HASH_TABLE) table;
98       GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, &table);
101    anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
106    anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
130    anv_batch_emit(batch, GENX(3DSTATE_SUBSLICE_HASH_TABLE), p) {
148    anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), p) {
166    anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
175    anv_batch_write_reg(&batch, GENX(CACHE_MODE_1), cm1) {
185    anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
187    anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
197    anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
209    anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
218    anv_batch_write_reg(&batch, GENX(SAMPLER_MODE), sm) {
226    anv_batch_write_reg(&batch, GENX(HALF_SLICE_CHICKEN7), hsc7) {
231    anv_batch_write_reg(&batch, GENX(TCCNTLREG), tcc) {
245       anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) {
256    anv_batch_write_reg(&batch, GENX(CS_CHICKEN1), cc1) {
262 #define AA_LINE_QUALITY_REG GENX(3D_CHICKEN3)
264 #define AA_LINE_QUALITY_REG GENX(CHICKEN_RASTER_1)
280       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
281          lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
284       anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
285          lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;
298       anv_batch_write_reg(&batch, GENX(CS_DEBUG_MODE2), csdm2) {
303       anv_batch_write_reg(&batch, GENX(INSTPM), instpm) {
319    anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
365 #define L3_ALLOCATION_REG GENX(L3ALLOC)
366 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
368 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
369 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
425    anv_batch_write_reg(batch, GENX(L3SQCREG1), l3sqc) {
439    anv_batch_write_reg(batch, GENX(L3CNTLREG2), l3cr2) {
450    anv_batch_write_reg(batch, GENX(L3CNTLREG3), l3cr3) {
464       anv_batch_write_reg(batch, GENX(SCRATCH1), s1) {
467       anv_batch_write_reg(batch, GENX(CHICKEN3), c3) {
481    anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
541    anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
606    anv_batch_emit(batch, GENX(3DSTATE_CPS), cps) {
616          cps_states.map + GENX(CPS_STATE_length) * 4 * i;
617       struct GENX(CPS_STATE) cps_state = {
626       GENX(CPS_STATE_pack)(NULL, cps_state_dwords, &cps_state);
629    anv_batch_emit(batch, GENX(3DSTATE_CPS_POINTERS), cps) {
827       struct GENX(SAMPLER_STATE) sampler_state = {
885       GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
889                 sampler->state[p], GENX(SAMPLER_STATE_length) * 4);