Cross Reference: /xsrc/external/mit/MesaLib/dist/src/microsoft/compiler/dxil

Lines Matching defs:vec32
40 extract_comps_from_vec32(nir_builder *b, nir_ssa_def *vec32,
49    for (unsigned i = 0; i < vec32->num_components; i += step) {
52          tmp = nir_pack_64_2x32_split(b, nir_channel(b, vec32, i),
53                                          nir_channel(b, vec32, i + 1));
57          dst_comps[i] = nir_channel(b, vec32, i);
63          tmp = nir_unpack_bits(b, nir_channel(b, vec32, i), dst_bit_size);
144       nir_ssa_def *vec32 = build_load_ptr_dxil(b, path.path[0], idx);
148          vec32 = nir_vec2(b, vec32,
158          vec32 = nir_ushr(b, vec32, shift);
162       extract_comps_from_vec32(b, vec32, bit_size, &comps[comp_idx],
176 ubo_load_select_32b_comps(nir_builder *b, nir_ssa_def *vec32,
182    assert(vec32->num_components == 4);
186       return vec32;
192       comps[i] = nir_channel(b, vec32, i);
234       nir_ssa_def *vec32 =
237       /* First re-arrange the vec32 to account for intra 16-byte offset. */
238       vec32 = ubo_load_select_32b_comps(b, vec32, offset, subload_num_bits / 8);
247          vec32 = nir_ushr(b, vec32, shift);
251       extract_comps_from_vec32(b, vec32, bit_size, &comps[comp_idx],
290       nir_ssa_def *vec32 =
303          vec32 = nir_ushr(b, vec32, shift);
307       extract_comps_from_vec32(b, vec32, bit_size, &comps[comp_idx],
352       nir_ssa_def *vec32 = load_comps_to_vec32(b, bit_size, &comps[comp_idx],
367             vec32 = nir_ishl(b, vec32, shift);
373          store->src[0] = nir_src_for_ssa(vec32);
380          store->src[0] = nir_src_for_ssa(vec32);
446       nir_ssa_def *vec32 = nir_vec(b, &comps_32bit[i], num_vec32_comps);
455          vec32 = nir_ushr(b, vec32, shift);
460       extract_comps_from_vec32(b, vec32, bit_size, &comps[dest_index], num_dest_comps);
471 lower_store_vec32(nir_builder *b, nir_ssa_def *index, nir_ssa_def *vec32, nir_intrinsic_op op)
474    for (unsigned i = 0; i < vec32->num_components; i++) {
478       store->src[0] = nir_src_for_ssa(nir_channel(b, vec32, i));
487                          nir_ssa_def *vec32, unsigned num_bits, nir_intrinsic_op op)
499       vec32 = nir_ishl(b, vec32, shift);
505       nir_store_shared_masked_dxil(b, vec32, nir_inot(b, mask), index);
510       nir_ssa_def *new_val = nir_ior(b, vec32,
549       nir_ssa_def *vec32 = load_comps_to_vec32(b, bit_size, &comps[comp_idx],
557          lower_masked_store_vec32(b, local_offset, index, vec32, num_bits, op);
559          lower_store_vec32(b, index, vec32, op);