Lines Matching refs:ins
89 mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar)
91 bool integer = midgard_is_integer_op(ins->op);
92 unsigned base_size = max_bitsize_for_alu(ins);
93 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
97 mir_get_imod(ins->src_shift[i], ins->src_types[i], half, scalar) :
98 ((ins->src_abs[i] << 0) |
99 ((ins->src_neg[i] << 1)));
134 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
136 bool is_full = nir_alu_type_get_type_size(ins->dest_type) == 32;
138 bool half_0 = nir_alu_type_get_type_size(ins->src_types[0]) == 16;
139 bool half_1 = nir_alu_type_get_type_size(ins->src_types[1]) == 16;
140 unsigned comp = component_from_mask(ins->mask);
143 mir_pack_scalar_source(mir_pack_mod(ins, 0, true), !half_0, ins->swizzle[0][comp]),
144 mir_pack_scalar_source(mir_pack_mod(ins, 1, true), !half_1, ins->swizzle[1][comp])
167 if (ins->has_inline_constant) {
169 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
209 mir_pack_mask_alu(midgard_instruction *ins, midgard_vector_alu *alu)
211 unsigned effective = ins->mask;
217 unsigned inst_size = max_bitsize_for_alu(ins);
218 signed upper_shift = mir_upper_override(ins, inst_size);
331 mir_pack_vector_srcs(midgard_instruction *ins, midgard_vector_alu *alu)
333 bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props);
335 unsigned base_size = max_bitsize_for_alu(ins);
338 if (ins->has_inline_constant && (i == 1))
341 if (ins->src[i] == ~0)
344 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
348 unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
353 .mod = mir_pack_mod(ins, i, false),
368 mir_pack_swizzle_ldst(midgard_instruction *ins)
372 unsigned v = ins->swizzle[0][c];
377 ins->load_store.swizzle |= v << (2 * c);
384 mir_pack_swizzle_tex(midgard_instruction *ins)
390 unsigned v = ins->swizzle[i][c];
399 ins->texture.swizzle = packed;
401 ins->texture.in_reg_swizzle = packed;
426 midgard_instruction *ins = bundle->instructions[i];
428 mir_foreach_src(ins, s) {
429 if (ins->src[s] == dependency)
439 mir_pack_tex_ooo(midgard_block *block, midgard_bundle *bundle, midgard_instruction *ins)
444 if (!mir_can_run_ooo(block, bundle + count + 1, ins->dest))
448 ins->texture.out_of_order = count;
459 midgard_pack_common_store_mask(midgard_instruction *ins) {
460 unsigned comp_sz = nir_alu_type_get_type_size(ins->dest_type);
461 unsigned mask = ins->mask;
465 switch (ins->op) {
484 if (ins->op == midgard_op_st_128)
486 else if (ins->op == midgard_op_st_64)
514 mir_pack_ldst_mask(midgard_instruction *ins)
516 unsigned sz = nir_alu_type_get_type_size(ins->dest_type);
517 unsigned packed = ins->mask;
519 if (OP_IS_COMMON_STORE(ins->op)) {
520 packed = midgard_pack_common_store_mask(ins);
523 packed = ((ins->mask & 0x2) ? (0x8 | 0x4) : 0) |
524 ((ins->mask & 0x1) ? (0x2 | 0x1) : 0);
530 bool u = (ins->mask & (1 << (2*i + 0))) != 0;
531 ASSERTED bool v = (ins->mask & (1 << (2*i + 1))) != 0;
541 ins->load_store.mask = packed;
545 mir_lower_inverts(midgard_instruction *ins)
548 ins->src_invert[0],
549 ins->src_invert[1],
550 ins->src_invert[2]
553 switch (ins->op) {
559 ins->op = midgard_alu_op_inor;
561 ins->op = midgard_alu_op_iandnot;
569 ins->op = midgard_alu_op_inand;
571 ins->op = midgard_alu_op_iornot;
580 ins->op = midgard_alu_op_inxor;
592 mir_lower_roundmode(midgard_instruction *ins)
594 if (alu_opcode_props[ins->op].props & MIDGARD_ROUNDS) {
595 assert(ins->roundmode <= 0x3);
596 ins->op += ins->roundmode;
601 load_store_from_instr(midgard_instruction *ins)
603 midgard_load_store_word ldst = ins->load_store;
604 ldst.op = ins->op;
607 ldst.reg = SSA_REG_FROM_FIXED(ins->src[0]) & 1;
609 ldst.reg = SSA_REG_FROM_FIXED(ins->dest);
615 if (OP_IS_ATOMIC(ins->op)) {
617 ldst.swizzle |= ins->swizzle[3][0] & 3;
618 ldst.swizzle |= (SSA_REG_FROM_FIXED(ins->src[3]) & 1 ? 1 : 0) << 2;
621 if (ins->src[1] != ~0) {
622 ldst.arg_reg = SSA_REG_FROM_FIXED(ins->src[1]) - REGISTER_LDST_BASE;
623 unsigned sz = nir_alu_type_get_type_size(ins->src_types[1]);
624 ldst.arg_comp = midgard_ldst_comp(ldst.arg_reg, ins->swizzle[1][0], sz);
627 if (ins->src[2] != ~0) {
628 ldst.index_reg = SSA_REG_FROM_FIXED(ins->src[2]) - REGISTER_LDST_BASE;
629 unsigned sz = nir_alu_type_get_type_size(ins->src_types[2]);
630 ldst.index_comp = midgard_ldst_comp(ldst.index_reg, ins->swizzle[2][0], sz);
637 texture_word_from_instr(midgard_instruction *ins)
639 midgard_texture_word tex = ins->texture;
640 tex.op = ins->op;
642 unsigned src1 = ins->src[1] == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->src[1]);
645 unsigned dest = ins->dest == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->dest);
648 if (ins->src[2] != ~0) {
650 .select = SSA_REG_FROM_FIXED(ins->src[2]) & 1,
652 .component = ins->swizzle[2][0]
659 if (ins->src[3] != ~0) {
660 unsigned x = ins->swizzle[3][0];
667 unsigned offset_reg = SSA_REG_FROM_FIXED(ins->src[3]);
681 vector_alu_from_instr(midgard_instruction *ins)
684 .op = ins->op,
685 .outmod = ins->outmod,
686 .reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins))
689 if (ins->has_inline_constant) {
693 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
735 emit_branch(midgard_instruction *ins,
742 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
743 bool is_conditional = ins->branch.conditional;
744 bool is_inverted = ins->branch.invert_conditional;
745 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
746 bool is_tilebuf_wait = ins->branch.target_type == TARGET_TILEBUF_WAIT;
748 bool is_writeout = ins->writeout;
751 int target_number = ins->branch.target_block;
831 } else { /* `ins->compact_branch`, misnomer */
856 midgard_instruction *ins = bundle->instructions[i];
859 if (ins->compact_branch) continue;
862 if (ins->has_inline_constant)
863 src2_reg = ins->inline_constant >> 11;
864 else if (ins->src[1] != ~0)
865 src2_reg = SSA_REG_FROM_FIXED(ins->src[1]);
870 .src1_reg = (ins->src[0] == ~0 ?
872 SSA_REG_FROM_FIXED(ins->src[0])),
874 .src2_imm = ins->has_inline_constant,
875 .out_reg = (ins->dest == ~0 ?
877 SSA_REG_FROM_FIXED(ins->dest)),
885 midgard_instruction *ins = bundle->instructions[i];
887 if (!ins->compact_branch) {
888 mir_lower_inverts(ins);
889 mir_lower_roundmode(ins);
892 if (midgard_is_branch_unit(ins->unit)) {
893 emit_branch(ins, ctx, block, bundle, emission);
894 } else if (ins->unit & UNITS_ANY_VECTOR) {
895 midgard_vector_alu source = vector_alu_from_instr(ins);
896 mir_pack_mask_alu(ins, &source);
897 mir_pack_vector_srcs(ins, &source);
901 midgard_scalar_alu source = vector_to_scalar_alu(vector_alu_from_instr(ins), ins);
924 mir_ldst_pack_offset(midgard_instruction *ins, int offset)
927 assert(!OP_IS_REG2REG_LDST(ins->op) ||
928 ins->op == midgard_op_lea ||
929 ins->op == midgard_op_lea_image);
931 if (OP_IS_UBO_READ(ins->op))
932 ins->load_store.signed_offset |= PACK_LDST_UBO_OFS(offset);
933 else if (OP_IS_IMAGE(ins->op))
934 ins->load_store.signed_offset |= PACK_LDST_ATTRIB_OFS(offset);
935 else if (OP_IS_SPECIAL(ins->op))
936 ins->load_store.signed_offset |= PACK_LDST_SELECTOR_OFS(offset);
938 ins->load_store.signed_offset |= PACK_LDST_MEM_OFS(offset);
987 midgard_instruction *ins = bundle->instructions[i];
988 mir_pack_ldst_mask(ins);
991 if (!OP_IS_ATOMIC(ins->op))
992 mir_pack_swizzle_ldst(ins);
995 unsigned offset = ins->constants.u32[0];
997 mir_ldst_pack_offset(ins, offset);
1029 midgard_instruction *ins = bundle->instructions[0];
1031 ins->texture.type = bundle->tag;
1032 ins->texture.next_type = next_tag;
1035 if (ins->op == midgard_tex_op_barrier) {
1036 ins->texture.cont = ins->texture.last = 1;
1037 ins->texture.op = ins->op;
1038 util_dynarray_append(emission, midgard_texture_word, ins->texture);
1042 signed override = mir_upper_override(ins, 32);
1044 ins->texture.mask = override > 0 ?
1045 ins->mask >> override :
1046 ins->mask;
1048 mir_pack_swizzle_tex(ins);
1051 mir_pack_tex_ooo(block, bundle, ins);
1053 unsigned osz = nir_alu_type_get_type_size(ins->dest_type);
1054 unsigned isz = nir_alu_type_get_type_size(ins->src_types[1]);
1059 ins->texture.out_full = (osz == 32);
1060 ins->texture.out_upper = override > 0;
1061 ins->texture.in_reg_full = (isz == 32);
1062 ins->texture.sampler_type = midgard_sampler_type(ins->dest_type);
1063 ins->texture.outmod = ins->outmod;
1065 if (mir_op_computes_derivatives(ctx->stage, ins->op)) {
1066 ins->texture.cont = !ins->helper_terminate;
1067 ins->texture.last = ins->helper_terminate || ins->helper_execute;
1069 ins->texture.cont = ins->texture.last = 1;
1072 midgard_texture_word texture = texture_word_from_instr(ins);
Indexes created Sun Oct 25 00:26:45 UTC 2026