Lines Matching refs:ins
188 mir_foreach_instr_global(ctx, ins) {
189 switch (ins->type) {
191 mark_node_class(aluw, ins->dest);
192 mark_node_class(alur, ins->src[0]);
193 mark_node_class(alur, ins->src[1]);
194 mark_node_class(alur, ins->src[2]);
196 if (ins->compact_branch && ins->writeout)
197 mark_node_class(brar, ins->src[0]);
202 mark_node_class(aluw, ins->dest);
203 mark_node_class(ldst, ins->src[0]);
204 mark_node_class(ldst, ins->src[1]);
205 mark_node_class(ldst, ins->src[2]);
206 mark_node_class(ldst, ins->src[3]);
210 mark_node_class(texr, ins->src[0]);
211 mark_node_class(texr, ins->src[1]);
212 mark_node_class(texr, ins->src[2]);
213 mark_node_class(texw, ins->dest);
332 mir_foreach_instr_in_block_rev(block, ins) {
333 if (ins->writeout)
334 r1w = ins->dest;
341 mir_foreach_instr_global(ctx, ins) {
342 if (ins->dest < ctx->temp_count)
343 lcra_add_node_interference(l, ins->dest, mir_bytemask(ins), r1w, 0xF);
355 mir_foreach_instr_in_block_rev(blk, ins) {
359 unsigned dest = ins->dest;
364 unsigned mask = mir_bytemask(ins);
372 if (ins->compact_branch && ins->writeout) {
386 mir_liveness_ins_update(live, ins, ctx->temp_count);
394 mir_is_64(midgard_instruction *ins)
396 if (nir_alu_type_get_type_size(ins->dest_type) == 64)
399 mir_foreach_src(ins, v) {
400 if (nir_alu_type_get_type_size(ins->src_types[v]) == 64)
457 mir_foreach_instr_global(ctx, ins) {
464 if (ins->type == TAG_ALU_4 && mir_is_64(ins)) {
465 mir_foreach_src(ins, v) {
466 unsigned s = ins->src[v];
473 if (ins->type == TAG_LOAD_STORE_4 && OP_HAS_ADDRESS(ins->op)) {
474 mir_foreach_src(ins, v) {
475 unsigned s = ins->src[v];
476 unsigned size = nir_alu_type_get_type_size(ins->src_types[v]);
483 if (ins->dest >= SSA_FIXED_MINIMUM) continue;
485 unsigned size = nir_alu_type_get_type_size(ins->dest_type);
487 if (ins->is_pack)
491 int comps1 = util_logbase2(ins->mask);
498 int dest = ins->dest;
511 mir_foreach_src(ins, s) {
512 unsigned src_size = nir_alu_type_get_type_size(ins->src_types[s]);
513 if (src_size == 16 && ins->src[s] < SSA_FIXED_MINIMUM)
514 min_bound[ins->src[s]] = MAX2(min_bound[ins->src[s]], 8);
521 if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->op)) {
530 if (ins->type == TAG_LOAD_STORE_4)
551 mir_foreach_instr_global(ctx, ins) {
554 if (ins->type == TAG_LOAD_STORE_4) {
555 set_class(l->class, ins->src[0], REG_CLASS_LDST);
556 set_class(l->class, ins->src[1], REG_CLASS_LDST);
557 set_class(l->class, ins->src[2], REG_CLASS_LDST);
558 set_class(l->class, ins->src[3], REG_CLASS_LDST);
560 if (OP_IS_VEC4_ONLY(ins->op)) {
561 lcra_restrict_range(l, ins->dest, 16);
562 lcra_restrict_range(l, ins->src[0], 16);
563 lcra_restrict_range(l, ins->src[1], 16);
564 lcra_restrict_range(l, ins->src[2], 16);
565 lcra_restrict_range(l, ins->src[3], 16);
567 } else if (ins->type == TAG_TEXTURE_4) {
568 set_class(l->class, ins->dest, REG_CLASS_TEXW);
569 set_class(l->class, ins->src[0], REG_CLASS_TEXR);
570 set_class(l->class, ins->src[1], REG_CLASS_TEXR);
571 set_class(l->class, ins->src[2], REG_CLASS_TEXR);
572 set_class(l->class, ins->src[3], REG_CLASS_TEXR);
577 mir_foreach_instr_global(ctx, ins) {
578 assert(check_write_class(l->class, ins->type, ins->dest));
579 assert(check_read_class(l->class, ins->type, ins->src[0]));
580 assert(check_read_class(l->class, ins->type, ins->src[1]));
581 assert(check_read_class(l->class, ins->type, ins->src[2]));
582 assert(check_read_class(l->class, ins->type, ins->src[3]));
587 mir_foreach_instr_global(ctx, ins) {
588 if (!(ins->compact_branch && ins->writeout)) continue;
590 if (ins->src[0] < ctx->temp_count)
591 l->solutions[ins->src[0]] = 0;
593 if (ins->src[2] < ctx->temp_count)
594 l->solutions[ins->src[2]] = (16 * 1) + COMPONENT_X * 4;
596 if (ins->src[3] < ctx->temp_count)
597 l->solutions[ins->src[3]] = (16 * 1) + COMPONENT_Y * 4;
599 if (ins->src[1] < ctx->temp_count)
600 l->solutions[ins->src[1]] = (16 * 1) + COMPONENT_Z * 4;
602 if (ins->dest < ctx->temp_count)
603 l->solutions[ins->dest] = (16 * 1) + COMPONENT_W * 4;
637 midgard_instruction *ins = v->instructions[i];
639 if (ins->dest >= ctx->temp_count)
642 bool used_as_r1 = (br->dest == ins->dest);
645 used_as_r1 |= (s > 0) && (br->src[s] == ins->dest);
648 lcra_add_node_interference(l, ins->dest, mir_bytemask(ins), node_r1, 0xFFFF);
687 midgard_instruction *ins)
693 util_logbase2(nir_alu_type_get_type_size(ins->src_types[i]) / 8);
697 util_logbase2(nir_alu_type_get_type_size(ins->dest_type) / 8);
699 switch (ins->type) {
704 if (ins->compact_branch)
707 struct phys_reg src1 = index_to_reg(ctx, l, ins->src[0], src_shift[0]);
708 struct phys_reg src2 = index_to_reg(ctx, l, ins->src[1], src_shift[1]);
709 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, dest_shift);
711 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
714 GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props) ? 0 :
717 offset_swizzle(ins->swizzle[0], src1.offset, src1.shift, dest.shift, dest_offset);
718 if (!ins->has_inline_constant)
719 offset_swizzle(ins->swizzle[1], src2.offset, src2.shift, dest.shift, dest_offset);
720 if (ins->src[0] != ~0)
721 ins->src[0] = SSA_FIXED_REGISTER(src1.reg);
722 if (ins->src[1] != ~0)
723 ins->src[1] = SSA_FIXED_REGISTER(src2.reg);
724 if (ins->dest != ~0)
725 ins->dest = SSA_FIXED_REGISTER(dest.reg);
734 bool encodes_src = OP_IS_STORE(ins->op);
737 struct phys_reg src = index_to_reg(ctx, l, ins->src[0], src_shift[0]);
740 ins->src[0] = SSA_FIXED_REGISTER(src.reg);
741 offset_swizzle(ins->swizzle[0], src.offset, src.shift, 0, 0);
743 struct phys_reg dst = index_to_reg(ctx, l, ins->dest, dest_shift);
745 ins->dest = SSA_FIXED_REGISTER(dst.reg);
746 offset_swizzle(ins->swizzle[0], 0, 2, 2, dst.offset);
747 mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset);
753 unsigned src_index = ins->src[i];
758 ins->src[i] = SSA_FIXED_REGISTER(src.reg);
759 ins->swizzle[i][0] += component;
767 if (ins->op == midgard_tex_op_barrier)
771 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, dest_shift);
772 struct phys_reg coord = index_to_reg(ctx, l, ins->src[1], src_shift[1]);
773 struct phys_reg lod = index_to_reg(ctx, l, ins->src[2], src_shift[2]);
774 struct phys_reg offset = index_to_reg(ctx, l, ins->src[3], src_shift[3]);
777 if (ins->src[1] != ~0)
778 ins->src[1] = SSA_FIXED_REGISTER(coord.reg);
779 offset_swizzle(ins->swizzle[1], coord.offset, coord.shift, dest.shift, 0);
782 if (ins->dest != ~0)
783 ins->dest = SSA_FIXED_REGISTER(dest.reg);
784 offset_swizzle(ins->swizzle[0], 0, 2, dest.shift,
787 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
790 if (ins->src[2] != ~0) {
792 ins->src[2] = SSA_FIXED_REGISTER(lod.reg);
793 ins->swizzle[2][0] = lod.offset / 4;
797 if (ins->src[3] != ~0) {
798 ins->src[3] = SSA_FIXED_REGISTER(offset.reg);
799 ins->swizzle[3][0] = offset.offset / 4;
813 mir_foreach_instr_global(ctx, ins)
814 install_registers_instr(ctx, l, ins);
827 mir_foreach_instr_global(ctx, ins) {
828 if (ins->no_spill & (1 << l->spill_class)) {
829 lcra_set_node_spill_cost(l, ins->dest, -1);
832 mir_foreach_src(ins, s)
833 lcra_set_node_spill_cost(l, ins->src[s], -1);
872 mir_foreach_instr_global_safe(ctx, ins) {
873 read_bytemask |= mir_bytemask_of_read_components(ins, spill_node);
874 if (ins->dest == spill_node)
888 mir_foreach_instr_in_block_safe(block, ins) {
889 if (ins->dest != spill_node) continue;
900 st.mask = ins->mask;
901 st.dest_type = st.src_types[1] = ins->dest_type;
906 mir_insert_instruction_after_scheduled(ctx, block, ins, st);
910 if (write_count > 1 && mir_bytemask(ins) != 0xF) {
913 mir_insert_instruction_before_scheduled(ctx, block, ins, read);
916 ins->dest = dest;
917 ins->no_spill |= (1 << spill_class);
923 midgard_instruction *it = ins;
925 && (it->bundle_id == ins->bundle_id)) {
941 v_load_store_scratch(dest, spill_slot, true, ins->mask);
942 mir_insert_instruction_after_scheduled(ctx, block, ins, st);
945 midgard_instruction mv = v_mov(ins->dest, dest);
948 mir_insert_instruction_after_scheduled(ctx, block, ins, mv);
969 mir_foreach_instr_in_block(block, ins) {
972 if (ins->hint) continue;
975 if (!mir_has_arg(ins, spill_node)) continue;
982 midgard_instruction *before = ins;
1008 mir_rewrite_index_src_single(ins, spill_node, index);
1017 mir_foreach_instr_global(ctx, ins) {
1018 ins->hint = false;
1034 mir_foreach_instr_in_block(block, ins) {
1035 mir_foreach_src(ins, i) {
1036 if (ins->src[i] < min_demote || ins->src[i] >= max_demote)
1039 midgard_instruction *before = ins;
1042 unsigned idx = (23 - SSA_REG_FROM_FIXED(ins->src[i])) * 4;
1051 .dest_type = ins->src_types[i],
1066 mir_rewrite_index_src_single(ins, ins->src[i], temp);
Indexes created Sun Oct 25 00:26:45 UTC 2026