1 /* $NetBSD: sunxi_lcdc.c,v 1.16 2026/04/19 10:55:21 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_lcdc.c,v 1.16 2026/04/19 10:55:21 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/kernel.h> 38 #include <sys/systm.h> 39 40 #include <dev/fdt/fdt_port.h> 41 #include <dev/fdt/fdtvar.h> 42 43 #include <arm/sunxi/sunxi_drm.h> 44 45 #include <drm/drm_crtc_helper.h> 46 #include <drm/drm_drv.h> 47 #include <drm/drm_vblank.h> 48 49 #define TCON_GCTL_REG 0x000 50 #define TCON_GCTL_TCON_EN __BIT(31) 51 #define TCON_GCTL_GAMMA_EN __BIT(30) 52 #define TCON_GCTL_IO_MAP_SEL __BIT(0) 53 #define TCON_GINT0_REG 0x004 54 #define TCON_GINT0_TCON0_VB_INT_EN __BIT(31) 55 #define TCON_GINT0_TCON1_VB_INT_EN __BIT(30) 56 #define TCON_GINT0_TCON0_VB_INT_FLAG __BIT(15) 57 #define TCON_GINT0_TCON1_VB_INT_FLAG __BIT(14) 58 #define TCON_GINT1_REG 0x008 59 #define TCON_GINT1_TCON1_LINE_INT_NUM __BITS(11,0) 60 61 #define TCON0_CTL_REG 0x040 62 #define TCON0_CTL_TCON0_EN __BIT(31) 63 #define TCON0_CTL_START_DELAY __BITS(8,4) 64 #define TCON0_CTL_TCON0_SRC_SEL __BITS(2,0) 65 #define TCON0_DCLK_REG 0x044 66 #define TCON0_DCLK_EN __BITS(31,28) 67 #define TCON0_DCLK_DIV __BITS(6,0) 68 #define TCON0_BASIC0_REG 0x048 69 #define TCON0_BASIC1_REG 0x04c 70 #define TCON0_BASIC2_REG 0x050 71 #define TCON0_BASIC3_REG 0x054 72 #define TCON0_IO_POL_REG 0x088 73 #define TCON0_IO_POL_IO_OUTPUT_SEL __BIT(31) 74 #define TCON0_IO_POL_DCLK_SEL __BITS(30,28) 75 #define TCON0_IO_POL_IO3_INV __BIT(27) 76 #define TCON0_IO_POL_IO2_INV __BIT(26) 77 #define TCON0_IO_POL_IO1_INV __BIT(25) 78 #define TCON0_IO_POL_IO0_INV __BIT(24) 79 #define TCON0_IO_POL_DATA_INV __BITS(23,0) 80 #define TCON0_IO_TRI_REG 0x08c 81 82 #define TCON1_CTL_REG 0x090 83 #define TCON1_CTL_TCON1_EN __BIT(31) 84 #define TCON1_CTL_START_DELAY __BITS(8,4) 85 #define TCON1_CTL_TCON1_SRC_SEL __BITS(1,0) 86 #define TCON1_BASIC0_REG 0x094 87 #define TCON1_BASIC1_REG 0x098 88 #define TCON1_BASIC2_REG 0x09c 89 #define TCON1_BASIC3_REG 0x0a0 90 #define TCON1_BASIC4_REG 0x0a4 91 #define TCON1_BASIC5_REG 0x0a8 92 #define TCON1_IO_POL_REG 0x0f0 93 #define TCON1_IO_POL_IO3_INV __BIT(27) 94 #define TCON1_IO_POL_IO2_INV __BIT(26) 95 #define TCON1_IO_POL_IO1_INV __BIT(25) 96 #define TCON1_IO_POL_IO0_INV __BIT(24) 97 #define TCON1_IO_POL_DATA_INV __BITS(23,0) 98 #define TCON1_IO_TRI_REG 0x0f4 99 100 enum { 101 TCON_PORT_INPUT = 0, 102 TCON_PORT_OUTPUT = 1, 103 }; 104 105 enum tcon_type { 106 TYPE_TCON0, 107 TYPE_TCON1, 108 }; 109 110 static const struct device_compatible_entry compat_data[] = { 111 { .compat = "allwinner,sun8i-h3-tcon-tv", .value = TYPE_TCON1 }, 112 { .compat = "allwinner,sun8i-v3s-tcon", .value = TYPE_TCON0 }, 113 { .compat = "allwinner,sun50i-a64-tcon-lcd", .value = TYPE_TCON0 }, 114 { .compat = "allwinner,sun50i-a64-tcon-tv", .value = TYPE_TCON1 }, 115 DEVICE_COMPAT_EOL 116 }; 117 118 struct sunxi_lcdc_softc; 119 120 struct sunxi_lcdc_encoder { 121 struct drm_encoder base; 122 struct sunxi_lcdc_softc *sc; 123 struct drm_display_mode curmode; 124 }; 125 126 struct sunxi_lcdc_softc { 127 device_t sc_dev; 128 bus_space_tag_t sc_bst; 129 bus_space_handle_t sc_bsh; 130 int sc_phandle; 131 132 enum tcon_type sc_type; 133 134 struct clk *sc_clk_ch[2]; 135 136 struct sunxi_lcdc_encoder sc_encoder; 137 struct drm_connector sc_connector; 138 139 struct fdt_device_ports sc_ports; 140 }; 141 142 #define to_sunxi_lcdc_encoder(x) container_of(x, struct sunxi_lcdc_encoder, base) 143 144 #define TCON_READ(sc, reg) \ 145 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 146 #define TCON_WRITE(sc, reg, val) \ 147 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 148 149 static void 150 sunxi_lcdc_destroy(struct drm_encoder *encoder) 151 { 152 } 153 154 static const struct drm_encoder_funcs sunxi_lcdc_funcs = { 155 .destroy = sunxi_lcdc_destroy, 156 }; 157 158 static void 159 sunxi_lcdc_tcon_dpms(struct drm_encoder *encoder, int mode) 160 { 161 } 162 163 static bool 164 sunxi_lcdc_tcon_mode_fixup(struct drm_encoder *encoder, 165 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 166 { 167 return true; 168 } 169 170 static void 171 sunxi_lcdc_tcon_mode_set(struct drm_encoder *encoder, 172 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 173 { 174 struct sunxi_lcdc_encoder *lcdc_encoder = to_sunxi_lcdc_encoder(encoder); 175 176 lcdc_encoder->curmode = *adjusted_mode; 177 } 178 179 static void 180 sunxi_lcdc_tcon0_prepare(struct drm_encoder *encoder) 181 { 182 struct sunxi_lcdc_encoder *lcdc_encoder = to_sunxi_lcdc_encoder(encoder); 183 struct sunxi_lcdc_softc * const sc = lcdc_encoder->sc; 184 uint32_t val; 185 186 val = TCON_READ(sc, TCON_GCTL_REG); 187 val |= TCON_GCTL_TCON_EN; 188 val &= ~TCON_GCTL_IO_MAP_SEL; 189 TCON_WRITE(sc, TCON_GCTL_REG, val); 190 191 TCON_WRITE(sc, TCON0_IO_TRI_REG, 0); 192 } 193 194 static void 195 sunxi_lcdc_tcon1_prepare(struct drm_encoder *encoder) 196 { 197 struct sunxi_lcdc_encoder *lcdc_encoder = to_sunxi_lcdc_encoder(encoder); 198 struct sunxi_lcdc_softc * const sc = lcdc_encoder->sc; 199 uint32_t val; 200 201 val = TCON_READ(sc, TCON_GCTL_REG); 202 val |= TCON_GCTL_TCON_EN; 203 TCON_WRITE(sc, TCON_GCTL_REG, val); 204 205 TCON_WRITE(sc, TCON1_IO_POL_REG, 0); 206 TCON_WRITE(sc, TCON1_IO_TRI_REG, 0xffffffff); 207 } 208 209 static void 210 sunxi_lcdc_tcon0_commit(struct drm_encoder *encoder) 211 { 212 struct sunxi_lcdc_encoder *lcdc_encoder = to_sunxi_lcdc_encoder(encoder); 213 struct sunxi_lcdc_softc * const sc = lcdc_encoder->sc; 214 struct drm_display_mode *mode = &lcdc_encoder->curmode; 215 uint32_t val; 216 int error; 217 218 const u_int interlace_p = (mode->flags & DRM_MODE_FLAG_INTERLACE) != 0; 219 const u_int hspw = mode->crtc_hsync_end - mode->crtc_hsync_start; 220 const u_int hbp = mode->crtc_htotal - mode->crtc_hsync_start; 221 const u_int vspw = mode->crtc_vsync_end - mode->crtc_vsync_start; 222 const u_int vbp = mode->crtc_vtotal - mode->crtc_vsync_start; 223 const u_int vblank_len = (mode->crtc_vtotal - mode->crtc_vdisplay) >> interlace_p; 224 const u_int start_delay = uimin(vblank_len, 30); 225 226 val = TCON0_CTL_TCON0_EN | 227 __SHIFTIN(start_delay, TCON0_CTL_START_DELAY); 228 TCON_WRITE(sc, TCON0_CTL_REG, val); 229 230 TCON_WRITE(sc, TCON0_BASIC0_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1)); 231 TCON_WRITE(sc, TCON0_BASIC1_REG, ((mode->crtc_htotal - 1) << 16) | (hbp - 1)); 232 TCON_WRITE(sc, TCON0_BASIC2_REG, ((mode->crtc_vtotal * 2) << 16) | (vbp - 1)); 233 TCON_WRITE(sc, TCON0_BASIC3_REG, ((hspw - 1) << 16) | (vspw - 1)); 234 235 val = TCON_READ(sc, TCON0_IO_POL_REG); 236 val &= ~(TCON0_IO_POL_IO3_INV|TCON0_IO_POL_IO2_INV| 237 TCON0_IO_POL_IO1_INV|TCON0_IO_POL_IO0_INV| 238 TCON0_IO_POL_DATA_INV); 239 if ((mode->flags & DRM_MODE_FLAG_PHSYNC) == 0) 240 val |= TCON0_IO_POL_IO1_INV; 241 if ((mode->flags & DRM_MODE_FLAG_PVSYNC) == 0) 242 val |= TCON0_IO_POL_IO0_INV; 243 TCON_WRITE(sc, TCON0_IO_POL_REG, val); 244 245 if (sc->sc_clk_ch[0] != NULL) { 246 error = clk_set_rate(sc->sc_clk_ch[0], mode->crtc_clock * 1000); 247 if (error != 0) { 248 device_printf(sc->sc_dev, "failed to set CH0 PLL rate to %u Hz: %d\n", 249 mode->crtc_clock * 1000, error); 250 return; 251 } 252 error = clk_enable(sc->sc_clk_ch[0]); 253 if (error != 0) { 254 device_printf(sc->sc_dev, "failed to enable CH0 PLL: %d\n", error); 255 return; 256 } 257 } else { 258 device_printf(sc->sc_dev, "no CH0 PLL configured\n"); 259 } 260 } 261 262 static void 263 sunxi_lcdc_tcon1_commit(struct drm_encoder *encoder) 264 { 265 struct sunxi_lcdc_encoder *lcdc_encoder = to_sunxi_lcdc_encoder(encoder); 266 struct sunxi_lcdc_softc * const sc = lcdc_encoder->sc; 267 struct drm_display_mode *mode = &lcdc_encoder->curmode; 268 uint32_t val; 269 int error; 270 271 const u_int interlace_p = (mode->flags & DRM_MODE_FLAG_INTERLACE) != 0; 272 const u_int hspw = mode->crtc_hsync_end - mode->crtc_hsync_start; 273 const u_int hbp = mode->crtc_htotal - mode->crtc_hsync_start; 274 const u_int vspw = mode->crtc_vsync_end - mode->crtc_vsync_start; 275 const u_int vbp = mode->crtc_vtotal - mode->crtc_vsync_start; 276 const u_int vblank_len = ((mode->crtc_vtotal - mode->crtc_vdisplay) >> interlace_p) - 2; 277 const u_int start_delay = uimin(vblank_len, 30); 278 279 val = TCON1_CTL_TCON1_EN | 280 __SHIFTIN(start_delay, TCON1_CTL_START_DELAY); 281 TCON_WRITE(sc, TCON1_CTL_REG, val); 282 283 TCON_WRITE(sc, TCON1_BASIC0_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1)); 284 TCON_WRITE(sc, TCON1_BASIC1_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1)); 285 TCON_WRITE(sc, TCON1_BASIC2_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1)); 286 TCON_WRITE(sc, TCON1_BASIC3_REG, ((mode->crtc_htotal - 1) << 16) | (hbp - 1)); 287 TCON_WRITE(sc, TCON1_BASIC4_REG, ((mode->crtc_vtotal * 2) << 16) | (vbp - 1)); 288 TCON_WRITE(sc, TCON1_BASIC5_REG, ((hspw - 1) << 16) | (vspw - 1)); 289 290 TCON_WRITE(sc, TCON_GINT1_REG, 291 __SHIFTIN(start_delay + 2, TCON_GINT1_TCON1_LINE_INT_NUM)); 292 293 if (sc->sc_clk_ch[1] != NULL) { 294 error = clk_set_rate(sc->sc_clk_ch[1], mode->crtc_clock * 1000); 295 if (error != 0) { 296 device_printf(sc->sc_dev, "failed to set CH1 PLL rate to %u Hz: %d\n", 297 mode->crtc_clock * 1000, error); 298 return; 299 } 300 error = clk_enable(sc->sc_clk_ch[1]); 301 if (error != 0) { 302 device_printf(sc->sc_dev, "failed to enable CH1 PLL: %d\n", error); 303 return; 304 } 305 } else { 306 device_printf(sc->sc_dev, "no CH1 PLL configured\n"); 307 } 308 } 309 310 static const struct drm_encoder_helper_funcs sunxi_lcdc_tcon0_helper_funcs = { 311 .dpms = sunxi_lcdc_tcon_dpms, 312 .mode_fixup = sunxi_lcdc_tcon_mode_fixup, 313 .prepare = sunxi_lcdc_tcon0_prepare, 314 .commit = sunxi_lcdc_tcon0_commit, 315 .mode_set = sunxi_lcdc_tcon_mode_set, 316 }; 317 318 static const struct drm_encoder_helper_funcs sunxi_lcdc_tcon1_helper_funcs = { 319 .dpms = sunxi_lcdc_tcon_dpms, 320 .mode_fixup = sunxi_lcdc_tcon_mode_fixup, 321 .prepare = sunxi_lcdc_tcon1_prepare, 322 .commit = sunxi_lcdc_tcon1_commit, 323 .mode_set = sunxi_lcdc_tcon_mode_set, 324 }; 325 326 static int 327 sunxi_lcdc_encoder_mode(struct fdt_endpoint *out_ep) 328 { 329 struct fdt_endpoint *remote_ep = fdt_endpoint_remote(out_ep); 330 331 if (remote_ep == NULL) 332 return DRM_MODE_ENCODER_NONE; 333 334 switch (fdt_endpoint_type(remote_ep)) { 335 case EP_DRM_BRIDGE: 336 return DRM_MODE_ENCODER_TMDS; 337 case EP_DRM_PANEL: 338 return DRM_MODE_ENCODER_LVDS; 339 default: 340 return DRM_MODE_ENCODER_NONE; 341 } 342 } 343 344 static void 345 sunxi_lcdc_enable_vblank(void *priv) 346 { 347 struct sunxi_lcdc_softc * const sc = priv; 348 const int crtc_index = ffs32(sc->sc_encoder.base.possible_crtcs) - 1; 349 350 if (crtc_index == 0) 351 TCON_WRITE(sc, TCON_GINT0_REG, TCON_GINT0_TCON0_VB_INT_EN); 352 else 353 TCON_WRITE(sc, TCON_GINT0_REG, TCON_GINT0_TCON1_VB_INT_EN); 354 } 355 356 static void 357 sunxi_lcdc_disable_vblank(void *priv) 358 { 359 struct sunxi_lcdc_softc * const sc = priv; 360 361 TCON_WRITE(sc, TCON_GINT0_REG, 0); 362 } 363 364 static void 365 sunxi_lcdc_setup_vblank(struct sunxi_lcdc_softc *sc) 366 { 367 const int crtc_index = ffs32(sc->sc_encoder.base.possible_crtcs) - 1; 368 struct drm_device *ddev = sc->sc_encoder.base.dev; 369 struct sunxi_drm_softc *drm_sc; 370 371 KASSERT(ddev != NULL); 372 373 drm_sc = device_private(ddev->dev); 374 drm_sc->sc_vbl[crtc_index].priv = sc; 375 drm_sc->sc_vbl[crtc_index].enable_vblank = sunxi_lcdc_enable_vblank; 376 drm_sc->sc_vbl[crtc_index].disable_vblank = sunxi_lcdc_disable_vblank; 377 } 378 379 static int 380 sunxi_lcdc_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 381 { 382 struct sunxi_lcdc_softc * const sc = device_private(dev); 383 struct fdt_endpoint *in_ep = fdt_endpoint_remote(ep); 384 struct fdt_endpoint *out_ep; 385 struct drm_crtc *crtc; 386 387 if (!activate) 388 return EINVAL; 389 390 if (fdt_endpoint_port_index(ep) != TCON_PORT_INPUT) 391 return EINVAL; 392 393 if (fdt_endpoint_type(in_ep) != EP_DRM_CRTC) 394 return EINVAL; 395 396 crtc = fdt_endpoint_get_data(in_ep); 397 398 sc->sc_encoder.sc = sc; 399 sc->sc_encoder.base.possible_crtcs = 1 << drm_crtc_index(crtc); 400 401 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, TCON_PORT_OUTPUT, 0); 402 if (out_ep != NULL) { 403 drm_encoder_init(crtc->dev, &sc->sc_encoder.base, &sunxi_lcdc_funcs, 404 sunxi_lcdc_encoder_mode(out_ep), NULL); 405 drm_encoder_helper_add(&sc->sc_encoder.base, &sunxi_lcdc_tcon0_helper_funcs); 406 407 sunxi_lcdc_setup_vblank(sc); 408 409 return fdt_endpoint_activate(out_ep, activate); 410 } 411 412 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, TCON_PORT_OUTPUT, 1); 413 if (out_ep != NULL) { 414 drm_encoder_init(crtc->dev, &sc->sc_encoder.base, &sunxi_lcdc_funcs, 415 sunxi_lcdc_encoder_mode(out_ep), NULL); 416 drm_encoder_helper_add(&sc->sc_encoder.base, &sunxi_lcdc_tcon1_helper_funcs); 417 418 sunxi_lcdc_setup_vblank(sc); 419 420 return fdt_endpoint_activate(out_ep, activate); 421 } 422 423 return ENXIO; 424 } 425 426 static void * 427 sunxi_lcdc_ep_get_data(device_t dev, struct fdt_endpoint *ep) 428 { 429 struct sunxi_lcdc_softc * const sc = device_private(dev); 430 431 return &sc->sc_encoder; 432 } 433 434 static int 435 sunxi_lcdc_intr(void *priv) 436 { 437 struct sunxi_lcdc_softc * const sc = priv; 438 struct drm_device *ddev = sc->sc_encoder.base.dev; 439 struct sunxi_drm_softc *drm_sc = device_private(ddev->dev); 440 uint32_t val; 441 int rv = 0; 442 443 const int crtc_index = ffs32(sc->sc_encoder.base.possible_crtcs) - 1; 444 const uint32_t status_mask = crtc_index == 0 ? 445 TCON_GINT0_TCON0_VB_INT_FLAG : TCON_GINT0_TCON1_VB_INT_FLAG; 446 447 val = TCON_READ(sc, TCON_GINT0_REG); 448 if ((val & status_mask) != 0) { 449 struct drm_crtc *crtc = drm_sc->sc_vbl[crtc_index].crtc; 450 451 TCON_WRITE(sc, TCON_GINT0_REG, val & ~status_mask); 452 if (crtc != NULL) { 453 drm_crtc_handle_vblank(crtc); 454 spin_lock(&ddev->event_lock); 455 if (drm_sc->sc_vbl[crtc_index].event != NULL) { 456 drm_crtc_send_vblank_event(crtc, 457 drm_sc->sc_vbl[crtc_index].event); 458 drm_sc->sc_vbl[crtc_index].event = NULL; 459 drm_crtc_vblank_put(crtc); 460 } 461 spin_unlock(&ddev->event_lock); 462 } else { 463 device_printf(sc->sc_dev, 464 "vblank interrupt and no crtc for index %u\n", 465 crtc_index); 466 } 467 rv = 1; 468 } 469 470 return rv; 471 } 472 473 static int 474 sunxi_lcdc_match(device_t parent, cfdata_t cf, void *aux) 475 { 476 struct fdt_attach_args * const faa = aux; 477 478 return of_compatible_match(faa->faa_phandle, compat_data); 479 } 480 481 static void 482 sunxi_lcdc_attach(device_t parent, device_t self, void *aux) 483 { 484 struct sunxi_lcdc_softc * const sc = device_private(self); 485 struct fdt_attach_args * const faa = aux; 486 const int phandle = faa->faa_phandle; 487 struct fdtbus_reset *rst; 488 char intrstr[128]; 489 struct clk *clk; 490 bus_addr_t addr; 491 bus_size_t size; 492 void *ih; 493 494 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 495 aprint_error(": couldn't get registers\n"); 496 return; 497 } 498 499 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 500 aprint_error(": couldn't decode interrupt\n"); 501 return; 502 } 503 504 rst = fdtbus_reset_get(phandle, "lcd"); 505 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) { 506 aprint_error(": couldn't de-assert reset\n"); 507 return; 508 } 509 510 clk = fdtbus_clock_get(phandle, "ahb"); 511 if (clk == NULL || clk_enable(clk) != 0) { 512 aprint_error(": couldn't enable bus clock\n"); 513 return; 514 } 515 516 sc->sc_dev = self; 517 sc->sc_bst = faa->faa_bst; 518 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 519 aprint_error(": couldn't map registers\n"); 520 return; 521 } 522 sc->sc_phandle = faa->faa_phandle; 523 sc->sc_type = of_compatible_lookup(phandle, compat_data)->value; 524 sc->sc_clk_ch[0] = fdtbus_clock_get(phandle, "tcon-ch0"); 525 sc->sc_clk_ch[1] = fdtbus_clock_get(phandle, "tcon-ch1"); 526 527 aprint_naive("\n"); 528 switch (sc->sc_type) { 529 case TYPE_TCON0: 530 aprint_normal(": TCON0\n"); 531 break; 532 case TYPE_TCON1: 533 aprint_normal(": TCON1\n"); 534 break; 535 } 536 537 sc->sc_ports.dp_ep_activate = sunxi_lcdc_ep_activate; 538 sc->sc_ports.dp_ep_get_data = sunxi_lcdc_ep_get_data; 539 fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_ENCODER); 540 541 ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 542 sunxi_lcdc_intr, sc, device_xname(self)); 543 if (ih == NULL) { 544 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 545 intrstr); 546 return; 547 } 548 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 549 } 550 551 CFATTACH_DECL_NEW(sunxi_lcdc, sizeof(struct sunxi_lcdc_softc), 552 sunxi_lcdc_match, sunxi_lcdc_attach, NULL, NULL); 553
Indexes created Sun Oct 25 00:26:45 UTC 2026