1 /* $NetBSD: rtl8169.c,v 1.185 2026/09/26 00:48:28 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.185 2026/09/26 00:48:28 tsutsui Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul (at) windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * six devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168 and the RTL8111. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 115 #include <sys/param.h> 116 #include <sys/cprng.h> 117 #include <sys/endian.h> 118 #include <sys/systm.h> 119 #include <sys/sockio.h> 120 #include <sys/mbuf.h> 121 #include <sys/kernel.h> 122 #include <sys/socket.h> 123 #include <sys/device.h> 124 125 #include <net/if.h> 126 #include <net/if_arp.h> 127 #include <net/if_dl.h> 128 #include <net/if_ether.h> 129 #include <net/if_media.h> 130 #include <net/if_vlanvar.h> 131 132 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 133 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 134 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 135 136 #include <net/bpf.h> 137 #include <sys/rndsource.h> 138 139 #include <sys/bus.h> 140 141 #include <dev/mii/mii.h> 142 #include <dev/mii/miivar.h> 143 144 #include <dev/ic/rtl81x9reg.h> 145 #include <dev/ic/rtl81x9var.h> 146 147 #include <dev/ic/rtl8169var.h> 148 149 #define RE_LOCK(sc) mutex_enter(&(sc)->sc_lock) 150 #define RE_UNLOCK(sc) mutex_exit(&(sc)->sc_lock) 151 #define RE_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_lock)) 152 153 #define ETHER_IS_ZERO(addr) \ 154 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 155 156 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 157 158 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 159 static int re_rx_list_init(struct rtk_softc *); 160 static int re_tx_list_init(struct rtk_softc *); 161 static void re_rxeof(struct rtk_softc *); 162 static void re_txeof(struct rtk_softc *); 163 static void re_tick(void *); 164 static void re_tick_locked(struct rtk_softc *); 165 static void re_start(struct ifnet *); 166 static void re_start_locked(struct rtk_softc *); 167 static int re_ioctl(struct ifnet *, u_long, void *); 168 static int re_ifflags_cb(struct ethercom *); 169 static int re_init(struct ifnet *); 170 static int re_init_locked(struct rtk_softc *); 171 static void re_stop(struct ifnet *, int); 172 static void re_stop_locked(struct rtk_softc *, int); 173 static void re_watchdog(struct ifnet *); 174 175 static int re_enable(struct rtk_softc *); 176 static void re_disable(struct rtk_softc *); 177 178 static int re_gmii_readreg(device_t, int, int, uint16_t *); 179 static int re_gmii_writereg(device_t, int, int, uint16_t); 180 181 static int re_miibus_readreg(device_t, int, int, uint16_t *); 182 static int re_miibus_writereg(device_t, int, int, uint16_t); 183 static void re_miibus_statchg(struct ifnet *); 184 185 static void re_reset(struct rtk_softc *); 186 187 static const struct re_revision { 188 uint32_t re_chipid; 189 const char *re_name; 190 } re_revisions[] = { 191 { RTK_HWREV_8100, "RTL8100" }, 192 { RTK_HWREV_8100E, "RTL8100E" }, 193 { RTK_HWREV_8100E_SPIN2, "RTL8100E 2" }, 194 { RTK_HWREV_8101, "RTL8101" }, 195 { RTK_HWREV_8101E, "RTL8101E" }, 196 { RTK_HWREV_8102E, "RTL8102E" }, 197 { RTK_HWREV_8106E, "RTL8106E" }, 198 { RTK_HWREV_8401E, "RTL8401E" }, 199 { RTK_HWREV_8402, "RTL8402" }, 200 { RTK_HWREV_8411, "RTL8411" }, 201 { RTK_HWREV_8411B, "RTL8411B" }, 202 { RTK_HWREV_8102EL, "RTL8102EL" }, 203 { RTK_HWREV_8102EL_SPIN1, "RTL8102EL 1" }, 204 { RTK_HWREV_8103E, "RTL8103E" }, 205 { RTK_HWREV_8110S, "RTL8110S" }, 206 { RTK_HWREV_8139CPLUS, "RTL8139C+" }, 207 { RTK_HWREV_8168B_SPIN1, "RTL8168 1" }, 208 { RTK_HWREV_8168B_SPIN2, "RTL8168 2" }, 209 { RTK_HWREV_8168B_SPIN3, "RTL8168 3" }, 210 { RTK_HWREV_8168C, "RTL8168C/8111C" }, 211 { RTK_HWREV_8168C_SPIN2, "RTL8168C/8111C" }, 212 { RTK_HWREV_8168CP, "RTL8168CP/8111CP" }, 213 { RTK_HWREV_8168F, "RTL8168F/8111F" }, 214 { RTK_HWREV_8168G, "RTL8168G/8111G" }, 215 { RTK_HWREV_8168GU, "RTL8168GU/8111GU" }, 216 { RTK_HWREV_8168H, "RTL8168H/8111H" }, 217 { RTK_HWREV_8105E, "RTL8105E" }, 218 { RTK_HWREV_8105E_SPIN1, "RTL8105E" }, 219 { RTK_HWREV_8168D, "RTL8168D/8111D" }, 220 { RTK_HWREV_8168DP, "RTL8168DP/8111DP" }, 221 { RTK_HWREV_8168E, "RTL8168E/8111E" }, 222 { RTK_HWREV_8168E_VL, "RTL8168E/8111E-VL" }, 223 { RTK_HWREV_8168EP, "RTL8168EP/8111EP" }, 224 { RTK_HWREV_8168FP, "RTL8168FP/8117" }, 225 { RTK_HWREV_8169, "RTL8169" }, 226 { RTK_HWREV_8169_8110SB, "RTL8169/8110SB" }, 227 { RTK_HWREV_8169_8110SBL, "RTL8169SBL" }, 228 { RTK_HWREV_8169_8110SC, "RTL8169/8110SCd" }, 229 { RTK_HWREV_8169_8110SCE, "RTL8169/8110SCe" }, 230 { RTK_HWREV_8169S, "RTL8169S" }, 231 232 { 0, NULL } 233 }; 234 235 static inline void 236 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 237 { 238 239 d->re_bufaddr_lo = htole32(RE_ADDR_LO(addr)); 240 d->re_bufaddr_hi = htole32(RE_ADDR_HI(addr)); 241 } 242 243 static int 244 re_gmii_readreg(device_t dev, int phy, int reg, uint16_t *val) 245 { 246 struct rtk_softc *sc = device_private(dev); 247 uint32_t data; 248 int i; 249 250 if (phy != 7) 251 return -1; 252 253 /* Let the rgephy driver read the GMEDIASTAT register */ 254 255 if (reg == RTK_GMEDIASTAT) { 256 *val = CSR_READ_1(sc, RTK_GMEDIASTAT); 257 return 0; 258 } 259 260 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 261 DELAY(1000); 262 263 for (i = 0; i < RTK_TIMEOUT; i++) { 264 data = CSR_READ_4(sc, RTK_PHYAR); 265 if (data & RTK_PHYAR_BUSY) 266 break; 267 DELAY(100); 268 } 269 270 if (i == RTK_TIMEOUT) { 271 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 272 return ETIMEDOUT; 273 } 274 275 *val = data & RTK_PHYAR_PHYDATA; 276 return 0; 277 } 278 279 static int 280 re_gmii_writereg(device_t dev, int phy, int reg, uint16_t val) 281 { 282 struct rtk_softc *sc = device_private(dev); 283 uint32_t data; 284 int i; 285 286 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 287 (val & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 288 DELAY(1000); 289 290 for (i = 0; i < RTK_TIMEOUT; i++) { 291 data = CSR_READ_4(sc, RTK_PHYAR); 292 if (!(data & RTK_PHYAR_BUSY)) 293 break; 294 DELAY(100); 295 } 296 297 if (i == RTK_TIMEOUT) { 298 printf("%s: PHY write reg %x <- %hx failed\n", 299 device_xname(sc->sc_dev), reg, val); 300 return ETIMEDOUT; 301 } 302 303 return 0; 304 } 305 306 static int 307 re_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 308 { 309 struct rtk_softc *sc = device_private(dev); 310 uint16_t re8139_reg = 0; 311 int rv = 0; 312 313 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 314 rv = re_gmii_readreg(dev, phy, reg, val); 315 return rv; 316 } 317 318 /* Pretend the internal PHY is only at address 0 */ 319 if (phy) { 320 return -1; 321 } 322 switch (reg) { 323 case MII_BMCR: 324 re8139_reg = RTK_BMCR; 325 break; 326 case MII_BMSR: 327 re8139_reg = RTK_BMSR; 328 break; 329 case MII_ANAR: 330 re8139_reg = RTK_ANAR; 331 break; 332 case MII_ANER: 333 re8139_reg = RTK_ANER; 334 break; 335 case MII_ANLPAR: 336 re8139_reg = RTK_LPAR; 337 break; 338 case MII_PHYIDR1: 339 case MII_PHYIDR2: 340 *val = 0; 341 return 0; 342 /* 343 * Allow the rlphy driver to read the media status 344 * register. If we have a link partner which does not 345 * support NWAY, this is the register which will tell 346 * us the results of parallel detection. 347 */ 348 case RTK_MEDIASTAT: 349 *val = CSR_READ_1(sc, RTK_MEDIASTAT); 350 return 0; 351 default: 352 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 353 return -1; 354 } 355 *val = CSR_READ_2(sc, re8139_reg); 356 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 357 /* 8139C+ has different bit layout. */ 358 *val &= ~(BMCR_LOOP | BMCR_ISO); 359 } 360 return 0; 361 } 362 363 static int 364 re_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 365 { 366 struct rtk_softc *sc = device_private(dev); 367 uint16_t re8139_reg = 0; 368 int rv; 369 370 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 371 rv = re_gmii_writereg(dev, phy, reg, val); 372 return rv; 373 } 374 375 /* Pretend the internal PHY is only at address 0 */ 376 if (phy) { 377 return -1; 378 } 379 switch (reg) { 380 case MII_BMCR: 381 re8139_reg = RTK_BMCR; 382 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 383 /* 8139C+ has different bit layout. */ 384 val &= ~(BMCR_LOOP | BMCR_ISO); 385 } 386 break; 387 case MII_BMSR: 388 re8139_reg = RTK_BMSR; 389 break; 390 case MII_ANAR: 391 re8139_reg = RTK_ANAR; 392 break; 393 case MII_ANER: 394 re8139_reg = RTK_ANER; 395 break; 396 case MII_ANLPAR: 397 re8139_reg = RTK_LPAR; 398 break; 399 case MII_PHYIDR1: 400 case MII_PHYIDR2: 401 return 0; 402 break; 403 default: 404 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 405 return -1; 406 } 407 CSR_WRITE_2(sc, re8139_reg, val); 408 return 0; 409 } 410 411 static void 412 re_miibus_statchg(struct ifnet *ifp) 413 { 414 415 return; 416 } 417 418 static void 419 re_reset(struct rtk_softc *sc) 420 { 421 int i; 422 423 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 424 425 for (i = 0; i < RTK_TIMEOUT; i++) { 426 DELAY(10); 427 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 428 break; 429 } 430 if (i == RTK_TIMEOUT) 431 printf("%s: reset never completed!\n", 432 device_xname(sc->sc_dev)); 433 434 /* 435 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 436 * but also says "Rtl8169s sigle chip detected". 437 */ 438 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 439 CSR_WRITE_1(sc, RTK_LDPS, 1); 440 441 } 442 443 /* 444 * The following routine is designed to test for a defect on some 445 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 446 * lines connected to the bus, however for a 32-bit only card, they 447 * should be pulled high. The result of this defect is that the 448 * NIC will not work right if you plug it into a 64-bit slot: DMA 449 * operations will be done with 64-bit transfers, which will fail 450 * because the 64-bit data lines aren't connected. 451 * 452 * There's no way to work around this (short of talking a soldering 453 * iron to the board), however we can detect it. The method we use 454 * here is to put the NIC into digital loopback mode, set the receiver 455 * to promiscuous mode, and then try to send a frame. We then compare 456 * the frame data we sent to what was received. If the data matches, 457 * then the NIC is working correctly, otherwise we know the user has 458 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 459 * slot. In the latter case, there's no way the NIC can work correctly, 460 * so we print out a message on the console and abort the device attach. 461 */ 462 463 int 464 re_diag(struct rtk_softc *sc) 465 { 466 struct ifnet *ifp = &sc->ethercom.ec_if; 467 struct mbuf *m0; 468 struct ether_header *eh; 469 struct re_rxsoft *rxs; 470 struct re_desc *cur_rx; 471 bus_dmamap_t dmamap; 472 uint16_t status; 473 uint32_t rxstat; 474 int total_len, i, error = 0; 475 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 476 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 477 478 RE_LOCK(sc); 479 480 /* Allocate a single mbuf */ 481 482 MGETHDR(m0, M_DONTWAIT, MT_DATA); 483 if (m0 == NULL) { 484 RE_UNLOCK(sc); 485 return ENOBUFS; 486 } 487 488 /* 489 * Initialize the NIC in test mode. This sets the chip up 490 * so that it can send and receive frames, but performs the 491 * following special functions: 492 * - Puts receiver in promiscuous mode 493 * - Enables digital loopback mode 494 * - Leaves interrupts turned off 495 */ 496 497 ifp->if_flags |= IFF_PROMISC; 498 sc->re_testmode = 1; 499 re_init_locked(sc); 500 re_stop_locked(sc, 0); 501 DELAY(100000); 502 re_init_locked(sc); 503 504 /* Put some data in the mbuf */ 505 506 eh = mtod(m0, struct ether_header *); 507 memcpy(eh->ether_dhost, &dst, ETHER_ADDR_LEN); 508 memcpy(eh->ether_shost, &src, ETHER_ADDR_LEN); 509 eh->ether_type = htons(ETHERTYPE_IP); 510 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 511 512 /* 513 * Queue the packet, start transmission. 514 */ 515 516 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 517 IF_ENQUEUE(&ifp->if_snd, m0); 518 re_start_locked(sc); 519 m0 = NULL; 520 521 /* Wait for it to propagate through the chip */ 522 523 DELAY(100000); 524 for (i = 0; i < RTK_TIMEOUT; i++) { 525 status = CSR_READ_2(sc, RTK_ISR); 526 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 527 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 528 break; 529 DELAY(10); 530 } 531 if (i == RTK_TIMEOUT) { 532 aprint_error_dev(sc->sc_dev, 533 "diagnostic failed, failed to receive packet " 534 "in loopback mode\n"); 535 error = EIO; 536 goto done; 537 } 538 539 /* 540 * The packet should have been dumped into the first 541 * entry in the RX DMA ring. Grab it from there. 542 */ 543 544 rxs = &sc->re_ldata.re_rxsoft[0]; 545 dmamap = rxs->rxs_dmamap; 546 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 547 BUS_DMASYNC_POSTREAD); 548 bus_dmamap_unload(sc->sc_dmat, dmamap); 549 550 m0 = rxs->rxs_mbuf; 551 rxs->rxs_mbuf = NULL; 552 eh = mtod(m0, struct ether_header *); 553 554 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 555 cur_rx = &sc->re_ldata.re_rx_list[0]; 556 rxstat = le32toh(cur_rx->re_cmdstat); 557 total_len = rxstat & sc->re_rxlenmask; 558 559 if (total_len != ETHER_MIN_LEN) { 560 aprint_error_dev(sc->sc_dev, 561 "diagnostic failed, received short packet\n"); 562 error = EIO; 563 goto done; 564 } 565 566 /* Test that the received packet data matches what we sent. */ 567 568 if (memcmp(&eh->ether_dhost, &dst, ETHER_ADDR_LEN) || 569 memcmp(&eh->ether_shost, &src, ETHER_ADDR_LEN) || 570 ntohs(eh->ether_type) != ETHERTYPE_IP) { 571 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 572 "expected TX data: %s/%s/0x%x\n" 573 "received RX data: %s/%s/0x%x\n" 574 "You may have a defective 32-bit NIC plugged " 575 "into a 64-bit PCI slot.\n" 576 "Please re-install the NIC in a 32-bit slot " 577 "for proper operation.\n" 578 "Read the re(4) man page for more details.\n" , 579 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 580 ether_sprintf(eh->ether_dhost), 581 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 582 error = EIO; 583 } 584 585 done: 586 /* Turn interface off, release resources */ 587 588 sc->re_testmode = 0; 589 ifp->if_flags &= ~IFF_PROMISC; 590 re_stop_locked(sc, 0); 591 m_freem(m0); 592 593 RE_UNLOCK(sc); 594 595 return error; 596 } 597 598 599 /* 600 * Attach the interface. Allocate softc structures, do ifmedia 601 * setup and ethernet/BPF attach. 602 */ 603 void 604 re_attach(struct rtk_softc *sc) 605 { 606 uint8_t eaddr[ETHER_ADDR_LEN]; 607 struct ifnet *ifp; 608 struct mii_data *mii = &sc->mii; 609 int error = 0, i; 610 const struct re_revision *rr; 611 const char *re_name = NULL; 612 uint32_t maclo, machi; 613 614 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NET); 615 616 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 617 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 618 sc->sc_hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 619 620 for (rr = re_revisions; rr->re_name != NULL; rr++) { 621 if (rr->re_chipid == sc->sc_hwrev) 622 re_name = rr->re_name; 623 } 624 625 if (re_name == NULL) 626 aprint_normal_dev(sc->sc_dev, 627 "unknown ASIC (0x%04x)\n", sc->sc_hwrev >> 16); 628 else 629 aprint_normal_dev(sc->sc_dev, 630 "%s (0x%04x)\n", re_name, sc->sc_hwrev >> 16); 631 632 switch (sc->sc_hwrev) { 633 case RTK_HWREV_8169: 634 sc->sc_quirk |= RTKQ_8169NONS; 635 break; 636 case RTK_HWREV_8169S: 637 case RTK_HWREV_8110S: 638 case RTK_HWREV_8169_8110SB: 639 case RTK_HWREV_8169_8110SBL: 640 case RTK_HWREV_8169_8110SC: 641 sc->sc_quirk |= RTKQ_MACLDPS; 642 break; 643 case RTK_HWREV_8168B_SPIN1: 644 case RTK_HWREV_8168B_SPIN2: 645 case RTK_HWREV_8168B_SPIN3: 646 sc->sc_quirk |= RTKQ_MACSTAT; 647 break; 648 case RTK_HWREV_8168C: 649 case RTK_HWREV_8168C_SPIN2: 650 case RTK_HWREV_8168CP: 651 case RTK_HWREV_8168D: 652 case RTK_HWREV_8168DP: 653 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 654 RTKQ_MACSTAT | RTKQ_CMDSTOP; 655 /* 656 * From FreeBSD driver: 657 * 658 * These (8168/8111) controllers support jumbo frame 659 * but it seems that enabling it requires touching 660 * additional magic registers. Depending on MAC 661 * revisions some controllers need to disable 662 * checksum offload. So disable jumbo frame until 663 * I have better idea what it really requires to 664 * make it support. 665 * RTL8168C/CP : supports up to 6KB jumbo frame. 666 * RTL8111C/CP : supports up to 9KB jumbo frame. 667 */ 668 sc->sc_quirk |= RTKQ_NOJUMBO; 669 break; 670 case RTK_HWREV_8168E: 671 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 672 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM | 673 RTKQ_NOJUMBO; 674 break; 675 case RTK_HWREV_8168E_VL: 676 case RTK_HWREV_8168F: 677 sc->sc_quirk |= RTKQ_EARLYOFF; 678 /*FALLTHROUGH*/ 679 case RTK_HWREV_8411: 680 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 681 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 682 break; 683 case RTK_HWREV_8168EP: 684 case RTK_HWREV_8168FP: 685 case RTK_HWREV_8168G: 686 case RTK_HWREV_8168GU: 687 case RTK_HWREV_8168H: 688 case RTK_HWREV_8411B: 689 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 690 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO | 691 RTKQ_RXDV_GATED | RTKQ_TXRXEN_LATER; 692 break; 693 case RTK_HWREV_8100E: 694 case RTK_HWREV_8100E_SPIN2: 695 case RTK_HWREV_8101E: 696 sc->sc_quirk |= RTKQ_NOJUMBO; 697 break; 698 case RTK_HWREV_8102E: 699 case RTK_HWREV_8102EL: 700 case RTK_HWREV_8102EL_SPIN1: 701 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 702 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 703 break; 704 case RTK_HWREV_8103E: 705 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 706 RTKQ_MACSTAT | RTKQ_CMDSTOP; 707 break; 708 case RTK_HWREV_8401E: 709 case RTK_HWREV_8105E: 710 case RTK_HWREV_8105E_SPIN1: /* XXX */ 711 case RTK_HWREV_8106E: 712 sc->sc_quirk |= RTKQ_PHYWAKE_PM | 713 RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT | 714 RTKQ_CMDSTOP; 715 break; 716 case RTK_HWREV_8402: 717 sc->sc_quirk |= RTKQ_PHYWAKE_PM | 718 RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT | 719 RTKQ_CMDSTOP; /* CMDSTOP_WAIT_TXQ */ 720 break; 721 default: 722 /* assume the latest features */ 723 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 724 sc->sc_quirk |= RTKQ_NOJUMBO; 725 } 726 727 /* Set RX length mask */ 728 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 729 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 730 sc->re_ldata.re_rx_desc_cnt = RE_RX_DESC_CNT_8169; 731 } else { 732 sc->sc_quirk |= RTKQ_NOJUMBO; 733 734 /* Set RX length mask */ 735 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 736 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 737 sc->re_ldata.re_rx_desc_cnt = RE_RX_DESC_CNT_8139; 738 } 739 740 /* Reset the adapter. */ 741 re_reset(sc); 742 743 /* 744 * RTL81x9 chips automatically read EEPROM to init MAC address, 745 * and some NAS override its MAC address per own configuration, 746 * so no need to explicitly read EEPROM and set ID registers. 747 */ 748 #ifdef RE_USE_EECMD 749 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 750 /* 751 * Get station address from ID registers. 752 */ 753 for (i = 0; i < ETHER_ADDR_LEN; i++) 754 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 755 } else { 756 uint16_t val; 757 int addr_len; 758 759 /* 760 * Get EEPROM command address length to fetch station address. 761 */ 762 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 763 addr_len = RTK_EEADDR_LEN1; 764 else 765 addr_len = RTK_EEADDR_LEN0; 766 767 /* 768 * Get station address from the EEPROM. 769 */ 770 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 771 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 772 eaddr[(i * 2) + 0] = val & 0xff; 773 eaddr[(i * 2) + 1] = val >> 8; 774 } 775 } 776 #else 777 /* 778 * Get station address from ID registers. 779 */ 780 for (i = 0; i < ETHER_ADDR_LEN; i++) 781 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 782 #endif 783 /* 784 * Some chips don't provide a viable MAC address, e.g., what's present 785 * on the NanoPi R4S (non-EE version). 786 */ 787 if (ETHER_IS_ZERO(eaddr)) { 788 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 789 machi = cprng_strong32() & 0xffff; 790 eaddr[0] = maclo & 0xff; 791 eaddr[1] = (maclo >> 8) & 0xff; 792 eaddr[2] = (maclo >> 16) & 0xff; 793 eaddr[3] = (maclo >> 24) & 0xff; 794 eaddr[4] = machi & 0xff; 795 eaddr[5] = (machi >> 8) & 0xff; 796 } 797 798 /* Take PHY out of power down mode. */ 799 if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0) 800 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80); 801 802 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 803 ether_sprintf(eaddr)); 804 805 #if 0 806 if (sc->re_ldata.re_tx_desc_cnt > 807 PAGE_SIZE / sizeof(struct re_desc)) { 808 sc->re_ldata.re_tx_desc_cnt = 809 PAGE_SIZE / sizeof(struct re_desc); 810 } 811 #endif 812 813 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 814 sc->re_ldata.re_tx_desc_cnt); 815 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 816 817 /* Allocate DMA'able memory for the TX ring */ 818 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 819 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 820 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 821 aprint_error_dev(sc->sc_dev, 822 "can't allocate tx listseg, error = %d\n", error); 823 goto fail_0; 824 } 825 826 /* Load the map for the TX ring. */ 827 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 828 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 829 (void **)&sc->re_ldata.re_tx_list, 830 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 831 aprint_error_dev(sc->sc_dev, 832 "can't map tx list, error = %d\n", error); 833 goto fail_1; 834 } 835 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 836 837 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 838 RE_TX_LIST_SZ(sc), 0, 0, 839 &sc->re_ldata.re_tx_list_map)) != 0) { 840 aprint_error_dev(sc->sc_dev, 841 "can't create tx list map, error = %d\n", error); 842 goto fail_2; 843 } 844 845 846 if ((error = bus_dmamap_load(sc->sc_dmat, 847 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 848 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 849 aprint_error_dev(sc->sc_dev, 850 "can't load tx list, error = %d\n", error); 851 goto fail_3; 852 } 853 854 /* Create DMA maps for TX buffers */ 855 for (i = 0; i < RE_TX_QLEN(sc); i++) { 856 error = bus_dmamap_create(sc->sc_dmat, 857 round_page(IP_MAXPACKET), 858 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 859 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 860 if (error) { 861 aprint_error_dev(sc->sc_dev, 862 "can't create DMA map for TX\n"); 863 goto fail_4; 864 } 865 } 866 867 /* Allocate DMA'able memory for the RX ring */ 868 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 869 if ((error = bus_dmamem_alloc(sc->sc_dmat, 870 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 871 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 872 aprint_error_dev(sc->sc_dev, 873 "can't allocate rx listseg, error = %d\n", error); 874 goto fail_4; 875 } 876 877 /* Load the map for the RX ring. */ 878 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 879 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 880 (void **)&sc->re_ldata.re_rx_list, 881 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 882 aprint_error_dev(sc->sc_dev, 883 "can't map rx list, error = %d\n", error); 884 goto fail_5; 885 } 886 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 887 888 if ((error = bus_dmamap_create(sc->sc_dmat, 889 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 890 &sc->re_ldata.re_rx_list_map)) != 0) { 891 aprint_error_dev(sc->sc_dev, 892 "can't create rx list map, error = %d\n", error); 893 goto fail_6; 894 } 895 896 if ((error = bus_dmamap_load(sc->sc_dmat, 897 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 898 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 899 aprint_error_dev(sc->sc_dev, 900 "can't load rx list, error = %d\n", error); 901 goto fail_7; 902 } 903 904 /* Create DMA maps for RX buffers */ 905 for (i = 0; i < RE_RX_DESC_CNT(sc); i++) { 906 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 907 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 908 if (error) { 909 aprint_error_dev(sc->sc_dev, 910 "can't create DMA map for RX\n"); 911 goto fail_8; 912 } 913 } 914 915 /* 916 * Record interface as attached. From here, we should not fail. 917 */ 918 sc->sc_flags |= RTK_ATTACHED; 919 920 ifp = &sc->ethercom.ec_if; 921 ifp->if_softc = sc; 922 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 923 ifp->if_mtu = ETHERMTU; 924 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 925 ifp->if_extflags = IFEF_MPSAFE; 926 ifp->if_ioctl = re_ioctl; 927 sc->ethercom.ec_capabilities |= 928 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 929 ifp->if_start = re_start; 930 ifp->if_stop = re_stop; 931 932 sc->sc_if_flags = ifp->if_flags; 933 934 /* 935 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 936 * so we have a workaround to handle the bug by padding 937 * such packets manually. 938 */ 939 ifp->if_capabilities |= 940 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 941 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 942 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 943 IFCAP_TSOv4; 944 945 ifp->if_watchdog = re_watchdog; 946 ifp->if_init = re_init; 947 ifp->if_capenable = ifp->if_capabilities; 948 IFQ_SET_MAXLEN(&ifp->if_snd, RE_IFQ_MAXLEN); 949 IFQ_SET_READY(&ifp->if_snd); 950 951 callout_init(&sc->rtk_tick_ch, CALLOUT_MPSAFE); 952 callout_setfunc(&sc->rtk_tick_ch, re_tick, sc); 953 954 /* Do MII setup */ 955 mii->mii_ifp = ifp; 956 mii->mii_readreg = re_miibus_readreg; 957 mii->mii_writereg = re_miibus_writereg; 958 mii->mii_statchg = re_miibus_statchg; 959 sc->ethercom.ec_mii = mii; 960 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 961 ether_mediastatus); 962 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 963 MII_OFFSET_ANY, 0); 964 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 965 966 /* 967 * Call MI attach routine. 968 */ 969 if_attach(ifp); 970 if_deferred_start_init(ifp, NULL); 971 ether_ifattach(ifp, eaddr); 972 ether_set_ifflags_cb(&sc->ethercom, re_ifflags_cb); 973 974 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 975 RND_TYPE_NET, RND_FLAG_DEFAULT); 976 977 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 978 pmf_class_network_register(sc->sc_dev, ifp); 979 else 980 aprint_error_dev(sc->sc_dev, 981 "couldn't establish power handler\n"); 982 983 return; 984 985 fail_8: 986 /* Destroy DMA maps for RX buffers. */ 987 for (i = 0; i < RE_RX_DESC_CNT(sc); i++) 988 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 989 bus_dmamap_destroy(sc->sc_dmat, 990 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 991 992 /* Free DMA'able memory for the RX ring. */ 993 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 994 fail_7: 995 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 996 fail_6: 997 bus_dmamem_unmap(sc->sc_dmat, 998 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 999 fail_5: 1000 bus_dmamem_free(sc->sc_dmat, 1001 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 1002 1003 fail_4: 1004 /* Destroy DMA maps for TX buffers. */ 1005 for (i = 0; i < RE_TX_QLEN(sc); i++) 1006 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 1007 bus_dmamap_destroy(sc->sc_dmat, 1008 sc->re_ldata.re_txq[i].txq_dmamap); 1009 1010 /* Free DMA'able memory for the TX ring. */ 1011 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 1012 fail_3: 1013 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 1014 fail_2: 1015 bus_dmamem_unmap(sc->sc_dmat, 1016 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1017 fail_1: 1018 bus_dmamem_free(sc->sc_dmat, 1019 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 1020 fail_0: 1021 mutex_destroy(&sc->sc_lock); 1022 1023 return; 1024 } 1025 1026 1027 /* 1028 * re_activate: 1029 * Handle device activation/deactivation requests. 1030 */ 1031 int 1032 re_activate(device_t self, enum devact act) 1033 { 1034 struct rtk_softc *sc = device_private(self); 1035 1036 switch (act) { 1037 case DVACT_DEACTIVATE: 1038 if_deactivate(&sc->ethercom.ec_if); 1039 return 0; 1040 default: 1041 return EOPNOTSUPP; 1042 } 1043 } 1044 1045 /* 1046 * re_detach: 1047 * Detach a rtk interface. 1048 */ 1049 int 1050 re_detach(struct rtk_softc *sc) 1051 { 1052 struct ifnet *ifp = &sc->ethercom.ec_if; 1053 int i; 1054 1055 /* 1056 * Succeed now if there isn't any work to do. 1057 */ 1058 if ((sc->sc_flags & RTK_ATTACHED) == 0) 1059 return 0; 1060 1061 re_stop(ifp, 1); 1062 1063 /* Detach all PHYs. */ 1064 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 1065 1066 rnd_detach_source(&sc->rnd_source); 1067 ether_ifdetach(ifp); 1068 if_detach(ifp); 1069 1070 /* Delete all remaining media. */ 1071 ifmedia_fini(&sc->mii.mii_media); 1072 1073 /* Destroy DMA maps for RX buffers. */ 1074 for (i = 0; i < RE_RX_DESC_CNT(sc); i++) 1075 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 1076 bus_dmamap_destroy(sc->sc_dmat, 1077 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 1078 1079 /* Free DMA'able memory for the RX ring. */ 1080 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 1081 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 1082 bus_dmamem_unmap(sc->sc_dmat, 1083 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 1084 bus_dmamem_free(sc->sc_dmat, 1085 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 1086 1087 /* Destroy DMA maps for TX buffers. */ 1088 for (i = 0; i < RE_TX_QLEN(sc); i++) 1089 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 1090 bus_dmamap_destroy(sc->sc_dmat, 1091 sc->re_ldata.re_txq[i].txq_dmamap); 1092 1093 /* Free DMA'able memory for the TX ring. */ 1094 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 1095 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 1096 bus_dmamem_unmap(sc->sc_dmat, 1097 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1098 bus_dmamem_free(sc->sc_dmat, 1099 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 1100 1101 pmf_device_deregister(sc->sc_dev); 1102 1103 mutex_destroy(&sc->sc_lock); 1104 1105 /* we don't want to run again */ 1106 sc->sc_flags &= ~RTK_ATTACHED; 1107 1108 return 0; 1109 } 1110 1111 /* 1112 * re_enable: 1113 * Enable the RTL81X9 chip. 1114 */ 1115 static int 1116 re_enable(struct rtk_softc *sc) 1117 { 1118 1119 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 1120 if ((*sc->sc_enable)(sc) != 0) { 1121 printf("%s: device enable failed\n", 1122 device_xname(sc->sc_dev)); 1123 return EIO; 1124 } 1125 sc->sc_flags |= RTK_ENABLED; 1126 } 1127 return 0; 1128 } 1129 1130 /* 1131 * re_disable: 1132 * Disable the RTL81X9 chip. 1133 */ 1134 static void 1135 re_disable(struct rtk_softc *sc) 1136 { 1137 1138 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 1139 (*sc->sc_disable)(sc); 1140 sc->sc_flags &= ~RTK_ENABLED; 1141 } 1142 } 1143 1144 static int 1145 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1146 { 1147 struct mbuf *n = NULL; 1148 bus_dmamap_t map; 1149 struct re_desc *d; 1150 struct re_rxsoft *rxs; 1151 uint32_t cmdstat; 1152 int error; 1153 1154 if (m == NULL) { 1155 MGETHDR(n, M_DONTWAIT, MT_DATA); 1156 if (n == NULL) 1157 return ENOBUFS; 1158 1159 MCLAIM(n, &sc->ethercom.ec_rx_mowner); 1160 MCLGET(n, M_DONTWAIT); 1161 if ((n->m_flags & M_EXT) == 0) { 1162 m_freem(n); 1163 return ENOBUFS; 1164 } 1165 m = n; 1166 } else 1167 m->m_data = m->m_ext.ext_buf; 1168 1169 /* 1170 * Initialize mbuf length fields and fixup 1171 * alignment so that the frame payload is 1172 * longword aligned. 1173 */ 1174 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1175 m->m_data += RE_ETHER_ALIGN; 1176 1177 rxs = &sc->re_ldata.re_rxsoft[idx]; 1178 map = rxs->rxs_dmamap; 1179 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1180 BUS_DMA_READ|BUS_DMA_NOWAIT); 1181 1182 if (error) 1183 goto out; 1184 1185 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1186 BUS_DMASYNC_PREREAD); 1187 1188 d = &sc->re_ldata.re_rx_list[idx]; 1189 #ifdef DIAGNOSTIC 1190 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1191 cmdstat = le32toh(d->re_cmdstat); 1192 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1193 if (cmdstat & RE_RDESC_STAT_OWN) { 1194 panic("%s: tried to map busy RX descriptor", 1195 device_xname(sc->sc_dev)); 1196 } 1197 #endif 1198 1199 rxs->rxs_mbuf = m; 1200 1201 d->re_vlanctl = 0; 1202 cmdstat = map->dm_segs[0].ds_len; 1203 if (idx == (RE_RX_DESC_CNT(sc) - 1)) 1204 cmdstat |= RE_RDESC_CMD_EOR; 1205 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1206 d->re_cmdstat = htole32(cmdstat); 1207 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1208 cmdstat |= RE_RDESC_CMD_OWN; 1209 d->re_cmdstat = htole32(cmdstat); 1210 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1211 1212 return 0; 1213 out: 1214 m_freem(n); 1215 return error; 1216 } 1217 1218 static int 1219 re_tx_list_init(struct rtk_softc *sc) 1220 { 1221 int i; 1222 1223 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1224 for (i = 0; i < RE_TX_QLEN(sc); i++) { 1225 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1226 } 1227 1228 bus_dmamap_sync(sc->sc_dmat, 1229 sc->re_ldata.re_tx_list_map, 0, 1230 sc->re_ldata.re_tx_list_map->dm_mapsize, 1231 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1232 sc->re_ldata.re_txq_prodidx = 0; 1233 sc->re_ldata.re_txq_considx = 0; 1234 sc->re_ldata.re_txq_free = RE_TX_QLEN(sc); 1235 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1236 sc->re_ldata.re_tx_nextfree = 0; 1237 1238 return 0; 1239 } 1240 1241 static int 1242 re_rx_list_init(struct rtk_softc *sc) 1243 { 1244 int i, error; 1245 1246 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1247 1248 for (i = 0; i < RE_RX_DESC_CNT(sc); i++) { 1249 error = re_newbuf(sc, i, NULL); 1250 if (error != 0) 1251 return error; 1252 } 1253 1254 sc->re_ldata.re_rx_prodidx = 0; 1255 sc->re_head = sc->re_tail = NULL; 1256 1257 return 0; 1258 } 1259 1260 /* 1261 * RX handler for C+ and 8169. For the gigE chips, we support 1262 * the reception of jumbo frames that have been fragmented 1263 * across multiple 2K mbuf cluster buffers. 1264 */ 1265 static void 1266 re_rxeof(struct rtk_softc *sc) 1267 { 1268 struct mbuf *m; 1269 struct ifnet *ifp; 1270 int i, total_len; 1271 struct re_desc *cur_rx; 1272 struct re_rxsoft *rxs; 1273 uint32_t rxstat, rxvlan; 1274 1275 RE_ASSERT_LOCKED(sc); 1276 1277 ifp = &sc->ethercom.ec_if; 1278 1279 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1280 cur_rx = &sc->re_ldata.re_rx_list[i]; 1281 RE_RXDESCSYNC(sc, i, 1282 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1283 rxstat = le32toh(cur_rx->re_cmdstat); 1284 rxvlan = le32toh(cur_rx->re_vlanctl); 1285 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1286 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1287 break; 1288 } 1289 total_len = rxstat & sc->re_rxlenmask; 1290 rxs = &sc->re_ldata.re_rxsoft[i]; 1291 m = rxs->rxs_mbuf; 1292 1293 /* Invalidate the RX mbuf and unload its map */ 1294 1295 bus_dmamap_sync(sc->sc_dmat, 1296 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1297 BUS_DMASYNC_POSTREAD); 1298 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1299 1300 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1301 if (re_newbuf(sc, i, NULL) != 0) { 1302 /* 1303 * If this is part of a multi-fragment packet, 1304 * discard all the pieces 1305 */ 1306 if_statinc(ifp, if_ierrors); 1307 if (sc->re_head != NULL) { 1308 m_freem(sc->re_head); 1309 sc->re_head = sc->re_tail = NULL; 1310 } 1311 re_newbuf(sc, i, m); 1312 1313 /* XXX needs to drop remaining frags */ 1314 continue; 1315 } 1316 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1317 if (sc->re_head == NULL) 1318 sc->re_head = sc->re_tail = m; 1319 else { 1320 m_remove_pkthdr(m); 1321 sc->re_tail->m_next = m; 1322 sc->re_tail = m; 1323 } 1324 continue; 1325 } 1326 1327 /* 1328 * NOTE: for the 8139C+, the frame length field 1329 * is always 12 bits in size, but for the gigE chips, 1330 * it is 13 bits (since the max RX frame length is 16K). 1331 * Unfortunately, all 32 bits in the status word 1332 * were already used, so to make room for the extra 1333 * length bit, RealTek took out the 'frame alignment 1334 * error' bit and shifted the other status bits 1335 * over one slot. The OWN, EOR, FS and LS bits are 1336 * still in the same places. We have already extracted 1337 * the frame length and checked the OWN bit, so rather 1338 * than using an alternate bit mapping, we shift the 1339 * status bits one space to the right so we can evaluate 1340 * them using the 8169 status as though it was in the 1341 * same format as that of the 8139C+. 1342 */ 1343 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1344 rxstat >>= 1; 1345 1346 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1347 #ifdef RE_DEBUG 1348 printf("%s: RX error (rxstat = 0x%08x)", 1349 device_xname(sc->sc_dev), rxstat); 1350 if (rxstat & RE_RDESC_STAT_FRALIGN) 1351 printf(", frame alignment error"); 1352 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1353 printf(", out of buffer space"); 1354 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1355 printf(", FIFO overrun"); 1356 if (rxstat & RE_RDESC_STAT_GIANT) 1357 printf(", giant packet"); 1358 if (rxstat & RE_RDESC_STAT_RUNT) 1359 printf(", runt packet"); 1360 if (rxstat & RE_RDESC_STAT_CRCERR) 1361 printf(", CRC error"); 1362 printf("\n"); 1363 #endif 1364 if_statinc(ifp, if_ierrors); 1365 /* 1366 * If this is part of a multi-fragment packet, 1367 * discard all the pieces. 1368 */ 1369 if (sc->re_head != NULL) { 1370 m_freem(sc->re_head); 1371 sc->re_head = sc->re_tail = NULL; 1372 } 1373 re_newbuf(sc, i, m); 1374 continue; 1375 } 1376 1377 /* 1378 * If allocating a replacement mbuf fails, 1379 * reload the current one. 1380 */ 1381 1382 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1383 if_statinc(ifp, if_ierrors); 1384 if (sc->re_head != NULL) { 1385 m_freem(sc->re_head); 1386 sc->re_head = sc->re_tail = NULL; 1387 } 1388 re_newbuf(sc, i, m); 1389 continue; 1390 } 1391 1392 if (sc->re_head != NULL) { 1393 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1394 /* 1395 * Special case: if there's 4 bytes or less 1396 * in this buffer, the mbuf can be discarded: 1397 * the last 4 bytes is the CRC, which we don't 1398 * care about anyway. 1399 */ 1400 if (m->m_len <= ETHER_CRC_LEN) { 1401 sc->re_tail->m_len -= 1402 (ETHER_CRC_LEN - m->m_len); 1403 m_freem(m); 1404 } else { 1405 m->m_len -= ETHER_CRC_LEN; 1406 m_remove_pkthdr(m); 1407 sc->re_tail->m_next = m; 1408 } 1409 m = sc->re_head; 1410 sc->re_head = sc->re_tail = NULL; 1411 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1412 } else 1413 m->m_pkthdr.len = m->m_len = 1414 (total_len - ETHER_CRC_LEN); 1415 1416 m_set_rcvif(m, ifp); 1417 1418 /* Do RX checksumming */ 1419 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1420 /* Check IP header checksum */ 1421 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) { 1422 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1423 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1424 m->m_pkthdr.csum_flags |= 1425 M_CSUM_IPv4_BAD; 1426 1427 /* Check TCP/UDP checksum */ 1428 if (RE_TCPPKT(rxstat)) { 1429 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1430 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1431 m->m_pkthdr.csum_flags |= 1432 M_CSUM_TCP_UDP_BAD; 1433 } else if (RE_UDPPKT(rxstat)) { 1434 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1435 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) { 1436 /* 1437 * XXX: 8139C+ thinks UDP csum 1438 * 0xFFFF is bad, force software 1439 * calculation. 1440 */ 1441 if (sc->sc_quirk & RTKQ_8139CPLUS) 1442 m->m_pkthdr.csum_flags 1443 &= ~M_CSUM_UDPv4; 1444 else 1445 m->m_pkthdr.csum_flags 1446 |= M_CSUM_TCP_UDP_BAD; 1447 } 1448 } 1449 } 1450 } else { 1451 /* Check IPv4 header checksum */ 1452 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) { 1453 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1454 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1455 m->m_pkthdr.csum_flags |= 1456 M_CSUM_IPv4_BAD; 1457 1458 /* Check TCPv4/UDPv4 checksum */ 1459 if (RE_TCPPKT(rxstat)) { 1460 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1461 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1462 m->m_pkthdr.csum_flags |= 1463 M_CSUM_TCP_UDP_BAD; 1464 } else if (RE_UDPPKT(rxstat)) { 1465 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1466 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1467 m->m_pkthdr.csum_flags |= 1468 M_CSUM_TCP_UDP_BAD; 1469 } 1470 } 1471 /* XXX Check TCPv6/UDPv6 checksum? */ 1472 } 1473 1474 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1475 vlan_set_tag(m, 1476 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA)); 1477 } 1478 if_percpuq_enqueue(ifp->if_percpuq, m); 1479 } 1480 1481 sc->re_ldata.re_rx_prodidx = i; 1482 } 1483 1484 static void 1485 re_txeof(struct rtk_softc *sc) 1486 { 1487 struct ifnet *ifp; 1488 struct re_txq *txq; 1489 uint32_t txstat; 1490 int idx, descidx; 1491 1492 RE_ASSERT_LOCKED(sc); 1493 1494 ifp = &sc->ethercom.ec_if; 1495 1496 for (idx = sc->re_ldata.re_txq_considx; 1497 sc->re_ldata.re_txq_free < RE_TX_QLEN(sc); 1498 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1499 txq = &sc->re_ldata.re_txq[idx]; 1500 KASSERT(txq->txq_mbuf != NULL); 1501 1502 descidx = txq->txq_descidx; 1503 RE_TXDESCSYNC(sc, descidx, 1504 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1505 txstat = 1506 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1507 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1508 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1509 if (txstat & RE_TDESC_CMD_OWN) { 1510 break; 1511 } 1512 1513 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1514 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1515 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1516 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1517 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1518 m_freem(txq->txq_mbuf); 1519 txq->txq_mbuf = NULL; 1520 txq->txq_nsegs = -42; 1521 1522 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1523 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1524 if_statinc_ref(ifp, nsr, if_collisions); 1525 if (txstat & RE_TDESC_STAT_TXERRSUM) 1526 if_statinc_ref(ifp, nsr, if_oerrors); 1527 else 1528 if_statinc_ref(ifp, nsr, if_opackets); 1529 IF_STAT_PUTREF(ifp); 1530 } 1531 1532 sc->re_ldata.re_txq_considx = idx; 1533 1534 if ((sc->sc_if_flags & IFF_OACTIVE) != 0 && 1535 sc->re_ldata.re_txq_free > 0 && 1536 sc->re_ldata.re_tx_free >= RE_NTXDESC_RSVD) { 1537 ifp->if_flags &= ~IFF_OACTIVE; 1538 sc->sc_if_flags = ifp->if_flags; 1539 } 1540 1541 /* 1542 * If not all descriptors have been released reaped yet, 1543 * reload the timer so that we will eventually get another 1544 * interrupt that will cause us to re-enter this routine. 1545 * This is done in case the transmitter has gone idle. 1546 */ 1547 if (sc->re_ldata.re_txq_free < RE_TX_QLEN(sc)) { 1548 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) 1549 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1550 1551 } else 1552 ifp->if_timer = 0; 1553 } 1554 1555 static void 1556 re_tick(void *arg) 1557 { 1558 struct rtk_softc *sc = arg; 1559 1560 RE_LOCK(sc); 1561 re_tick_locked(sc); 1562 RE_UNLOCK(sc); 1563 } 1564 1565 static void 1566 re_tick_locked(struct rtk_softc *sc) 1567 { 1568 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1569 mii_tick(&sc->mii); 1570 1571 callout_schedule(&sc->rtk_tick_ch, hz); 1572 } 1573 1574 1575 int 1576 re_intr(void *arg) 1577 { 1578 struct rtk_softc *sc = arg; 1579 struct ifnet *ifp; 1580 uint16_t status, rndstatus = 0; 1581 int handled = 0; 1582 1583 if (!device_has_power(sc->sc_dev)) 1584 return 0; 1585 1586 ifp = &sc->ethercom.ec_if; 1587 1588 if ((ifp->if_flags & IFF_UP) == 0) 1589 return 0; 1590 1591 const uint16_t status_mask = (sc->sc_quirk & RTKQ_IM_HW) ? 1592 RTK_INTRS_IM_HW : RTK_INTRS_CPLUS; 1593 1594 RE_LOCK(sc); 1595 1596 for (;;) { 1597 1598 status = CSR_READ_2(sc, RTK_ISR); 1599 /* If the card has gone away the read returns 0xffff. */ 1600 if (status == 0xffff) 1601 break; 1602 if (status != 0) { 1603 handled = 1; 1604 CSR_WRITE_2(sc, RTK_ISR, status); 1605 rndstatus = status; 1606 } 1607 1608 if ((status & status_mask) == 0) 1609 break; 1610 1611 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1612 re_rxeof(sc); 1613 1614 /* 1615 * Some chips will ignore a second TX request issued 1616 * while an existing transmission is in progress. If 1617 * the transmitter goes idle but there are still 1618 * packets waiting to be sent, we need to restart the 1619 * channel here to flush them out. This only seems to 1620 * be required with the PCIe devices. 1621 */ 1622 if ((status & (RTK_ISR_TX_OK | RTK_ISR_TX_DESC_UNAVAIL)) && 1623 (sc->sc_quirk & RTKQ_PCIE) != 0) { 1624 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1625 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1626 else 1627 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1628 } 1629 1630 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1631 RTK_ISR_TX_DESC_UNAVAIL | RTK_ISR_TX_OK)) 1632 re_txeof(sc); 1633 1634 if (status & RTK_ISR_SYSTEM_ERR) 1635 re_init_locked(sc); 1636 1637 if (status & RTK_ISR_LINKCHG) { 1638 callout_stop(&sc->rtk_tick_ch); 1639 re_tick_locked(sc); 1640 } 1641 } 1642 1643 if (handled) 1644 if_schedule_deferred_start(ifp); 1645 1646 rnd_add_uint32(&sc->rnd_source, rndstatus); 1647 1648 RE_UNLOCK(sc); 1649 1650 return handled; 1651 } 1652 1653 1654 1655 /* 1656 * Main transmit routine for C+ and gigE NICs. 1657 */ 1658 static void 1659 re_start(struct ifnet *ifp) 1660 { 1661 struct rtk_softc *sc = ifp->if_softc; 1662 1663 RE_LOCK(sc); 1664 re_start_locked(sc); 1665 RE_UNLOCK(sc); 1666 } 1667 1668 static void 1669 re_start_locked(struct rtk_softc *sc) 1670 { 1671 struct ifnet *ifp = &sc->ethercom.ec_if; 1672 struct mbuf *m; 1673 bus_dmamap_t map; 1674 struct re_txq *txq; 1675 struct re_desc *d; 1676 uint32_t cmdstat, re_flags, vlanctl; 1677 int ofree, idx, error, nsegs, seg; 1678 int startdesc, curdesc, lastdesc; 1679 bool pad; 1680 1681 RE_ASSERT_LOCKED(sc); 1682 1683 ofree = sc->re_ldata.re_txq_free; 1684 idx = sc->re_ldata.re_txq_prodidx; 1685 1686 for (;;) { 1687 1688 if (sc->re_ldata.re_txq_free == 0 || 1689 sc->re_ldata.re_tx_free == 0) { 1690 /* no more free slots left */ 1691 ifp->if_flags |= IFF_OACTIVE; 1692 sc->sc_if_flags = ifp->if_flags; 1693 break; 1694 } 1695 1696 IFQ_POLL(&ifp->if_snd, m); 1697 if (m == NULL) 1698 break; 1699 1700 /* 1701 * Set up checksum offload. Note: checksum offload bits must 1702 * appear in all descriptors of a multi-descriptor transmit 1703 * attempt. (This is according to testing done with an 8169 1704 * chip. I'm not sure if this is a requirement or a bug.) 1705 */ 1706 1707 vlanctl = 0; 1708 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1709 uint32_t segsz = m->m_pkthdr.segsz; 1710 1711 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1712 re_flags = RE_TDESC_CMD_LGSEND | 1713 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1714 } else { 1715 re_flags = RE_TDESC_CMD_LGSEND_V4; 1716 vlanctl |= 1717 (segsz << RE_TDESC_VLANCTL_MSSVAL_SHIFT); 1718 } 1719 } else { 1720 /* 1721 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1722 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1723 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1724 */ 1725 re_flags = 0; 1726 if ((m->m_pkthdr.csum_flags & 1727 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1728 != 0) { 1729 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1730 re_flags |= RE_TDESC_CMD_IPCSUM; 1731 if (m->m_pkthdr.csum_flags & 1732 M_CSUM_TCPv4) { 1733 re_flags |= 1734 RE_TDESC_CMD_TCPCSUM; 1735 } else if (m->m_pkthdr.csum_flags & 1736 M_CSUM_UDPv4) { 1737 re_flags |= 1738 RE_TDESC_CMD_UDPCSUM; 1739 } 1740 } else { 1741 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1742 if (m->m_pkthdr.csum_flags & 1743 M_CSUM_TCPv4) { 1744 vlanctl |= 1745 RE_TDESC_VLANCTL_TCPCSUM; 1746 } else if (m->m_pkthdr.csum_flags & 1747 M_CSUM_UDPv4) { 1748 vlanctl |= 1749 RE_TDESC_VLANCTL_UDPCSUM; 1750 } 1751 } 1752 } 1753 } 1754 1755 txq = &sc->re_ldata.re_txq[idx]; 1756 map = txq->txq_dmamap; 1757 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1758 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1759 1760 if (__predict_false(error)) { 1761 /* XXX try to defrag if EFBIG? */ 1762 printf("%s: can't map mbuf (error %d)\n", 1763 device_xname(sc->sc_dev), error); 1764 1765 IFQ_DEQUEUE(&ifp->if_snd, m); 1766 m_freem(m); 1767 if_statinc(ifp, if_oerrors); 1768 continue; 1769 } 1770 1771 nsegs = map->dm_nsegs; 1772 pad = false; 1773 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1774 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1775 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1776 pad = true; 1777 nsegs++; 1778 } 1779 1780 if (nsegs > sc->re_ldata.re_tx_free) { 1781 /* 1782 * Not enough free descriptors to transmit this packet. 1783 */ 1784 ifp->if_flags |= IFF_OACTIVE; 1785 sc->sc_if_flags = ifp->if_flags; 1786 bus_dmamap_unload(sc->sc_dmat, map); 1787 break; 1788 } 1789 1790 IFQ_DEQUEUE(&ifp->if_snd, m); 1791 1792 /* 1793 * Make sure that the caches are synchronized before we 1794 * ask the chip to start DMA for the packet data. 1795 */ 1796 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1797 BUS_DMASYNC_PREWRITE); 1798 /* 1799 * Set up hardware VLAN tagging. Note: vlan tag info must 1800 * appear in all descriptors of a multi-descriptor 1801 * transmission attempt. 1802 */ 1803 if (vlan_has_tag(m)) 1804 vlanctl |= bswap16(vlan_get_tag(m)) | 1805 RE_TDESC_VLANCTL_TAG; 1806 1807 /* 1808 * Map the segment array into descriptors. 1809 * Note that we set the start-of-frame and 1810 * end-of-frame markers for either TX or RX, 1811 * but they really only have meaning in the TX case. 1812 * (In the RX case, it's the chip that tells us 1813 * where packets begin and end.) 1814 * We also keep track of the end of the ring 1815 * and set the end-of-ring bits as needed, 1816 * and we set the ownership bits in all except 1817 * the very first descriptor. (The caller will 1818 * set this descriptor later when it start 1819 * transmission or reception.) 1820 */ 1821 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1822 lastdesc = -1; 1823 for (seg = 0; seg < map->dm_nsegs; 1824 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1825 d = &sc->re_ldata.re_tx_list[curdesc]; 1826 #ifdef DIAGNOSTIC 1827 RE_TXDESCSYNC(sc, curdesc, 1828 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1829 cmdstat = le32toh(d->re_cmdstat); 1830 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1831 if (cmdstat & RE_TDESC_STAT_OWN) { 1832 panic("%s: tried to map busy TX descriptor", 1833 device_xname(sc->sc_dev)); 1834 } 1835 #endif 1836 1837 d->re_vlanctl = htole32(vlanctl); 1838 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1839 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1840 if (seg == 0) 1841 cmdstat |= RE_TDESC_CMD_SOF; 1842 else 1843 cmdstat |= RE_TDESC_CMD_OWN; 1844 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1845 cmdstat |= RE_TDESC_CMD_EOR; 1846 if (seg == nsegs - 1) { 1847 cmdstat |= RE_TDESC_CMD_EOF; 1848 lastdesc = curdesc; 1849 } 1850 d->re_cmdstat = htole32(cmdstat); 1851 RE_TXDESCSYNC(sc, curdesc, 1852 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1853 } 1854 if (__predict_false(pad)) { 1855 d = &sc->re_ldata.re_tx_list[curdesc]; 1856 d->re_vlanctl = htole32(vlanctl); 1857 re_set_bufaddr(d, RE_TXPADDADDR(sc)); 1858 cmdstat = re_flags | 1859 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1860 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1861 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1862 cmdstat |= RE_TDESC_CMD_EOR; 1863 d->re_cmdstat = htole32(cmdstat); 1864 RE_TXDESCSYNC(sc, curdesc, 1865 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1866 lastdesc = curdesc; 1867 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1868 } 1869 KASSERT(lastdesc != -1); 1870 1871 /* Transfer ownership of packet to the chip. */ 1872 1873 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1874 htole32(RE_TDESC_CMD_OWN); 1875 RE_TXDESCSYNC(sc, startdesc, 1876 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1877 1878 /* update info of TX queue and descriptors */ 1879 txq->txq_mbuf = m; 1880 txq->txq_descidx = lastdesc; 1881 txq->txq_nsegs = nsegs; 1882 1883 sc->re_ldata.re_txq_free--; 1884 sc->re_ldata.re_tx_free -= nsegs; 1885 sc->re_ldata.re_tx_nextfree = curdesc; 1886 1887 idx = RE_NEXT_TXQ(sc, idx); 1888 1889 /* 1890 * If there's a BPF listener, bounce a copy of this frame 1891 * to him. 1892 */ 1893 bpf_mtap(ifp, m, BPF_D_OUT); 1894 } 1895 1896 if (sc->re_ldata.re_txq_free < ofree) { 1897 /* 1898 * TX packets are enqueued. 1899 */ 1900 sc->re_ldata.re_txq_prodidx = idx; 1901 1902 /* 1903 * Start the transmitter to poll. 1904 * 1905 * RealTek put the TX poll request register in a different 1906 * location on the 8169 gigE chip. I don't know why. 1907 */ 1908 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1909 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1910 else 1911 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1912 1913 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) { 1914 /* 1915 * Use the countdown timer for interrupt moderation. 1916 * 'TX done' interrupts are disabled. Instead, we reset 1917 * the countdown timer, which will begin counting until 1918 * it hits the value in the TIMERINT register, and then 1919 * trigger an interrupt. Each time we write to the 1920 * TIMERCNT register, the timer count is reset to 0. 1921 */ 1922 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1923 } 1924 1925 /* 1926 * Set a timeout in case the chip goes out to lunch. 1927 */ 1928 ifp->if_timer = 5; 1929 } 1930 } 1931 1932 static int 1933 re_init(struct ifnet *ifp) 1934 { 1935 struct rtk_softc *sc = ifp->if_softc; 1936 int error; 1937 1938 RE_LOCK(sc); 1939 error = re_init_locked(sc); 1940 RE_UNLOCK(sc); 1941 1942 return error; 1943 } 1944 1945 static int 1946 re_init_locked(struct rtk_softc *sc) 1947 { 1948 struct ifnet *ifp = &sc->ethercom.ec_if; 1949 uint32_t rxcfg = 0; 1950 uint16_t cfg; 1951 int error; 1952 #ifdef RE_USE_EECMD 1953 const uint8_t *enaddr; 1954 uint32_t reg; 1955 #endif 1956 1957 sc->sc_if_flags = ifp->if_flags; 1958 1959 if ((error = re_enable(sc)) != 0) 1960 goto out; 1961 1962 /* 1963 * Cancel pending I/O and free all RX/TX buffers. 1964 */ 1965 re_stop_locked(sc, 0); 1966 1967 re_reset(sc); 1968 1969 /* 1970 * Enable C+ RX and TX mode, as well as VLAN stripping and 1971 * RX checksum offload. We must configure the C+ register 1972 * before all others. 1973 */ 1974 cfg = RE_CPLUSCMD_PCI_MRW; 1975 1976 /* 1977 * XXX: For old 8169 set bit 14. 1978 * For 8169S/8110S and above, do not set bit 14. 1979 */ 1980 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1981 cfg |= (0x1 << 14); 1982 1983 if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0) 1984 cfg |= RE_CPLUSCMD_VLANSTRIP; 1985 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx | 1986 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0) 1987 cfg |= RE_CPLUSCMD_RXCSUM_ENB; 1988 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) { 1989 cfg |= RE_CPLUSCMD_MACSTAT_DIS; 1990 cfg |= RE_CPLUSCMD_TXENB; 1991 } else 1992 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB; 1993 1994 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg); 1995 1996 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1997 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 1998 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) { 1999 CSR_WRITE_2(sc, RTK_IM, 0x0000); 2000 } else { 2001 CSR_WRITE_2(sc, RTK_IM, 0x5151); 2002 } 2003 } 2004 2005 DELAY(10000); 2006 2007 #ifdef RE_USE_EECMD 2008 /* 2009 * Init our MAC address. Even though the chipset 2010 * documentation doesn't mention it, we need to enter "Config 2011 * register write enable" mode to modify the ID registers. 2012 */ 2013 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 2014 enaddr = CLLADDR(ifp->if_sadl); 2015 reg = enaddr[0] | (enaddr[1] << 8) | 2016 (enaddr[2] << 16) | (enaddr[3] << 24); 2017 CSR_WRITE_4(sc, RTK_IDR0, reg); 2018 reg = enaddr[4] | (enaddr[5] << 8); 2019 CSR_WRITE_4(sc, RTK_IDR4, reg); 2020 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 2021 #endif 2022 2023 /* 2024 * For C+ mode, initialize the RX descriptors and mbufs. 2025 */ 2026 error = re_rx_list_init(sc); 2027 if (error != 0) { 2028 re_stop(ifp, 0); 2029 goto out; 2030 } 2031 re_tx_list_init(sc); 2032 2033 /* 2034 * Load the addresses of the RX and TX lists into the chip. 2035 */ 2036 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 2037 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 2038 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 2039 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 2040 2041 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 2042 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 2043 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 2044 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 2045 2046 if (sc->sc_quirk & RTKQ_RXDV_GATED) { 2047 CSR_WRITE_4(sc, RTK_MISC, 2048 CSR_READ_4(sc, RTK_MISC) & ~RTK_MISC_RXDV_GATED_EN); 2049 } 2050 2051 /* 2052 * Enable transmit and receive. 2053 */ 2054 if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) == 0) 2055 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 2056 2057 /* 2058 * Set the initial TX and RX configuration. 2059 */ 2060 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 2061 /* test mode is needed only for old 8169 */ 2062 CSR_WRITE_4(sc, RTK_TXCFG, 2063 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 2064 } else 2065 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 2066 2067 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 2068 2069 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 2070 2071 /* Set the individual bit to receive frames for this host only. */ 2072 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 2073 rxcfg |= RTK_RXCFG_RX_INDIV; 2074 if (sc->sc_quirk & RTKQ_EARLYOFF) 2075 rxcfg |= RTK_RXCFG_EARLYOFF; 2076 else if (sc->sc_quirk & RTKQ_RXDV_GATED) 2077 rxcfg |= RTK_RXCFG_EARLYOFFV2; 2078 2079 /* If we want promiscuous mode, set the allframes bit. */ 2080 if (ifp->if_flags & IFF_PROMISC) 2081 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 2082 else 2083 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 2084 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 2085 2086 /* 2087 * Set capture broadcast bit to capture broadcast frames. 2088 */ 2089 if (ifp->if_flags & IFF_BROADCAST) 2090 rxcfg |= RTK_RXCFG_RX_BROAD; 2091 else 2092 rxcfg &= ~RTK_RXCFG_RX_BROAD; 2093 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 2094 2095 /* 2096 * Program the multicast filter, if necessary. 2097 */ 2098 rtk_setmulti(sc); 2099 2100 /* 2101 * some chips require to enable TX/RX *AFTER* TX/RX configuration 2102 */ 2103 if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) != 0) 2104 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 2105 2106 /* 2107 * Enable interrupts. 2108 */ 2109 if (sc->re_testmode) 2110 CSR_WRITE_2(sc, RTK_IMR, 0); 2111 else if ((sc->sc_quirk & RTKQ_IM_HW) != 0) 2112 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_IM_HW); 2113 else 2114 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 2115 2116 /* Start RX/TX process. */ 2117 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 2118 #ifdef notdef 2119 /* Enable receiver and transmitter. */ 2120 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 2121 #endif 2122 2123 /* 2124 * Initialize the timer interrupt register so that 2125 * a timer interrupt will be generated once the timer 2126 * reaches a certain number of ticks. The timer is 2127 * reloaded on each transmit. This gives us TX interrupt 2128 * moderation, which dramatically improves TX frame rate. 2129 */ 2130 2131 unsigned defer; /* timer interval / ns */ 2132 unsigned period; /* busclock period / ns */ 2133 2134 /* 2135 * Maximum frame rate 2136 * 1500 byte PDU -> 81274 Hz 2137 * 46 byte PDU -> 1488096 Hz 2138 * 2139 * Deferring interrupts by up to 128us needs descriptors for 2140 * 1500 byte PDU -> 10.4 frames 2141 * 46 byte PDU -> 190.4 frames 2142 * 2143 */ 2144 defer = 128000; 2145 2146 if ((sc->sc_quirk & RTKQ_IM_HW) != 0) { 2147 period = 1; 2148 defer = 0; 2149 } else if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 2150 period = 8; 2151 } else { 2152 switch (CSR_READ_1(sc, RTK_CFG2_BUSFREQ) & 0x7) { 2153 case RTK_BUSFREQ_33MHZ: 2154 period = 30; 2155 break; 2156 case RTK_BUSFREQ_66MHZ: 2157 period = 15; 2158 break; 2159 default: 2160 /* lowest possible clock */ 2161 period = 60; 2162 break; 2163 } 2164 } 2165 2166 /* Timer Interrupt register address varies */ 2167 uint16_t re8139_reg; 2168 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 2169 re8139_reg = RTK_TIMERINT; 2170 else 2171 re8139_reg = RTK_TIMERINT_8169; 2172 CSR_WRITE_4(sc, re8139_reg, defer / period); 2173 2174 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 2175 /* 2176 * For 8169 gigE NICs, set the max allowed RX packet 2177 * size so we can receive jumbo frames. 2178 */ 2179 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 2180 } 2181 2182 if (sc->re_testmode) 2183 return 0; 2184 2185 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 2186 2187 ifp->if_flags |= IFF_RUNNING; 2188 ifp->if_flags &= ~IFF_OACTIVE; 2189 sc->sc_if_flags = ifp->if_flags; 2190 2191 callout_schedule(&sc->rtk_tick_ch, hz); 2192 2193 out: 2194 if (error) { 2195 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2196 sc->sc_if_flags = ifp->if_flags; 2197 ifp->if_timer = 0; 2198 printf("%s: interface not running\n", 2199 device_xname(sc->sc_dev)); 2200 } 2201 2202 return error; 2203 } 2204 2205 static int 2206 re_ioctl(struct ifnet *ifp, u_long command, void *data) 2207 { 2208 struct rtk_softc *sc = ifp->if_softc; 2209 struct ifreq *ifr = data; 2210 int error = 0, s; 2211 2212 switch (command) { 2213 case SIOCSIFMTU: 2214 /* 2215 * Disable jumbo frames if it's not supported. 2216 */ 2217 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 2218 ifr->ifr_mtu > ETHERMTU) { 2219 error = EINVAL; 2220 break; 2221 } 2222 2223 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2224 error = EINVAL; 2225 else if ((error = ifioctl_common(ifp, command, data)) == 2226 ENETRESET) 2227 error = 0; 2228 break; 2229 default: 2230 s = splnet(); 2231 error = ether_ioctl(ifp, command, data); 2232 splx(s); 2233 2234 if (error != ENETRESET) 2235 break; 2236 2237 error = 0; 2238 2239 if (command == SIOCSIFCAP) 2240 error = (*ifp->if_init)(ifp); 2241 else if (command == SIOCADDMULTI || command == SIOCADDMULTI) { 2242 RE_LOCK(sc); 2243 if (sc->sc_if_flags & IFF_RUNNING) 2244 rtk_setmulti(sc); 2245 RE_UNLOCK(sc); 2246 } 2247 break; 2248 } 2249 2250 return error; 2251 } 2252 2253 static int 2254 re_ifflags_cb(struct ethercom *ec) 2255 { 2256 struct ifnet * const ifp = &ec->ec_if; 2257 struct rtk_softc * const sc = ifp->if_softc; 2258 int ret = 0; 2259 u_short change; 2260 2261 KASSERT(IFNET_LOCKED(ifp)); 2262 RE_LOCK(sc); 2263 2264 change = ifp->if_flags ^ sc->sc_if_flags; 2265 sc->sc_if_flags = ifp->if_flags; 2266 2267 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 2268 ret = ENETRESET; 2269 } else if ((change & IFF_PROMISC) != 0) { 2270 if ((sc->sc_if_flags & IFF_RUNNING) != 0) 2271 rtk_setmulti(sc); 2272 } 2273 2274 RE_UNLOCK(sc); 2275 return ret; 2276 } 2277 2278 static void 2279 re_watchdog(struct ifnet *ifp) 2280 { 2281 struct rtk_softc *sc = ifp->if_softc; 2282 2283 RE_LOCK(sc); 2284 2285 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2286 if_statinc(ifp, if_oerrors); 2287 2288 re_txeof(sc); 2289 re_rxeof(sc); 2290 2291 re_init_locked(sc); 2292 2293 RE_UNLOCK(sc); 2294 } 2295 2296 /* 2297 * Stop the adapter and free any mbufs allocated to the 2298 * RX and TX lists. 2299 */ 2300 static void 2301 re_stop(struct ifnet *ifp, int disable) 2302 { 2303 struct rtk_softc *sc = ifp->if_softc; 2304 2305 RE_LOCK(sc); 2306 2307 re_stop_locked(sc, disable); 2308 2309 RE_UNLOCK(sc); 2310 } 2311 2312 static void 2313 re_stop_locked(struct rtk_softc *sc, int disable) 2314 { 2315 struct ifnet *ifp = &sc->ethercom.ec_if; 2316 int i; 2317 2318 callout_stop(&sc->rtk_tick_ch); 2319 2320 mii_down(&sc->mii); 2321 2322 /* 2323 * Disable accepting frames to put RX MAC into idle state. 2324 * Otherwise it's possible to get frames while stop command 2325 * execution is in progress and controller can DMA the frame 2326 * to already freed RX buffer during that period. 2327 */ 2328 CSR_WRITE_4(sc, RTK_RXCFG, CSR_READ_4(sc, RTK_RXCFG) & 2329 ~(RTK_RXCFG_RX_ALLPHYS | RTK_RXCFG_RX_INDIV | RTK_RXCFG_RX_MULTI | 2330 RTK_RXCFG_RX_BROAD)); 2331 2332 if (sc->sc_quirk & RTKQ_RXDV_GATED) { 2333 CSR_WRITE_4(sc, RTK_MISC, 2334 CSR_READ_4(sc, RTK_MISC) | RTK_MISC_RXDV_GATED_EN); 2335 } 2336 2337 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0) 2338 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB | 2339 RTK_CMD_RX_ENB); 2340 else 2341 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2342 DELAY(1000); 2343 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2344 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 2345 2346 if (sc->re_head != NULL) { 2347 m_freem(sc->re_head); 2348 sc->re_head = sc->re_tail = NULL; 2349 } 2350 2351 /* Free the TX list buffers. */ 2352 for (i = 0; i < RE_TX_QLEN(sc); i++) { 2353 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 2354 bus_dmamap_unload(sc->sc_dmat, 2355 sc->re_ldata.re_txq[i].txq_dmamap); 2356 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 2357 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 2358 sc->re_ldata.re_txq[i].txq_nsegs = 0; 2359 } 2360 } 2361 2362 /* Free the RX list buffers. */ 2363 for (i = 0; i < RE_RX_DESC_CNT(sc); i++) { 2364 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 2365 bus_dmamap_unload(sc->sc_dmat, 2366 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2367 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2368 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2369 } 2370 } 2371 2372 if (disable) 2373 re_disable(sc); 2374 2375 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2376 ifp->if_timer = 0; 2377 sc->sc_if_flags = ifp->if_flags; 2378 } 2379
Indexes created Sun Oct 25 00:26:45 UTC 2026