Lines Matching refs:__u64
177 __u64 bo_size;
179 __u64 alignment;
181 __u64 domains;
183 __u64 domain_flags;
214 __u64 bo_info_ptr;
302 __u64 flags;
332 __u64 flags;
368 __u64 addr;
369 __u64 size;
422 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
424 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
437 __u64 flags;
439 __u64 tiling_info;
453 __u64 addr_ptr;
467 __u64 timeout;
487 __u64 handle;
489 __u64 timeout;
498 __u64 status;
511 __u64 seq_no;
516 __u64 fences;
519 __u64 timeout_ns;
542 __u64 value;
588 __u64 va_address;
590 __u64 offset_in_bo;
592 __u64 map_size;
627 __u64 chunk_data;
637 /** this points to __u64 * which point to cs chunks */
638 __u64 chunks;
642 __u64 handle;
683 __u64 va_start;
699 __u64 handle;
714 __u64 point;
742 __u64 shadow_va;
743 __u64 csa_va;
744 __u64 gds_va;
745 __u64 flags;
959 __u64 return_pointer;
1027 __u64 vram_size;
1028 __u64 vram_cpu_accessible_size;
1029 __u64 gtt_size;
1034 __u64 total_heap_size;
1037 __u64 usable_heap_size;
1045 __u64 heap_usage;
1051 __u64 max_allocation;
1101 __u64 max_engine_clock;
1102 __u64 max_memory_clock;
1114 __u64 ids_flags;
1116 __u64 virtual_address_offset;
1118 __u64 virtual_address_max;
1135 __u64 prim_buf_gpu_addr;
1137 __u64 pos_buf_gpu_addr;
1139 __u64 cntl_sb_buf_gpu_addr;
1141 __u64 param_buf_gpu_addr;
1165 __u64 high_va_offset;
1167 __u64 high_va_max;
1171 __u64 tcc_disabled_mask;
1172 __u64 min_engine_clock;
1173 __u64 min_memory_clock;
1181 __u64 mall_size; /* AKA infinity cache */
1199 __u64 capabilities_flags;
1268 __u64 addr;