Cross Reference: /xsrc/external/mit/libdrm/dist/radeon/radeon

Lines Matching refs:tile_mode
1288                              unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode)
1353                 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D;
1356                 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_2AA;
1359                 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_4AA;
1362                 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_8AA;
1370                 *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1373                 *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1381                 *tile_mode = SI_TILE_MODE_COLOR_2D_8BPP;
1384                 *tile_mode = SI_TILE_MODE_COLOR_2D_16BPP;
1387                 *tile_mode = SI_TILE_MODE_COLOR_2D_32BPP;
1391                 *tile_mode = SI_TILE_MODE_COLOR_2D_64BPP;
1398         gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode];
1406             *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
1408             *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
1410             *tile_mode = SI_TILE_MODE_COLOR_1D;
1415         *tile_mode = SI_TILE_MODE_COLOR_LINEAR_ALIGNED;
1519                                           unsigned tile_mode,
1544             surf->tiling_index[i] = tile_mode;
1553                               unsigned bpe, unsigned tile_mode,
1588                 surf->tiling_index[i] = tile_mode;
1590                 surf->stencil_tiling_index[i] = tile_mode;
1592                 surf->stencil_tiling_index[i] = tile_mode;
1601                                        unsigned tile_mode, unsigned stencil_tile_mode)
1605     r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0);
1620                               unsigned bpe, unsigned tile_mode,
1664             switch (tile_mode) {
1669                 tile_mode = SI_TILE_MODE_COLOR_1D;
1673                 tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
1676                 tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
1681             return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
1690                 surf->tiling_index[i] = tile_mode;
1692                 surf->stencil_tiling_index[i] = tile_mode;
1694                 surf->stencil_tiling_index[i] = tile_mode;
1703                                        unsigned tile_mode, unsigned stencil_tile_mode)
1710     gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
1713     r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, surf->tile_split, 0, 0);
1728     unsigned mode, tile_mode, stencil_tile_mode;
1754     r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1768         r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
1771         r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1774         r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1788     unsigned mode, tile_mode, stencil_tile_mode;
1800     return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1859                               unsigned tile_mode,
1867     uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
2118                               unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode)
2160                 *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64;
2164                 *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128;
2167                 *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256;
2174                 *stencil_tile_mode = *tile_mode;
2182             *tile_mode = CIK_TILE_MODE_COLOR_2D_SCANOUT;
2184             *tile_mode = CIK_TILE_MODE_COLOR_2D;
2189                           !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), *tile_mode,
2199             *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
2201             *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
2203             *tile_mode = SI_TILE_MODE_COLOR_1D;
2209         *tile_mode = SI_TILE_MODE_COLOR_LINEAR_ALIGNED;
2218                                unsigned bpe, unsigned tile_mode,
2267             switch (tile_mode) {
2269                 tile_mode = SI_TILE_MODE_COLOR_1D;
2272                 tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
2279                 tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
2284             return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
2293                 surf->tiling_index[i] = tile_mode;
2295                 surf->stencil_tiling_index[i] = tile_mode;
2297                 surf->stencil_tiling_index[i] = tile_mode;
2306                                         unsigned tile_mode, unsigned stencil_tile_mode)
2312                         !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), tile_mode,
2315     r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode,
2333     unsigned mode, tile_mode, stencil_tile_mode;
2359     r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2373         r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
2376         r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2379         r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2393     unsigned mode, tile_mode, stencil_tile_mode;
2405     return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);