Lines Matching defs:ibs_request
75 struct amdgpu_cs_request *ibs_request);
852 struct amdgpu_cs_request ibs_request = {0};
908 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
909 ibs_request.number_of_ibs = 2;
910 ibs_request.ibs = ib_info;
911 ibs_request.resources = bo_list;
912 ibs_request.fence_info.handle = NULL;
914 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
921 fence_status.fence = ibs_request.seq_no;
950 struct amdgpu_cs_request ibs_request = {0};
999 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
1000 ibs_request.number_of_ibs = 2;
1001 ibs_request.ibs = ib_info;
1002 ibs_request.resources = bo_list;
1003 ibs_request.fence_info.handle = NULL;
1005 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
1012 fence_status.fence = ibs_request.seq_no;
1054 struct amdgpu_cs_request *ibs_request;
1068 ibs_request = calloc(1, sizeof(*ibs_request));
1069 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1161 ib_info, ibs_request);
1185 free(ibs_request);
1216 struct amdgpu_cs_request ibs_request[2] = {0};
1265 ibs_request[0].ip_type = AMDGPU_HW_IP_DMA;
1266 ibs_request[0].number_of_ibs = 1;
1267 ibs_request[0].ibs = &ib_info[0];
1268 ibs_request[0].resources = bo_list[0];
1269 ibs_request[0].fence_info.handle = NULL;
1270 r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1);
1282 ibs_request[1].ip_type = gc_ip_type;
1283 ibs_request[1].number_of_ibs = 1;
1284 ibs_request[1].ibs = &ib_info[1];
1285 ibs_request[1].resources = bo_list[1];
1286 ibs_request[1].fence_info.handle = NULL;
1288 r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[1], 1);
1294 fence_status.fence = ibs_request[1].seq_no;
1306 ibs_request[0].ip_type = gc_ip_type;
1307 ibs_request[0].number_of_ibs = 1;
1308 ibs_request[0].ibs = &ib_info[0];
1309 ibs_request[0].resources = bo_list[0];
1310 ibs_request[0].fence_info.handle = NULL;
1311 r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1);
1323 ibs_request[1].ip_type = gc_ip_type;
1324 ibs_request[1].number_of_ibs = 1;
1325 ibs_request[1].ibs = &ib_info[1];
1326 ibs_request[1].resources = bo_list[1];
1327 ibs_request[1].fence_info.handle = NULL;
1328 r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request[1], 1);
1335 fence_status.fence = ibs_request[1].seq_no;
1363 struct amdgpu_cs_request ibs_request;
1398 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
1399 ibs_request.ip_type = AMDGPU_HW_IP_COMPUTE;
1400 ibs_request.ring = instance;
1401 ibs_request.number_of_ibs = 1;
1402 ibs_request.ibs = &ib_info;
1403 ibs_request.resources = bo_list;
1404 ibs_request.fence_info.handle = NULL;
1407 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
1414 fence_status.fence = ibs_request.seq_no;
1462 * pm4_src, resources, ib_info, and ibs_request
1463 * submit command stream described in ibs_request and wait for this IB accomplished
1472 struct amdgpu_cs_request *ibs_request,
1489 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1508 ibs_request->ip_type = ip_type;
1509 ibs_request->ring = instance;
1510 ibs_request->number_of_ibs = 1;
1511 ibs_request->ibs = ib_info;
1512 ibs_request->fence_info.handle = NULL;
1518 NULL, &ibs_request->resources);
1521 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1524 r = amdgpu_cs_submit(context_handle, 0, ibs_request, 1);
1527 r = amdgpu_bo_list_destroy(ibs_request->resources);
1532 fence_status.ring = ibs_request->ring;
1534 fence_status.fence = ibs_request->seq_no;
1554 struct amdgpu_cs_request *ibs_request)
1559 ibs_request, false);
1574 struct amdgpu_cs_request *ibs_request;
1589 ibs_request = calloc(1, sizeof(*ibs_request));
1590 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1653 ibs_request, secure);
1683 ibs_request, true);
1707 ibs_request, true);
1740 ibs_request, true);
1753 free(ibs_request);
1783 struct amdgpu_cs_request *ibs_request;
1797 ibs_request = calloc(1, sizeof(*ibs_request));
1798 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
1877 ib_info, ibs_request);
1893 free(ibs_request);
1916 struct amdgpu_cs_request *ibs_request;
1930 ibs_request = calloc(1, sizeof(*ibs_request));
1931 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
2031 ib_info, ibs_request);
2051 free(ibs_request);
2078 struct amdgpu_cs_request ibs_request[2] = {0};
2136 ibs_request[i].ip_type = AMDGPU_HW_IP_GFX;
2137 ibs_request[i].number_of_ibs = 2;
2138 ibs_request[i].ibs = ib_info;
2139 ibs_request[i].resources = bo_list;
2140 ibs_request[i].fence_info.handle = NULL;
2143 r = amdgpu_cs_submit(context_handle, 0,ibs_request, ib_cs_num);
2150 fence_status[i].fence = ibs_request[i].seq_no;
2190 struct amdgpu_cs_request *ibs_request;
2200 ibs_request = calloc(1, sizeof(*ibs_request));
2201 CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
2252 ib_info, ibs_request);
2257 free(ibs_request);
2281 struct amdgpu_cs_request ibs_request;
2402 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
2403 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
2404 ibs_request.ring = 0;
2405 ibs_request.number_of_ibs = 1;
2406 ibs_request.ibs = &ib_info;
2407 ibs_request.resources = bo_list;
2408 ibs_request.fence_info.handle = NULL;
2410 r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request, 1);
2412 seq_no = ibs_request.seq_no;
2431 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
2432 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
2433 ibs_request.ring = 0;
2434 ibs_request.number_of_ibs = 1;
2435 ibs_request.ibs = &ib_info;
2436 ibs_request.resources = bo_list;
2437 ibs_request.fence_info.handle = NULL;
2439 ibs_request.number_of_dependencies = 1;
2441 ibs_request.dependencies = calloc(1, sizeof(*ibs_request.dependencies));
2442 ibs_request.dependencies[0].context = context_handle[1];
2443 ibs_request.dependencies[0].ip_instance = 0;
2444 ibs_request.dependencies[0].ring = 0;
2445 ibs_request.dependencies[0].fence = seq_no;
2448 r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request, 1);
2457 fence_status.fence = ibs_request.seq_no;
2478 free(ibs_request.dependencies);