Cross Reference: /xsrc/external/mit/xf86-video-ast/dist/src/ast

Lines Matching refs:UCHAR
691         SetIndexReg(CRTC_PORT, 0x8C, (UCHAR) ((ulColorIndex & 0x0F) << 4));
692         SetIndexReg(CRTC_PORT, 0x8D, (UCHAR) (ulRefreshRateIndex & 0xFF));
693         SetIndexReg(CRTC_PORT, 0x8E, (UCHAR) (ulModeID & 0xFF));
700             SetIndexReg(CRTC_PORT, 0x92, (UCHAR) (pScrn->bitsPerPixel) );
701             SetIndexReg(CRTC_PORT, 0x93, (UCHAR) (mode->Clock / 1000) );
702             SetIndexReg(CRTC_PORT, 0x94, (UCHAR) (mode->CrtcHDisplay) );
703             SetIndexReg(CRTC_PORT, 0x95, (UCHAR) (mode->CrtcHDisplay >> 8) );	/* color depth */
704             SetIndexReg(CRTC_PORT, 0x96, (UCHAR) (mode->CrtcVDisplay) );
705             SetIndexReg(CRTC_PORT, 0x97, (UCHAR) (mode->CrtcVDisplay >> 8) );	/* color depth */
718     UCHAR jReg;
733         SetIndexReg(SEQ_PORT,(UCHAR) (i+1), jReg);
741         SetIndexReg(CRTC_PORT,(UCHAR) i, jReg);
749         SetReg(AR_PORT_WRITE, (UCHAR) i);
762         SetIndexReg(GR_PORT,(UCHAR) i, jReg);
774     UCHAR jReg05, jReg07, jReg09, jRegAC, jRegAD, jRegAE;
789     SetIndexRegMask(CRTC_PORT,0x00, 0x00, (UCHAR) usTemp);
792     SetIndexRegMask(CRTC_PORT,0x01, 0x00, (UCHAR) usTemp);
795     SetIndexRegMask(CRTC_PORT,0x02, 0x00, (UCHAR) usTemp);
799     SetIndexRegMask(CRTC_PORT,0x03, 0xE0, (UCHAR) (usTemp & 0x1F));
802     SetIndexRegMask(CRTC_PORT,0x04, 0x00, (UCHAR) (usTemp));
805     SetIndexRegMask(CRTC_PORT,0x05, 0x60, (UCHAR) ((usTemp & 0x1F) | jReg05));
807     SetIndexRegMask(CRTC_PORT,0xAC, 0x00, (UCHAR) jRegAC);
808     SetIndexRegMask(CRTC_PORT,0xAD, 0x00, (UCHAR) jRegAD);
815     SetIndexRegMask(CRTC_PORT,0x06, 0x00, (UCHAR) usTemp);
820     SetIndexRegMask(CRTC_PORT,0x10, 0x00, (UCHAR) usTemp);
824     SetIndexRegMask(CRTC_PORT,0x11, 0x70, (UCHAR) (usTemp & 0x0F));
829     SetIndexRegMask(CRTC_PORT,0x12, 0x00, (UCHAR) usTemp);
834     SetIndexRegMask(CRTC_PORT,0x15, 0x00, (UCHAR) usTemp);
837     SetIndexRegMask(CRTC_PORT,0x16, 0x00, (UCHAR) usTemp);
839     SetIndexRegMask(CRTC_PORT,0x07, 0x00, (UCHAR) jReg07);
840     SetIndexRegMask(CRTC_PORT,0x09, 0xDF, (UCHAR) jReg09);
841     SetIndexRegMask(CRTC_PORT,0xAE, 0x00, (UCHAR) (jRegAE | 0x80));	/* disable line compare */
866     SetIndexReg(CRTC_PORT,0x13, (UCHAR) (usOffset & 0xFF));
867     SetIndexReg(CRTC_PORT,0xB0, (UCHAR) ((usOffset >> 8) & 0x3F));
907     UCHAR jRegA0, jRegA3, jRegA8;
931     SetIndexRegMask(CRTC_PORT,0xA0, 0x8F, (UCHAR) jRegA0);
932     SetIndexRegMask(CRTC_PORT,0xA3, 0xF0, (UCHAR) jRegA3);
933     SetIndexRegMask(CRTC_PORT,0xA8, 0xFD, (UCHAR) jRegA8);
936     UCHAR jRegA2 = 0x80;
939     SetIndexRegMask(CRTC_PORT,0xA2, 0x3F, (UCHAR) jRegA2);
965     UCHAR jReg;
982     UCHAR DACR, DACG, DACB;
1170 static void SetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex, UCHAR jData )
1226 static UCHAR GetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex)
1229     UCHAR jData;
1280     jData = (UCHAR) ((ulData & 0xFF00) >> 8);
1291     UCHAR jReg;