Cross Reference: /xsrc/external/mit/xf86-video-ast/dist/src/ast

Lines Matching defs:jReg
256     UCHAR jReg;
318         GetIndexRegMask(CRTC_PORT, 0x99, 0xFC, jReg);			/* D[1:0]: Reserved Video Buffer */
319         jReg |= 0x02;										    /* 2MB */
320         SetIndexReg(CRTC_PORT, 0x99, jReg);
539    UCHAR jReg;
544    GetIndexRegMask(CRTC_PORT, 0xAA, 0xFF, jReg);
545    switch (jReg & 0x03)
563    GetIndexRegMask(CRTC_PORT, 0x99, 0xFF, jReg);
564    switch (jReg & 0x03)
584    UCHAR jReg;
608        GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
609        if ((jReg & 0x08) && (pAST->jChipType == AST2000))
611        else if ((jReg & 0x08) && (pScrn->bitsPerPixel == 8))
674    UCHAR jReg;
677    GetIndexRegMask(CRTC_PORT, 0x90, 0xFF, jReg);
678    if (jReg & 0x10)
685    GetIndexRegMask(CRTC_PORT, 0xA3, 0xFF, jReg);
686    if (jReg & 0x80)
691        GetIndexRegMask(CRTC_PORT, 0xD1, 0x0E, jReg);
692        switch (jReg)
723        GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
724        if (!(jReg & 0x80))
726        else if (jReg & 0x01)
1125     UCHAR i, jIndex, jReg, *pjExtRegInfo;
1163     jReg = 0x04;
1165         jReg |= 0x20;
1166     SetIndexRegMask(CRTC_PORT,0xB6, 0xFF, jReg);
1493     UCHAR jReg;
1496     GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
1498     if ((jReg & 0x80) == 0)			/* VGA only */
1596         GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
1597     } while ((jReg & 0x40) == 0);
2888     UCHAR jReg;
2890     GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
2892     if ((jReg & 0x80) == 0)			/* VGA only */
2938         GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
2939     } while ((jReg & 0x40) == 0);
3379     UCHAR jReg;
3381     GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
3383     if ((jReg & 0x80) == 0)			/* VGA only */
3411         GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
3412     } while ((jReg & 0x40) == 0);
3457     UCHAR jReg;
3463     GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg);
3464     if (!(jReg & 0x80))														/* Init SCU DVO Settings */
3525     UCHAR jReg;
3530         GetIndexRegMask(CRTC_PORT, 0xD1, 0xFF, jReg);      /* D[1]: DVO Enable */
3531         switch (jReg & 0x0E)	/* D[11:9] */
3956     UCHAR jReg;
3958     jReg = inb(pAST->RelocateIO + 0x43);
3959     if (jReg != 0x01)
3970     jReg = GetReg(VGA_ENABLE_PORT);
3971     if (jReg == 0xFF)	/* MMIO Access is disabled */