Lines Matching refs:SetIndexRegMask
109 SetIndexRegMask(CRTC_PORT, 0x9B, 0x00, SendACK);
119 SetIndexRegMask(CRTC_PORT, 0x9B, 0x00, SendACK);
162 SetIndexRegMask(CRTC_PORT, 0x9B, ~0x40, 0x40);
169 SetIndexRegMask(CRTC_PORT, 0x9B, ~0x40, 0x00);
180 SetIndexRegMask(CRTC_PORT, 0x9a, 0x00, data);
205 SetIndexRegMask(CRTC_PORT, 0x9a, 0x00, data);
414 SetIndexRegMask(CRTC_PORT,0xA1, 0xFF, 0x04);
418 SetIndexRegMask(CRTC_PORT,0xA2, 0xFF, 0x80);
782 SetIndexRegMask(SEQ_PORT,0x01, 0xDF, 0x20);
800 SetIndexRegMask(SEQ_PORT,0x01, 0xDF, 0x00);
934 SetIndexRegMask(SEQ_PORT,0x01, 0xDF, SEQ01);
935 SetIndexRegMask(CRTC_PORT,0xB6, 0xFC, CRB6);
1149 SetIndexRegMask(CRTC_PORT,jIndex, 0x00, *(UCHAR *) (pjExtRegInfo));
1156 SetIndexRegMask(CRTC_PORT,0xA1, 0xFF, 0x03);
1159 SetIndexRegMask(CRTC_PORT,0x8C, 0x00, 0x01);
1160 SetIndexRegMask(CRTC_PORT,0xB7, 0x00, 0x00);
1166 SetIndexRegMask(CRTC_PORT,0xB6, 0xFF, jReg);
1176 SetIndexRegMask(CRTC_PORT, 0xbc, 0x00, 0x40);
1177 SetIndexRegMask(CRTC_PORT, 0xbd, 0x00, 0x38);
1178 SetIndexRegMask(CRTC_PORT, 0xbe, 0x00, 0x3a);
1179 SetIndexRegMask(CRTC_PORT, 0xbf, 0x00, 0x38);
1180 SetIndexRegMask(CRTC_PORT, 0xcf, 0x00, 0x70);
1181 SetIndexRegMask(CRTC_PORT, 0xb5, 0x00, 0xa8);
1182 SetIndexRegMask(CRTC_PORT, 0xbb, 0x00, 0x43);
3516 SetIndexRegMask(CRTC_PORT, 0xA3, 0xCF, 0x80); /* enable DVO, single-edge */
3606 SetIndexRegMask(CRTC_PORT, 0xB7, 0xFE, ujCRB7);
3622 SetIndexRegMask(CRTC_PORT, 0xB7, 0xFB, ujCRB7);