Cross Reference: /xsrc/external/mit/xf86-video-ati-kms/dist/src/evergreen

Lines Matching defs:dst_obj
103     evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
104     evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
105     evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
125     cb_conf.w = accel_state->dst_obj.pitch;
126     cb_conf.h = accel_state->dst_obj.height;
128     cb_conf.bo = accel_state->dst_obj.bo;
129     cb_conf.surface = accel_state->dst_obj.surface;
131     if (accel_state->dst_obj.bpp == 8) {
134     } else if (accel_state->dst_obj.bpp == 16) {
159     if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
164     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
175     if (accel_state->dst_obj.bpp == 16) {
183     } else if (accel_state->dst_obj.bpp == 8) {
282     evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
283     evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
284     evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
356     cb_conf.w = accel_state->dst_obj.pitch;
357     cb_conf.h = accel_state->dst_obj.height;
359     cb_conf.bo = accel_state->dst_obj.bo;
360     cb_conf.surface = accel_state->dst_obj.surface;
361     if (accel_state->dst_obj.bpp == 8) {
364     } else if (accel_state->dst_obj.bpp == 16) {
383     if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
388     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
455     struct r600_accel_object src_obj, dst_obj;
464     dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
470     dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
471     dst_obj.surface = radeon_get_pixmap_surface(pDst);
473     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
475     if (src_obj.bo == dst_obj.bo)
483     dst_obj.width = pDst->drawable.width;
484     dst_obj.height = pDst->drawable.height;
485     dst_obj.bpp = pDst->drawable.bitsPerPixel;
487 	dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
489 	dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
494 			   &dst_obj,
501 				       drmmode_get_height_align(pScrn, accel_state->dst_obj.tiling_flags));
502 	unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
504 	if (accel_state->dst_obj.surface)
505 		size = accel_state->dst_obj.surface->bo_size;
587 	uint32_t orig_dst_domain = accel_state->dst_obj.domain;
590 	uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
591 	struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
593 	struct radeon_surface *orig_dst_surface = accel_state->dst_obj.surface;
597 	accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
598 	accel_state->dst_obj.bo = accel_state->copy_area_bo;
599 	accel_state->dst_obj.tiling_flags = 0;
601 	accel_state->dst_obj.surface = NULL;
611 	accel_state->dst_obj.domain = orig_dst_domain;
612 	accel_state->dst_obj.bo = orig_bo;
613 	accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
615 	accel_state->dst_obj.surface = orig_dst_surface;
1296     struct r600_accel_object src_obj, mask_obj, dst_obj;
1314     dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
1315     dst_obj.surface = radeon_get_pixmap_surface(pDst);
1316     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
1317     dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
1318     dst_obj.width = pDst->drawable.width;
1319     dst_obj.height = pDst->drawable.height;
1320     dst_obj.bpp = pDst->drawable.bitsPerPixel;
1322 	dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
1324 	dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
1358 		&dst_obj,
1382     evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1383     evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1384     evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1434     cb_conf.w = accel_state->dst_obj.pitch;
1435     cb_conf.h = accel_state->dst_obj.height;
1438     cb_conf.bo = accel_state->dst_obj.bo;
1439     cb_conf.surface = accel_state->dst_obj.surface;
1474     if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
1480     switch (dst_obj.bpp) {
1491     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
1669     struct r600_accel_object src_obj, dst_obj;
1709     dst_obj.pitch = dst_pitch_hw;
1710     dst_obj.width = pDst->drawable.width;
1711     dst_obj.height = pDst->drawable.height;
1712     dst_obj.bpp = bpp;
1713     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
1714     dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
1715     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
1716     dst_obj.surface = radeon_get_pixmap_surface(pDst);
1721 			   &dst_obj,
1785     struct r600_accel_object src_obj, dst_obj;
1832     accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
1833     radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, accel_state->dst_obj.domain);
1848     dst_obj.pitch = scratch_pitch;
1849     dst_obj.width = w;
1850     dst_obj.height = h;
1851     dst_obj.bo = scratch;
1852     dst_obj.bpp = bpp;
1853     dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
1854     dst_obj.tiling_flags = 0;
1855     dst_obj.surface = NULL;
1860 			   &dst_obj,
2107     info->accel_state->dst_obj.bo = NULL;