Cross Reference: /xsrc/external/mit/xf86-video-ati-kms/dist/src/evergreen

Lines Matching defs:src_obj
305     tex_res.w                   = accel_state->src_obj[0].width;
306     tex_res.h                   = accel_state->src_obj[0].height;
307     tex_res.pitch               = accel_state->src_obj[0].pitch;
313     tex_res.bo                  = accel_state->src_obj[0].bo;
314     tex_res.mip_bo              = accel_state->src_obj[0].bo;
315     tex_res.surface             = accel_state->src_obj[0].surface;
316     if (accel_state->src_obj[0].bpp == 8) {
322     } else if (accel_state->src_obj[0].bpp == 16) {
339     if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
342     evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
455     struct r600_accel_object src_obj, dst_obj;
465     src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
469     src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
472     src_obj.surface = radeon_get_pixmap_surface(pSrc);
474     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
475     if (src_obj.bo == dst_obj.bo)
478     src_obj.width = pSrc->drawable.width;
479     src_obj.height = pSrc->drawable.height;
480     src_obj.bpp = pSrc->drawable.bitsPerPixel;
481     src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
492 			   &src_obj,
588 	uint32_t orig_src_domain = accel_state->src_obj[0].domain;
589 	uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
594 	struct radeon_surface *orig_src_surface = accel_state->src_obj[0].surface;
607 	accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
608 	accel_state->src_obj[0].bo = accel_state->copy_area_bo;
609 	accel_state->src_obj[0].tiling_flags = 0;
610 	accel_state->src_obj[0].surface = NULL;
621 	accel_state->src_obj[0].domain = orig_src_domain;
622 	accel_state->src_obj[0].bo = orig_bo;
623 	accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
624 	accel_state->src_obj[0].surface = orig_src_surface;
878     tex_res.pitch               = accel_state->src_obj[unit].pitch;
885     tex_res.bo                  = accel_state->src_obj[unit].bo;
886     tex_res.mip_bo              = accel_state->src_obj[unit].bo;
887     tex_res.surface             = accel_state->src_obj[unit].surface;
890     switch (accel_state->src_obj[unit].bpp) {
1021     if ((accel_state->src_obj[unit].tiling_flags & RADEON_TILING_MASK) ==
1024     evergreen_set_tex_resource  (pScrn, &tex_res, accel_state->src_obj[unit].domain);
1296     struct r600_accel_object src_obj, mask_obj, dst_obj;
1304 	src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
1305 	src_obj.surface = radeon_get_pixmap_surface(pSrc);
1306 	src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
1307 	src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
1308 	src_obj.width = pSrc->drawable.width;
1309 	src_obj.height = pSrc->drawable.height;
1310 	src_obj.bpp = pSrc->drawable.bitsPerPixel;
1311 	src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
1356 		pSrc ? &src_obj : NULL,
1669     struct r600_accel_object src_obj, dst_obj;
1700     src_obj.pitch = scratch_pitch;
1701     src_obj.width = w;
1702     src_obj.height = h;
1703     src_obj.bpp = bpp;
1704     src_obj.domain = RADEON_GEM_DOMAIN_GTT;
1705     src_obj.bo = scratch;
1706     src_obj.tiling_flags = 0;
1707     src_obj.surface = NULL;
1719 			   &src_obj,
1785     struct r600_accel_object src_obj, dst_obj;
1830     accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
1831     radeon_add_pixmap(info->cs, pSrc, info->accel_state->src_obj[0].domain, 0);
1839     src_obj.pitch = src_pitch_hw;
1840     src_obj.width = pSrc->drawable.width;
1841     src_obj.height = pSrc->drawable.height;
1842     src_obj.bpp = bpp;
1843     src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
1844     src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
1845     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
1846     src_obj.surface = radeon_get_pixmap_surface(pSrc);
1858 			   &src_obj,
2105     info->accel_state->src_obj[0].bo = NULL;
2106     info->accel_state->src_obj[1].bo = NULL;