Lines Matching refs:accel_state
60 struct radeon_accel_state *accel_state = info->accel_state;
88 accel_state->solid_vs_offset, accel_state->solid_ps_offset,
97 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
98 radeon_vbo_check(pScrn, &accel_state->cbuf, 256);
103 evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
104 evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
105 evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
108 vs_conf.shader_addr = accel_state->vs_mc_addr;
109 vs_conf.shader_size = accel_state->vs_size;
112 vs_conf.bo = accel_state->shaders_bo;
115 ps_conf.shader_addr = accel_state->ps_mc_addr;
116 ps_conf.shader_size = accel_state->ps_size;
121 ps_conf.bo = accel_state->shaders_bo;
125 cb_conf.w = accel_state->dst_obj.pitch;
126 cb_conf.h = accel_state->dst_obj.height;
128 cb_conf.bo = accel_state->dst_obj.bo;
129 cb_conf.surface = accel_state->dst_obj.surface;
131 if (accel_state->dst_obj.bpp == 8) {
134 } else if (accel_state->dst_obj.bpp == 16) {
150 if (accel_state->planemask & 0x000000ff)
152 if (accel_state->planemask & 0x0000ff00)
154 if (accel_state->planemask & 0x00ff0000)
156 if (accel_state->planemask & 0xff000000)
158 cb_conf.rop = accel_state->rop;
159 if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
164 evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
171 ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
172 ps_const_conf.bo = accel_state->cbuf.vb_bo;
173 ps_const_conf.const_addr = accel_state->cbuf.vb_offset;
175 if (accel_state->dst_obj.bpp == 16) {
183 } else if (accel_state->dst_obj.bpp == 8) {
199 radeon_vbo_commit(pScrn, &accel_state->cbuf);
202 if (accel_state->vsync)
205 accel_state->dst_pix = pPix;
206 accel_state->fg = fg;
216 struct radeon_accel_state *accel_state = info->accel_state;
218 if (accel_state->vsync)
220 accel_state->vline_crtc,
221 accel_state->vline_y1,
222 accel_state->vline_y2);
232 struct radeon_accel_state *accel_state = info->accel_state;
236 EVERGREENDoneSolid(info->accel_state->dst_pix);
238 EVERGREENPrepareSolid(accel_state->dst_pix,
239 accel_state->rop,
240 accel_state->planemask,
241 accel_state->fg);
244 if (accel_state->vsync)
247 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 8);
258 radeon_vbo_commit(pScrn, &accel_state->vbo);
265 struct radeon_accel_state *accel_state = info->accel_state;
277 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
282 evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
283 evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
284 evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
287 vs_conf.shader_addr = accel_state->vs_mc_addr;
288 vs_conf.shader_size = accel_state->vs_size;
291 vs_conf.bo = accel_state->shaders_bo;
294 ps_conf.shader_addr = accel_state->ps_mc_addr;
295 ps_conf.shader_size = accel_state->ps_size;
300 ps_conf.bo = accel_state->shaders_bo;
305 tex_res.w = accel_state->src_obj[0].width;
306 tex_res.h = accel_state->src_obj[0].height;
307 tex_res.pitch = accel_state->src_obj[0].pitch;
312 tex_res.size = accel_state->src_size[0];
313 tex_res.bo = accel_state->src_obj[0].bo;
314 tex_res.mip_bo = accel_state->src_obj[0].bo;
315 tex_res.surface = accel_state->src_obj[0].surface;
316 if (accel_state->src_obj[0].bpp == 8) {
322 } else if (accel_state->src_obj[0].bpp == 16) {
339 if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
342 evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
356 cb_conf.w = accel_state->dst_obj.pitch;
357 cb_conf.h = accel_state->dst_obj.height;
359 cb_conf.bo = accel_state->dst_obj.bo;
360 cb_conf.surface = accel_state->dst_obj.surface;
361 if (accel_state->dst_obj.bpp == 8) {
364 } else if (accel_state->dst_obj.bpp == 16) {
374 if (accel_state->planemask & 0x000000ff)
376 if (accel_state->planemask & 0x0000ff00)
378 if (accel_state->planemask & 0x00ff0000)
380 if (accel_state->planemask & 0xff000000)
382 cb_conf.rop = accel_state->rop;
383 if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
388 evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
405 struct radeon_accel_state *accel_state = info->accel_state;
407 if (accel_state->vsync)
409 accel_state->vline_crtc,
410 accel_state->vline_y1,
411 accel_state->vline_y2);
423 struct radeon_accel_state *accel_state = info->accel_state;
426 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
443 radeon_vbo_commit(pScrn, &accel_state->vbo);
454 struct radeon_accel_state *accel_state = info->accel_state;
467 accel_state->same_surface = FALSE;
476 accel_state->same_surface = TRUE;
495 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
499 if (accel_state->same_surface == TRUE) {
501 drmmode_get_height_align(pScrn, accel_state->dst_obj.tiling_flags));
502 unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
504 if (accel_state->dst_obj.surface)
505 size = accel_state->dst_obj.surface->bo_size;
507 if (accel_state->copy_area_bo) {
508 radeon_bo_unref(accel_state->copy_area_bo);
509 accel_state->copy_area_bo = NULL;
511 accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
514 if (!accel_state->copy_area_bo)
517 radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
520 radeon_bo_unref(accel_state->copy_area_bo);
521 accel_state->copy_area_bo = NULL;
524 accel_state->copy_area = (void*)accel_state->copy_area_bo;
528 if (accel_state->vsync)
531 accel_state->dst_pix = pDst;
532 accel_state->src_pix = pSrc;
533 accel_state->xdir = xdir;
534 accel_state->ydir = ydir;
544 struct radeon_accel_state *accel_state = info->accel_state;
546 if (!accel_state->same_surface)
549 if (accel_state->copy_area)
550 accel_state->copy_area = NULL;
562 struct radeon_accel_state *accel_state = info->accel_state;
564 if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY))
568 EVERGREENDoneCopy(info->accel_state->dst_pix);
570 EVERGREENPrepareCopy(accel_state->src_pix,
571 accel_state->dst_pix,
572 accel_state->xdir,
573 accel_state->ydir,
574 accel_state->rop,
575 accel_state->planemask);
578 if (accel_state->vsync)
581 if (accel_state->same_surface &&
586 } else if (accel_state->same_surface && accel_state->copy_area) {
587 uint32_t orig_dst_domain = accel_state->dst_obj.domain;
588 uint32_t orig_src_domain = accel_state->src_obj[0].domain;
589 uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
590 uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
591 struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
592 int orig_rop = accel_state->rop;
593 struct radeon_surface *orig_dst_surface = accel_state->dst_obj.surface;
594 struct radeon_surface *orig_src_surface = accel_state->src_obj[0].surface;
597 accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
598 accel_state->dst_obj.bo = accel_state->copy_area_bo;
599 accel_state->dst_obj.tiling_flags = 0;
600 accel_state->rop = 3;
601 accel_state->dst_obj.surface = NULL;
607 accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
608 accel_state->src_obj[0].bo = accel_state->copy_area_bo;
609 accel_state->src_obj[0].tiling_flags = 0;
610 accel_state->src_obj[0].surface = NULL;
611 accel_state->dst_obj.domain = orig_dst_domain;
612 accel_state->dst_obj.bo = orig_bo;
613 accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
614 accel_state->rop = orig_rop;
615 accel_state->dst_obj.surface = orig_dst_surface;
621 accel_state->src_obj[0].domain = orig_src_domain;
622 accel_state->src_obj[0].bo = orig_bo;
623 accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
624 accel_state->src_obj[0].surface = orig_src_surface;
805 struct radeon_accel_state *accel_state = info->accel_state;
818 accel_state->is_transform[unit] = TRUE;
819 accel_state->transform[unit] = pPict->transform;
831 accel_state->is_transform[unit] = FALSE;
851 struct radeon_accel_state *accel_state = info->accel_state;
878 tex_res.pitch = accel_state->src_obj[unit].pitch;
883 tex_res.size = accel_state->src_size[unit];
885 tex_res.bo = accel_state->src_obj[unit].bo;
886 tex_res.mip_bo = accel_state->src_obj[unit].bo;
887 tex_res.surface = accel_state->src_obj[unit].surface;
890 switch (accel_state->src_obj[unit].bpp) {
958 if (!accel_state->msk_pic) {
968 if (accel_state->component_alpha) {
969 if (accel_state->src_alpha) {
996 if (accel_state->component_alpha) {
1021 if ((accel_state->src_obj[unit].tiling_flags & RADEON_TILING_MASK) ==
1024 evergreen_set_tex_resource (pScrn, &tex_res, accel_state->src_obj[unit].domain);
1154 struct radeon_accel_state *accel_state = info->accel_state;
1218 if (!accel_state->msk_pic) {
1228 if (accel_state->component_alpha) {
1229 if (accel_state->src_alpha) {
1261 if (accel_state->component_alpha) {
1291 struct radeon_accel_state *accel_state = info->accel_state;
1338 accel_state->msk_pic = pMaskPicture;
1340 accel_state->component_alpha = TRUE;
1342 accel_state->src_alpha = TRUE;
1344 accel_state->src_alpha = FALSE;
1346 accel_state->component_alpha = FALSE;
1347 accel_state->src_alpha = FALSE;
1350 accel_state->msk_pic = NULL;
1351 accel_state->component_alpha = FALSE;
1352 accel_state->src_alpha = FALSE;
1359 accel_state->comp_vs_offset, accel_state->comp_ps_offset,
1372 radeon_vbo_check(pScrn, &accel_state->vbo, 24);
1374 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
1376 radeon_vbo_check(pScrn, &accel_state->cbuf, 256);
1382 evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1383 evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1384 evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1393 accel_state->is_transform[0] = FALSE;
1402 accel_state->is_transform[1] = FALSE;
1417 vs_conf.shader_addr = accel_state->vs_mc_addr;
1418 vs_conf.shader_size = accel_state->vs_size;
1421 vs_conf.bo = accel_state->shaders_bo;
1424 ps_conf.shader_addr = accel_state->ps_mc_addr;
1425 ps_conf.shader_size = accel_state->ps_size;
1430 ps_conf.bo = accel_state->shaders_bo;
1434 cb_conf.w = accel_state->dst_obj.pitch;
1435 cb_conf.h = accel_state->dst_obj.height;
1438 cb_conf.bo = accel_state->dst_obj.bo;
1439 cb_conf.surface = accel_state->dst_obj.surface;
1474 if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
1491 evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
1501 cbuf = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
1502 vs_const_conf.bo = accel_state->cbuf.vb_bo;
1503 vs_const_conf.const_addr = accel_state->cbuf.vb_offset;
1528 radeon_vbo_commit(pScrn, &accel_state->cbuf);
1531 if (accel_state->vsync)
1534 accel_state->composite_op = op;
1535 accel_state->dst_pic = pDstPicture;
1536 accel_state->src_pic = pSrcPicture;
1537 accel_state->dst_pix = pDst;
1538 accel_state->msk_pix = pMask;
1539 accel_state->src_pix = pSrc;
1545 struct radeon_accel_state *accel_state)
1549 if (accel_state->vsync)
1551 accel_state->vline_crtc,
1552 accel_state->vline_y1,
1553 accel_state->vline_y2);
1555 vtx_size = accel_state->msk_pix ? 24 : 16;
1565 struct radeon_accel_state *accel_state = info->accel_state;
1567 EVERGREENFinishComposite(pScrn, pDst, accel_state);
1578 struct radeon_accel_state *accel_state = info->accel_state;
1582 EVERGREENFinishComposite(pScrn, pDst, info->accel_state);
1584 EVERGREENPrepareComposite(info->accel_state->composite_op,
1585 info->accel_state->src_pic,
1586 info->accel_state->msk_pic,
1587 info->accel_state->dst_pic,
1588 info->accel_state->src_pix,
1589 info->accel_state->msk_pix,
1590 info->accel_state->dst_pix);
1593 if (accel_state->vsync)
1596 if (accel_state->msk_pix) {
1598 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 24);
1621 radeon_vbo_commit(pScrn, &accel_state->vbo);
1625 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
1642 radeon_vbo_commit(pScrn, &accel_state->vbo);
1654 struct radeon_accel_state *accel_state = info->accel_state;
1722 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
1751 if (info->accel_state->vsync)
1772 struct radeon_accel_state *accel_state = info->accel_state;
1816 if (!accel_state->allowHWDFS)
1828 radeon_cs_space_add_persistent_bo(info->cs, info->accel_state->shaders_bo,
1830 accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
1831 radeon_add_pixmap(info->cs, pSrc, info->accel_state->src_obj[0].domain, 0);
1832 accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
1833 radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, accel_state->dst_obj.domain);
1861 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
1907 struct radeon_accel_state *accel_state = info->accel_state;
1909 return ++accel_state->exaSyncMarker;
1923 struct radeon_accel_state *accel_state = info->accel_state;
1928 accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
1930 if (!accel_state->shaders_bo) {
1941 struct radeon_accel_state *accel_state = info->accel_state;
1946 ret = radeon_bo_map(accel_state->shaders_bo, 1);
1951 shader = accel_state->shaders_bo->ptr;
1954 accel_state->solid_vs_offset = 0;
1955 evergreen_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4);
1958 accel_state->solid_ps_offset = 512;
1959 evergreen_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4);
1962 accel_state->copy_vs_offset = 1024;
1963 evergreen_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4);
1966 accel_state->copy_ps_offset = 1536;
1967 evergreen_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4);
1970 accel_state->comp_vs_offset = 2048;
1971 evergreen_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4);
1974 accel_state->comp_ps_offset = 2560;
1975 evergreen_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4);
1978 accel_state->xv_vs_offset = 3072;
1979 evergreen_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4);
1982 accel_state->xv_ps_offset = 3584;
1983 evergreen_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);
1985 radeon_bo_unmap(accel_state->shaders_bo);
1994 struct radeon_accel_state *accel_state = info->accel_state;
1999 ret = radeon_bo_map(accel_state->shaders_bo, 1);
2004 shader = accel_state->shaders_bo->ptr;
2007 accel_state->solid_vs_offset = 0;
2008 cayman_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4);
2011 accel_state->solid_ps_offset = 512;
2012 cayman_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4);
2015 accel_state->copy_vs_offset = 1024;
2016 cayman_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4);
2019 accel_state->copy_ps_offset = 1536;
2020 cayman_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4);
2023 accel_state->comp_vs_offset = 2048;
2024 cayman_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4);
2027 accel_state->comp_ps_offset = 2560;
2028 cayman_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4);
2031 accel_state->xv_vs_offset = 3072;
2032 cayman_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4);
2035 accel_state->xv_ps_offset = 3584;
2036 cayman_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);
2038 radeon_bo_unmap(accel_state->shaders_bo);
2049 if (!info->accel_state->exa) {
2054 info->accel_state->exa->exa_major = EXA_VERSION_MAJOR;
2055 info->accel_state->exa->exa_minor = EXA_VERSION_MINOR;
2057 info->accel_state->exa->PrepareSolid = EVERGREENPrepareSolid;
2058 info->accel_state->exa->Solid = EVERGREENSolid;
2059 info->accel_state->exa->DoneSolid = EVERGREENDoneSolid;
2061 info->accel_state->exa->PrepareCopy = EVERGREENPrepareCopy;
2062 info->accel_state->exa->Copy = EVERGREENCopy;
2063 info->accel_state->exa->DoneCopy = EVERGREENDoneCopy;
2065 info->accel_state->exa->MarkSync = EVERGREENMarkSync;
2066 info->accel_state->exa->WaitMarker = EVERGREENSync;
2068 info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
2069 info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
2070 info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;
2071 info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS;
2072 info->accel_state->exa->UploadToScreen = EVERGREENUploadToScreen;
2073 info->accel_state->exa->DownloadFromScreen = EVERGREENDownloadFromScreen;
2074 info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
2075 info->accel_state->exa->SharePixmapBacking = RADEONEXASharePixmapBacking;
2076 info->accel_state->exa->SetSharedPixmapBacking = RADEONEXASetSharedPixmapBacking;
2077 info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS | EXA_SUPPORTS_PREPARE_AUX |
2079 info->accel_state->exa->pixmapOffsetAlign = 256;
2080 info->accel_state->exa->pixmapPitchAlign = 256;
2082 info->accel_state->exa->CheckComposite = EVERGREENCheckComposite;
2083 info->accel_state->exa->PrepareComposite = EVERGREENPrepareComposite;
2084 info->accel_state->exa->Composite = EVERGREENComposite;
2085 info->accel_state->exa->DoneComposite = EVERGREENDoneComposite;
2087 info->accel_state->exa->maxPitchBytes = 32768;
2088 info->accel_state->exa->maxX = 8192;
2089 info->accel_state->exa->maxY = 8192;
2094 info->accel_state->vsync = TRUE;
2096 info->accel_state->vsync = FALSE;
2098 if (!exaDriverInit(pScreen, info->accel_state->exa)) {
2099 free(info->accel_state->exa);
2103 info->accel_state->XInited3D = FALSE;
2104 info->accel_state->copy_area = NULL;
2105 info->accel_state->src_obj[0].bo = NULL;
2106 info->accel_state->src_obj[1].bo = NULL;
2107 info->accel_state->dst_obj.bo = NULL;
2108 info->accel_state->copy_area_bo = NULL;
2109 info->accel_state->vbo.vb_start_op = -1;
2110 info->accel_state->cbuf.vb_start_op = -1;
2111 info->accel_state->finish_op = evergreen_finish_op;
2112 info->accel_state->vbo.verts_per_op = 3;
2113 info->accel_state->cbuf.verts_per_op = 1;