Lines Matching refs:dst_obj
69 struct r600_accel_object src_obj, dst_obj;
143 dst_obj.bo = radeon_get_pixmap_bo(pPixmap)->bo.radeon;
144 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
145 dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
147 dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8);
158 dst_obj.width = pPixmap->drawable.width;
159 dst_obj.height = pPixmap->drawable.height;
160 dst_obj.bpp = pPixmap->drawable.bitsPerPixel;
161 dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
166 &dst_obj,
185 evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
186 evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
187 evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
370 cb_conf.w = accel_state->dst_obj.pitch;
371 cb_conf.h = accel_state->dst_obj.height;
373 cb_conf.bo = accel_state->dst_obj.bo;
374 cb_conf.surface = accel_state->dst_obj.surface;
376 switch (accel_state->dst_obj.bpp) {
404 if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
409 evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);