Cross Reference: /xsrc/external/mit/xf86-video-ati-kms/dist/src/evergreen_textured

Lines Matching refs:accel_state
64     struct radeon_accel_state *accel_state = info->accel_state;
167 			   accel_state->xv_vs_offset, accel_state->xv_ps_offset,
179     radeon_vbo_check(pScrn, &accel_state->vbo, 16);
180     radeon_vbo_check(pScrn, &accel_state->cbuf, 512);
185     evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
186     evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
187     evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
203     vs_conf.shader_addr         = accel_state->vs_mc_addr;
204     vs_conf.shader_size         = accel_state->vs_size;
207     vs_conf.bo                  = accel_state->shaders_bo;
210     ps_conf.shader_addr         = accel_state->ps_mc_addr;
211     ps_conf.shader_size         = accel_state->ps_size;
216     ps_conf.bo                  = accel_state->shaders_bo;
223 	accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
227 	tex_res.w                   = accel_state->src_obj[0].width;
228 	tex_res.h                   = accel_state->src_obj[0].height;
229 	tex_res.pitch               = accel_state->src_obj[0].pitch;
234 	tex_res.size                = accel_state->src_size[0];
235 	tex_res.bo                  = accel_state->src_obj[0].bo;
236 	tex_res.mip_bo              = accel_state->src_obj[0].bo;
249 	if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
252 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
271 	tex_res.w                   = accel_state->src_obj[0].width >> 1;
272 	tex_res.h                   = accel_state->src_obj[0].height >> 1;
273 	tex_res.pitch               = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
283 	if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
286 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
295 	tex_res.w                   = accel_state->src_obj[0].width >> 1;
296 	tex_res.h                   = accel_state->src_obj[0].height >> 1;
297 	tex_res.pitch               = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
307 	if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
310 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
319 	accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
323 	tex_res.w                   = accel_state->src_obj[0].width;
324 	tex_res.h                   = accel_state->src_obj[0].height;
325 	tex_res.pitch               = accel_state->src_obj[0].pitch >> 1;
330 	tex_res.size                = accel_state->src_size[0];
331 	tex_res.bo                  = accel_state->src_obj[0].bo;
332 	tex_res.mip_bo              = accel_state->src_obj[0].bo;
348 	if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
351 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
370     cb_conf.w = accel_state->dst_obj.pitch;
371     cb_conf.h = accel_state->dst_obj.height;
373     cb_conf.bo = accel_state->dst_obj.bo;
374     cb_conf.surface = accel_state->dst_obj.surface;
376     switch (accel_state->dst_obj.bpp) {
404     if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
409     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
416     ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
417     ps_const_conf.bo = accel_state->cbuf.vb_bo;
418     ps_const_conf.const_addr = accel_state->cbuf.vb_offset;
436     radeon_vbo_commit(pScrn, &accel_state->cbuf);
442     vs_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
443     vs_const_conf.bo = accel_state->cbuf.vb_bo;
444     vs_const_conf.const_addr = accel_state->cbuf.vb_offset;
452     radeon_vbo_commit(pScrn, &accel_state->cbuf);
493 	vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
510 	radeon_vbo_commit(pScrn, &accel_state->vbo);
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