Lines Matching refs:accel_state
54 struct radeon_accel_state *accel_state = info->accel_state;
59 memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object));
60 accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8);
62 accel_state->src_size[0] = src0->surface->bo_size;
65 if (accel_state->src_obj[0].pitch & pitch_align)
66 RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[0].pitch));
69 memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object));
70 accel_state->src_size[0] = 0;
74 memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object));
75 accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8);
77 accel_state->src_size[1] = src1->surface->bo_size;
81 if (accel_state->src_obj[1].pitch & pitch_align)
82 RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[1].pitch));
85 memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object));
86 accel_state->src_size[1] = 0;
90 memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object));
91 accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8);
93 accel_state->dst_size = dst->surface->bo_size;
96 accel_state->dst_obj.tiling_flags = 0;
98 if (accel_state->dst_obj.pitch & pitch_align)
99 RADEON_FALLBACK(("Bad dst pitch 0x%08x\n", accel_state->dst_obj.pitch));
102 memset(&accel_state->dst_obj, 0, sizeof(struct r600_accel_object));
103 accel_state->dst_size = 0;
109 accel_state->rop = rop;
110 accel_state->planemask = planemask;
112 accel_state->vs_size = 512;
113 accel_state->ps_size = 512;
114 accel_state->vs_mc_addr = vs_offset;
115 accel_state->ps_mc_addr = ps_offset;
118 radeon_cs_space_add_persistent_bo(info->cs, accel_state->shaders_bo,
120 if (accel_state->src_obj[0].bo)
121 radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[0].bo,
122 accel_state->src_obj[0].domain, 0);
123 if (accel_state->src_obj[1].bo)
124 radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[1].bo,
125 accel_state->src_obj[1].domain, 0);
126 if (accel_state->dst_obj.bo)
127 radeon_cs_space_add_persistent_bo(info->cs, accel_state->dst_obj.bo,
128 0, accel_state->dst_obj.domain);
141 struct radeon_accel_state *accel_state = info->accel_state;
167 accel_state->solid_vs_offset, accel_state->solid_ps_offset,
175 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
180 r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
181 r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
182 r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
185 vs_conf.shader_addr = accel_state->vs_mc_addr;
186 vs_conf.shader_size = accel_state->vs_size;
189 vs_conf.bo = accel_state->shaders_bo;
192 ps_conf.shader_addr = accel_state->ps_mc_addr;
193 ps_conf.shader_size = accel_state->ps_size;
199 ps_conf.bo = accel_state->shaders_bo;
203 cb_conf.w = accel_state->dst_obj.pitch;
204 cb_conf.h = accel_state->dst_obj.height;
206 cb_conf.bo = accel_state->dst_obj.bo;
207 cb_conf.surface = accel_state->dst_obj.surface;
209 if (accel_state->dst_obj.bpp == 8) {
212 } else if (accel_state->dst_obj.bpp == 16) {
228 if (accel_state->planemask & 0x000000ff)
230 if (accel_state->planemask & 0x0000ff00)
232 if (accel_state->planemask & 0x00ff0000)
234 if (accel_state->planemask & 0xff000000)
236 cb_conf.rop = accel_state->rop;
237 if (accel_state->dst_obj.tiling_flags == 0)
239 r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
244 if (accel_state->dst_obj.bpp == 16) {
252 } else if (accel_state->dst_obj.bpp == 8) {
271 if (accel_state->vsync)
274 accel_state->dst_pix = pPix;
275 accel_state->fg = fg;
285 struct radeon_accel_state *accel_state = info->accel_state;
287 if (accel_state->vsync)
289 accel_state->vline_crtc,
290 accel_state->vline_y1,
291 accel_state->vline_y2);
301 struct radeon_accel_state *accel_state = info->accel_state;
305 R600DoneSolid(info->accel_state->dst_pix);
307 R600PrepareSolid(accel_state->dst_pix,
308 accel_state->rop,
309 accel_state->planemask,
310 accel_state->fg);
313 if (accel_state->vsync)
316 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 8);
327 radeon_vbo_commit(pScrn, &accel_state->vbo);
334 struct radeon_accel_state *accel_state = info->accel_state;
346 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
351 r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
352 r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
353 r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
356 vs_conf.shader_addr = accel_state->vs_mc_addr;
357 vs_conf.shader_size = accel_state->vs_size;
360 vs_conf.bo = accel_state->shaders_bo;
363 ps_conf.shader_addr = accel_state->ps_mc_addr;
364 ps_conf.shader_size = accel_state->ps_size;
370 ps_conf.bo = accel_state->shaders_bo;
375 tex_res.w = accel_state->src_obj[0].width;
376 tex_res.h = accel_state->src_obj[0].height;
377 tex_res.pitch = accel_state->src_obj[0].pitch;
382 tex_res.size = accel_state->src_size[0];
383 tex_res.bo = accel_state->src_obj[0].bo;
384 tex_res.mip_bo = accel_state->src_obj[0].bo;
385 tex_res.surface = accel_state->src_obj[0].surface;
386 if (accel_state->src_obj[0].bpp == 8) {
392 } else if (accel_state->src_obj[0].bpp == 16) {
410 if (accel_state->src_obj[0].tiling_flags == 0)
412 r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
426 cb_conf.w = accel_state->dst_obj.pitch;
427 cb_conf.h = accel_state->dst_obj.height;
429 cb_conf.bo = accel_state->dst_obj.bo;
430 cb_conf.surface = accel_state->dst_obj.surface;
431 if (accel_state->dst_obj.bpp == 8) {
434 } else if (accel_state->dst_obj.bpp == 16) {
445 if (accel_state->planemask & 0x000000ff)
447 if (accel_state->planemask & 0x0000ff00)
449 if (accel_state->planemask & 0x00ff0000)
451 if (accel_state->planemask & 0xff000000)
453 cb_conf.rop = accel_state->rop;
454 if (accel_state->dst_obj.tiling_flags == 0)
456 r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
473 struct radeon_accel_state *accel_state = info->accel_state;
475 if (accel_state->vsync)
477 accel_state->vline_crtc,
478 accel_state->vline_y1,
479 accel_state->vline_y2);
491 struct radeon_accel_state *accel_state = info->accel_state;
494 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
511 radeon_vbo_commit(pScrn, &accel_state->vbo);
522 struct radeon_accel_state *accel_state = info->accel_state;
535 accel_state->same_surface = FALSE;
544 accel_state->same_surface = TRUE;
563 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
567 if (accel_state->same_surface == TRUE) {
568 unsigned long size = accel_state->dst_obj.surface->bo_size;
569 unsigned long align = accel_state->dst_obj.surface->bo_alignment;
571 if (accel_state->copy_area_bo) {
572 radeon_bo_unref(accel_state->copy_area_bo);
573 accel_state->copy_area_bo = NULL;
575 accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, align,
578 if (!accel_state->copy_area_bo)
581 radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
584 radeon_bo_unref(accel_state->copy_area_bo);
585 accel_state->copy_area_bo = NULL;
588 accel_state->copy_area = (void*)accel_state->copy_area_bo;
592 if (accel_state->vsync)
595 accel_state->dst_pix = pDst;
596 accel_state->src_pix = pSrc;
597 accel_state->xdir = xdir;
598 accel_state->ydir = ydir;
608 struct radeon_accel_state *accel_state = info->accel_state;
610 if (!accel_state->same_surface)
613 if (accel_state->copy_area) {
614 accel_state->copy_area = NULL;
627 struct radeon_accel_state *accel_state = info->accel_state;
629 if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY))
633 R600DoneCopy(info->accel_state->dst_pix);
635 R600PrepareCopy(accel_state->src_pix,
636 accel_state->dst_pix,
637 accel_state->xdir,
638 accel_state->ydir,
639 accel_state->rop,
640 accel_state->planemask);
643 if (accel_state->vsync)
646 if (accel_state->same_surface &&
651 } else if (accel_state->same_surface && accel_state->copy_area) {
652 uint32_t orig_dst_domain = accel_state->dst_obj.domain;
653 uint32_t orig_src_domain = accel_state->src_obj[0].domain;
654 uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
655 uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
656 struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
657 int orig_rop = accel_state->rop;
660 accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
661 accel_state->dst_obj.bo = accel_state->copy_area_bo;
662 accel_state->dst_obj.tiling_flags = 0;
663 accel_state->rop = 3;
669 accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
670 accel_state->src_obj[0].bo = accel_state->copy_area_bo;
671 accel_state->src_obj[0].tiling_flags = 0;
672 accel_state->dst_obj.domain = orig_dst_domain;
673 accel_state->dst_obj.bo = orig_bo;
674 accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
675 accel_state->rop = orig_rop;
681 accel_state->src_obj[0].domain = orig_src_domain;
682 accel_state->src_obj[0].bo = orig_bo;
683 accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
865 struct radeon_accel_state *accel_state = info->accel_state;
892 tex_res.pitch = accel_state->src_obj[unit].pitch;
897 tex_res.size = accel_state->src_size[unit];
899 tex_res.bo = accel_state->src_obj[unit].bo;
900 tex_res.mip_bo = accel_state->src_obj[unit].bo;
901 tex_res.surface = accel_state->src_obj[unit].surface;
905 switch (accel_state->src_obj[unit].bpp) {
973 if (!accel_state->msk_pic) {
983 if (accel_state->component_alpha) {
984 if (accel_state->src_alpha) {
1011 if (accel_state->component_alpha) {
1036 if (accel_state->src_obj[unit].tiling_flags == 0)
1038 r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[unit].domain);
1084 accel_state->is_transform[unit] = TRUE;
1085 accel_state->transform[unit] = pPict->transform;
1097 accel_state->is_transform[unit] = FALSE;
1198 struct radeon_accel_state *accel_state = info->accel_state;
1262 if (!accel_state->msk_pic) {
1272 if (accel_state->component_alpha) {
1273 if (accel_state->src_alpha) {
1305 if (accel_state->component_alpha) {
1335 struct radeon_accel_state *accel_state = info->accel_state;
1381 accel_state->msk_pic = pMaskPicture;
1383 accel_state->component_alpha = TRUE;
1385 accel_state->src_alpha = TRUE;
1387 accel_state->src_alpha = FALSE;
1389 accel_state->component_alpha = FALSE;
1390 accel_state->src_alpha = FALSE;
1393 accel_state->msk_pic = NULL;
1394 accel_state->component_alpha = FALSE;
1395 accel_state->src_alpha = FALSE;
1402 accel_state->comp_vs_offset, accel_state->comp_ps_offset,
1414 radeon_vbo_check(pScrn, &accel_state->vbo, 24);
1416 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
1422 r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1423 r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1424 r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1432 accel_state->is_transform[0] = FALSE;
1440 accel_state->is_transform[1] = FALSE;
1455 vs_conf.shader_addr = accel_state->vs_mc_addr;
1456 vs_conf.shader_size = accel_state->vs_size;
1459 vs_conf.bo = accel_state->shaders_bo;
1462 ps_conf.shader_addr = accel_state->ps_mc_addr;
1463 ps_conf.shader_size = accel_state->ps_size;
1469 ps_conf.bo = accel_state->shaders_bo;
1473 cb_conf.w = accel_state->dst_obj.pitch;
1474 cb_conf.h = accel_state->dst_obj.height;
1477 cb_conf.bo = accel_state->dst_obj.bo;
1478 cb_conf.surface = accel_state->dst_obj.surface;
1513 if (accel_state->dst_obj.tiling_flags == 0)
1527 r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
1555 if (accel_state->vsync)
1558 accel_state->composite_op = op;
1559 accel_state->dst_pic = pDstPicture;
1560 accel_state->src_pic = pSrcPicture;
1561 accel_state->dst_pix = pDst;
1562 accel_state->msk_pix = pMask;
1563 accel_state->src_pix = pSrc;
1569 struct radeon_accel_state *accel_state)
1573 if (accel_state->vsync)
1575 accel_state->vline_crtc,
1576 accel_state->vline_y1,
1577 accel_state->vline_y2);
1579 vtx_size = accel_state->msk_pix ? 24 : 16;
1589 struct radeon_accel_state *accel_state = info->accel_state;
1591 R600FinishComposite(pScrn, pDst, accel_state);
1602 struct radeon_accel_state *accel_state = info->accel_state;
1609 R600FinishComposite(pScrn, pDst, info->accel_state);
1611 R600PrepareComposite(info->accel_state->composite_op,
1612 info->accel_state->src_pic,
1613 info->accel_state->msk_pic,
1614 info->accel_state->dst_pic,
1615 info->accel_state->src_pix,
1616 info->accel_state->msk_pix,
1617 info->accel_state->dst_pix);
1620 if (accel_state->vsync)
1623 if (accel_state->msk_pix) {
1625 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 24);
1648 radeon_vbo_commit(pScrn, &accel_state->vbo);
1652 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
1669 radeon_vbo_commit(pScrn, &accel_state->vbo);
1681 struct radeon_accel_state *accel_state = info->accel_state;
1752 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
1781 if (info->accel_state->vsync)
1802 struct radeon_accel_state *accel_state = info->accel_state;
1854 radeon_cs_space_add_persistent_bo(info->cs, info->accel_state->shaders_bo,
1856 accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
1857 radeon_add_pixmap(info->cs, pSrc, info->accel_state->src_obj[0].domain, 0);
1858 accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
1859 radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, accel_state->dst_obj.domain);
1887 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
1933 struct radeon_accel_state *accel_state = info->accel_state;
1935 return ++accel_state->exaSyncMarker;
1944 struct radeon_accel_state *accel_state = info->accel_state;
1946 if (accel_state->exaMarkerSynced != marker) {
1947 accel_state->exaMarkerSynced = marker;
1956 struct radeon_accel_state *accel_state = info->accel_state;
1961 accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
1963 if (!accel_state->shaders_bo) {
1974 struct radeon_accel_state *accel_state = info->accel_state;
1979 ret = radeon_bo_map(accel_state->shaders_bo, 1);
1984 shader = accel_state->shaders_bo->ptr;
1987 accel_state->solid_vs_offset = 0;
1988 R600_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4);
1991 accel_state->solid_ps_offset = 512;
1992 R600_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4);
1995 accel_state->copy_vs_offset = 1024;
1996 R600_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4);
1999 accel_state->copy_ps_offset = 1536;
2000 R600_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4);
2003 accel_state->comp_vs_offset = 2048;
2004 R600_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4);
2007 accel_state->comp_ps_offset = 2560;
2008 R600_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4);
2011 accel_state->xv_vs_offset = 3072;
2012 R600_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4);
2015 accel_state->xv_ps_offset = 3584;
2016 R600_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);
2018 radeon_bo_unmap(accel_state->shaders_bo);
2028 if (!info->accel_state->exa) {
2033 info->accel_state->exa->exa_major = EXA_VERSION_MAJOR;
2034 info->accel_state->exa->exa_minor = EXA_VERSION_MINOR;
2036 info->accel_state->exa->PrepareSolid = R600PrepareSolid;
2037 info->accel_state->exa->Solid = R600Solid;
2038 info->accel_state->exa->DoneSolid = R600DoneSolid;
2040 info->accel_state->exa->PrepareCopy = R600PrepareCopy;
2041 info->accel_state->exa->Copy = R600Copy;
2042 info->accel_state->exa->DoneCopy = R600DoneCopy;
2044 info->accel_state->exa->MarkSync = R600MarkSync;
2045 info->accel_state->exa->WaitMarker = R600Sync;
2047 info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
2048 info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
2049 info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;
2050 info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS;
2051 info->accel_state->exa->UploadToScreen = R600UploadToScreenCS;
2052 info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreenCS;
2053 info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
2054 info->accel_state->exa->SharePixmapBacking = RADEONEXASharePixmapBacking;
2055 info->accel_state->exa->SetSharedPixmapBacking = RADEONEXASetSharedPixmapBacking;
2056 info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS | EXA_SUPPORTS_PREPARE_AUX |
2058 info->accel_state->exa->pixmapOffsetAlign = 256;
2059 info->accel_state->exa->pixmapPitchAlign = 256;
2061 info->accel_state->exa->CheckComposite = R600CheckComposite;
2062 info->accel_state->exa->PrepareComposite = R600PrepareComposite;
2063 info->accel_state->exa->Composite = R600Composite;
2064 info->accel_state->exa->DoneComposite = R600DoneComposite;
2066 info->accel_state->exa->maxPitchBytes = 32768;
2067 info->accel_state->exa->maxX = 8192;
2068 info->accel_state->exa->maxY = 8192;
2073 info->accel_state->vsync = TRUE;
2075 info->accel_state->vsync = FALSE;
2077 if (!exaDriverInit(pScreen, info->accel_state->exa)) {
2078 free(info->accel_state->exa);
2082 info->accel_state->XInited3D = FALSE;
2083 info->accel_state->src_obj[0].bo = NULL;
2084 info->accel_state->src_obj[1].bo = NULL;
2085 info->accel_state->dst_obj.bo = NULL;
2086 info->accel_state->copy_area_bo = NULL;
2087 info->accel_state->vbo.vb_start_op = -1;
2088 info->accel_state->finish_op = r600_finish_op;
2089 info->accel_state->vbo.verts_per_op = 3;
Indexes created Thu Jul 23 00:25:05 UTC 2026