Cross Reference: /xsrc/external/mit/xf86-video-ati-kms/dist/src/radeon_exa

Lines Matching refs:state_2d
63     if (info->state_2d.op == 0 && op == 0)
66     has_src = info->state_2d.src_pitch_offset || info->state_2d.src_bo;
73     OUT_RING_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right);
74     OUT_RING_REG(RADEON_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl);
75     OUT_RING_REG(RADEON_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr);
76     OUT_RING_REG(RADEON_DP_BRUSH_BKGD_CLR, info->state_2d.dp_brush_bkgd_clr);
77     OUT_RING_REG(RADEON_DP_SRC_FRGD_CLR,   info->state_2d.dp_src_frgd_clr);
78     OUT_RING_REG(RADEON_DP_SRC_BKGD_CLR,   info->state_2d.dp_src_bkgd_clr);
79     OUT_RING_REG(RADEON_DP_WRITE_MASK, info->state_2d.dp_write_mask);
80     OUT_RING_REG(RADEON_DP_CNTL, info->state_2d.dp_cntl);
82     OUT_RING_REG(RADEON_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset);
83     OUT_RING_RELOC(info->state_2d.dst_bo, 0, info->state_2d.dst_domain);
86 	OUT_RING_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset);
87 	OUT_RING_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
92 	info->state_2d.op = op;
114     info->state_2d.op = 0;
150 	info->state_2d.dst_bo = driver_priv->bo->bo.radeon;
151  	info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM;
154     info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX |
156     info->state_2d.dp_brush_bkgd_clr = 0x00000000;
157     info->state_2d.dp_src_frgd_clr = 0xffffffff;
158     info->state_2d.dp_src_bkgd_clr = 0x00000000;
159     info->state_2d.dp_gui_master_cntl = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
165     info->state_2d.dp_brush_frgd_clr = fg;
166     info->state_2d.dp_cntl = (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM);
167     info->state_2d.dp_write_mask = pm;
168     info->state_2d.dst_pitch_offset = dst_pitch_offset;
169     info->state_2d.src_pitch_offset = 0;
170     info->state_2d.src_bo = NULL;
211     info->state_2d.dp_gui_master_cntl = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
219     info->state_2d.dp_cntl = ((info->accel_state->xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
221     info->state_2d.dp_brush_frgd_clr = 0xffffffff;
222     info->state_2d.dp_brush_bkgd_clr = 0x00000000;
223     info->state_2d.dp_src_frgd_clr = 0xffffffff;
224     info->state_2d.dp_src_bkgd_clr = 0x00000000;
225     info->state_2d.dp_write_mask = planemask;
226     info->state_2d.dst_pitch_offset = dst_pitch_offset;
227     info->state_2d.src_pitch_offset = src_pitch_offset;
228     info->state_2d.default_sc_bottom_right =  (RADEON_DEFAULT_SC_RIGHT_MAX
262     info->state_2d.src_bo = driver_priv->bo->bo.radeon;
265     info->state_2d.dst_bo = driver_priv->bo->bo.radeon;
266     info->state_2d.dst_domain = driver_priv->shared ? RADEON_GEM_DOMAIN_GTT : RADEON_GEM_DOMAIN_VRAM;
268 				      info->state_2d.dst_domain);