Cross Reference: /xsrc/external/mit/xf86-video-ati-kms/dist/src/radeon_exa

Lines Matching refs:accel_state
265     info->accel_state->need_src_tile_x = info->accel_state->need_src_tile_y = FALSE;
266     info->accel_state->src_tile_width = info->accel_state->src_tile_height = 65536; /* "infinite" */
279 	    info->accel_state->need_src_tile_x = (w & (w - 1)) != 0 || badPitch;
280 	    info->accel_state->need_src_tile_y = (h & (h - 1)) != 0;
282 	    if ((info->accel_state->need_src_tile_x ||
283 		 info->accel_state->need_src_tile_y) &&
288 		info->accel_state->need_src_tile_x =
289 		    info->accel_state->need_src_tile_y =
290 		    info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y;
293 	if (info->accel_state->need_src_tile_x)
294 	    info->accel_state->src_tile_width = w;
295 	if (info->accel_state->need_src_tile_y)
296 	    info->accel_state->src_tile_height = h;
368 	!(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y));
396     info->accel_state->texW[unit] = w;
397     info->accel_state->texH[unit] = h;
455 	info->accel_state->is_transform[unit] = TRUE;
456 	info->accel_state->transform[unit] = pPict->transform;
458 	info->accel_state->is_transform[unit] = FALSE;
547     info->accel_state->composite_op = op;
548     info->accel_state->dst_pic = pDstPicture;
549     info->accel_state->msk_pic = pMaskPicture;
550     info->accel_state->src_pic = pSrcPicture;
551     info->accel_state->dst_pix = pDst;
552     info->accel_state->msk_pix = pMask;
553     info->accel_state->src_pix = pSrc;
638 	info->accel_state->is_transform[1] = FALSE;
765 	!(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y));
794     info->accel_state->texW[unit] = w;
795     info->accel_state->texH[unit] = h;
852 	info->accel_state->is_transform[unit] = TRUE;
853 	info->accel_state->transform[unit] = pPict->transform;
855 	info->accel_state->is_transform[unit] = FALSE;
1000 	info->accel_state->is_transform[1] = FALSE;
1171 	if ((unit == 0) && info->accel_state->msk_pic)
1216 	if (unit != 0 || !info->accel_state->need_src_tile_x)
1221 	if (unit != 0 || !info->accel_state->need_src_tile_y)
1270 	info->accel_state->is_transform[unit] = TRUE;
1271 	info->accel_state->transform[unit] = pPict->transform;
1274 	if (info->accel_state->has_tcl) {
1275 	    info->accel_state->texW[unit] = 1;
1276 	    info->accel_state->texH[unit] = 1;
1295 	    info->accel_state->texW[unit] = w;
1296 	    info->accel_state->texH[unit] = h;
1299 	info->accel_state->is_transform[unit] = FALSE;
1302 	if (info->accel_state->has_tcl) {
1303 	    info->accel_state->texW[unit] = 1;
1304 	    info->accel_state->texH[unit] = 1;
1324 	    info->accel_state->texW[unit] = w;
1325 	    info->accel_state->texH[unit] = h;
1492 	info->accel_state->is_transform[1] = FALSE;
1496     if (info->accel_state->has_tcl) {
1557     if (info->accel_state->has_tcl) {
2102     if (info->accel_state->draw_header) {
2104 	    info->accel_state->draw_header[0] = CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD,
2105 							   info->accel_state->num_vtx *
2106 							   info->accel_state->vtx_count + 1);
2107 	    info->accel_state->draw_header[2] = (RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
2111 						 (info->accel_state->num_vtx << RADEON_CP_VC_CNTL_NUM_SHIFT));
2113 	    info->accel_state->draw_header[0] = CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
2114 							   info->accel_state->num_vtx *
2115 							   info->accel_state->vtx_count);
2116 	    info->accel_state->draw_header[1] = (RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST |
2118 						 (info->accel_state->num_vtx << RADEON_CP_VC_CNTL_NUM_SHIFT));
2120 	    info->accel_state->draw_header[0] = CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
2121 							   info->accel_state->num_vtx *
2122 							   info->accel_state->vtx_count);
2123 	    info->accel_state->draw_header[1] = (RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
2125 						 (info->accel_state->num_vtx << RADEON_CP_VC_CNTL_NUM_SHIFT));
2127 	info->accel_state->draw_header = NULL;
2146     struct radeon_accel_state *accel_state = info->accel_state;
2150     if (!accel_state->src_pic->pDrawable)
2151 	pScreen->DestroyPixmap(accel_state->src_pix);
2153     if (accel_state->msk_pic && !accel_state->msk_pic->pDrawable)
2154 	pScreen->DestroyPixmap(accel_state->msk_pix);
2204 	RadeonFinishComposite(info->accel_state->dst_pix);
2206 	info->accel_state->exa->PrepareComposite(info->accel_state->composite_op,
2207 						 info->accel_state->src_pic,
2208 						 info->accel_state->msk_pic,
2209 						 info->accel_state->dst_pic,
2210 						 info->accel_state->src_pix,
2211 						 info->accel_state->msk_pix,
2212 						 info->accel_state->dst_pix);
2224     if (info->accel_state->is_transform[0]) {
2225 	if ((info->ChipFamily < CHIP_FAMILY_R300) || !info->accel_state->has_tcl) {
2226 	    transformPoint(info->accel_state->transform[0], &srcTopLeft);
2227 	    transformPoint(info->accel_state->transform[0], &srcTopRight);
2228 	    transformPoint(info->accel_state->transform[0], &srcBottomLeft);
2229 	    transformPoint(info->accel_state->transform[0], &srcBottomRight);
2233     if (info->accel_state->msk_pic) {
2243 	if (info->accel_state->is_transform[1]) {
2244 	    if ((info->ChipFamily < CHIP_FAMILY_R300) || !info->accel_state->has_tcl) {
2245 		transformPoint(info->accel_state->transform[1], &maskTopLeft);
2246 		transformPoint(info->accel_state->transform[1], &maskTopRight);
2247 		transformPoint(info->accel_state->transform[1], &maskBottomLeft);
2248 		transformPoint(info->accel_state->transform[1], &maskBottomRight);
2256     if (info->accel_state->vsync)
2262 	if (!info->accel_state->draw_header) {
2265 	    info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
2266 	    info->accel_state->num_vtx = 0;
2267 	    info->accel_state->vtx_count = vtx_count;
2271 	    if (info->accel_state->msk_pic)
2286 	info->accel_state->num_vtx += 3;
2289 	if (!info->accel_state->draw_header) {
2292 	    info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
2293 	    info->accel_state->num_vtx = 0;
2294 	    info->accel_state->vtx_count = vtx_count;
2304 	info->accel_state->num_vtx += 4;
2307 	if (!info->accel_state->draw_header) {
2310 	    info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
2311 	    info->accel_state->num_vtx = 0;
2312 	    info->accel_state->vtx_count = vtx_count;
2322 	info->accel_state->num_vtx += 3;
2326     if (info->accel_state->msk_pic) {
2329 			 xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0],      xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0],
2330 			 xFixedToFloat(maskTopLeft.x) / info->accel_state->texW[1],     xFixedToFloat(maskTopLeft.y) / info->accel_state->texH[1]);
2333 		xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0],   xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0],
2334 		xFixedToFloat(maskBottomLeft.x) / info->accel_state->texW[1],  xFixedToFloat(maskBottomLeft.y) / info->accel_state->texH[1]);
2336 		xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0],  xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0],
2337 		xFixedToFloat(maskBottomRight.x) / info->accel_state->texW[1], xFixedToFloat(maskBottomRight.y) / info->accel_state->texH[1]);
2339 		xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0],     xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0],
2340 		xFixedToFloat(maskTopRight.x) / info->accel_state->texW[1],    xFixedToFloat(maskTopRight.y) / info->accel_state->texH[1]);
2344 		    xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0],      xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0]);
2347 		xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0],   xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0]);
2349 		xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0],  xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0]);
2351 		xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0],     xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]);
2371     if (!info->accel_state->need_src_tile_x && !info->accel_state->need_src_tile_y) {
2384     modulus(srcY, info->accel_state->src_tile_height, tileSrcY);
2392 	int h = info->accel_state->src_tile_height - tileSrcY;
2398 	modulus(srcX, info->accel_state->src_tile_width, tileSrcX);
2403 	    int w = info->accel_state->src_tile_width - tileSrcX;