Lines Matching refs:accel_state
54 struct radeon_accel_state *accel_state = info->accel_state;
56 accel_state->vline_crtc = NULL;
57 accel_state->vline_y1 = -1;
58 accel_state->vline_y2 = 0;
64 struct radeon_accel_state *accel_state = info->accel_state;
66 accel_state->vline_crtc =
68 if (accel_state->vline_y1 == -1)
69 accel_state->vline_y1 = y1;
70 if (y1 < accel_state->vline_y1)
71 accel_state->vline_y1 = y1;
72 if (y2 > accel_state->vline_y2)
73 accel_state->vline_y2 = y2;
148 struct radeon_accel_state *accel_state = info->accel_state;
153 accel_state->ib_reset_op = info->cs->cdw;
154 accel_state->vbo.vb_start_op = accel_state->vbo.vb_offset;
155 accel_state->cbuf.vb_start_op = accel_state->cbuf.vb_offset;
164 struct radeon_accel_state *accel_state = info->accel_state;
168 accel_state->finish_op(pScrn, vert_size);
169 accel_state->ib_reset_op = info->cs->cdw;
185 if (info->accel_state->ib_reset_op) {
187 info->cs->cdw = info->accel_state->ib_reset_op;
188 info->accel_state->ib_reset_op = 0;
192 info->accel_state->vbo.vb_offset = 0;
193 info->accel_state->vbo.vb_start_op = -1;
194 info->accel_state->cbuf.vb_offset = 0;
195 info->accel_state->cbuf.vb_start_op = -1;
203 info->accel_state->vbo.vb_bo,
208 if (info->accel_state->cbuf.vb_bo) {
210 info->accel_state->cbuf.vb_bo,
218 info->accel_state->XInited3D = FALSE;
219 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;