Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/atombios

Lines Matching defs:radeon_crtc
171     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
175 	atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
177 	    atombios_enable_crtc_memreq(info->atomBIOS, radeon_crtc->crtc_id, 1);
178 	atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
183 	atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
185 	    atombios_enable_crtc_memreq(info->atomBIOS, radeon_crtc->crtc_id, 0);
186 	atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
194     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
227     param.ucCRTC			= radeon_crtc->crtc_id;
245     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
278     param.ucCRTC= radeon_crtc->crtc_id;
296     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
331 	    radeon_crtc->pll_id = ATOM_PPLL_INVALID;
333 	    radeon_crtc->pll_id = ATOM_PPLL1;
335 	    radeon_crtc->pll_id = ATOM_PPLL2;
337 	radeon_crtc->pll_id = radeon_crtc->crtc_id;
339 /*    ErrorF("Picked PLL %d\n", radeon_crtc->pll_id); */
345 	    radeon_output->pll_id = radeon_crtc->pll_id;
357     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
370 	    radeon_crtc->pll_algo = RADEON_PLL_NEW;
372 	    radeon_crtc->pll_algo = RADEON_PLL_OLD;
375 	    radeon_crtc->pll_algo = RADEON_PLL_NEW;
377 	    radeon_crtc->pll_algo = RADEON_PLL_OLD;
413 		    radeon_crtc->pll_algo = RADEON_PLL_OLD;
582     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
604 	switch (radeon_crtc->pll_id) {
615 	if (radeon_crtc->crtc_id == 0) {
651 	       radeon_crtc->crtc_id, mode->Clock, (long unsigned int)sclock * 10);
654 	       radeon_crtc->crtc_id, (unsigned int)ref_div, (unsigned int)fb_div,
671 	    args.v2.ucPpll = radeon_crtc->pll_id;
672 	    args.v2.ucCRTC = radeon_crtc->crtc_id;
681 	    args.v3.ucPpll = radeon_crtc->pll_id;
682 	    args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2);
687 	    args.v5.ucCRTC = radeon_crtc->crtc_id;
693 	    args.v5.ucPpll = radeon_crtc->pll_id;
713 /*	ErrorF("Set CRTC %d PLL success\n", radeon_crtc->crtc_id); */
717     ErrorF("Set CRTC %d PLL failed\n", radeon_crtc->crtc_id);
727     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
758     switch (radeon_crtc->crtc_id) {
790     OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
792     OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
794     OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
796     OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
798     OUTREG(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
799     OUTREG(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
801     OUTREG(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
802     OUTREG(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
803     OUTREG(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
804     OUTREG(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
805     OUTREG(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, info->virtualX);
806     OUTREG(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, info->virtualY);
807     OUTREG(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,
809     OUTREG(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
811     OUTREG(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, mode->VDisplay);
814     OUTREG(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
815     OUTREG(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, (mode->HDisplay << 16) | mode->VDisplay);
818 	OUTREG(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, EVERGREEN_INTERLEAVE_EN);
820 	OUTREG(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
830     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
864     if (radeon_crtc->crtc_id == 0)
879 	if (radeon_crtc->crtc_id) {
887     OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
889     OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
891     OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
895 	OUTREG(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
898     OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
899     OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
900     OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
901     OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
902     OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, info->virtualX);
903     OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, info->virtualY);
904     OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
906     OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
908     OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, mode->VDisplay);
911     OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
912     OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
916 	OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
919 	OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
928     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
956     switch (radeon_crtc->crtc_id) {
985     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
990 	radeon_crtc->can_tile = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
1008 	if (!IS_AVIVO_VARIANT && (radeon_crtc->crtc_id == 0))
1022     radeon_crtc->initialized = TRUE;
1194 	//RADEONCrtcPrivatePtr radeon_crtc = pRADEONEnt->Controller[i];