Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/atombios

Lines Matching refs:OUTREG
607 	    OUTREG(EVERGREEN_P1PLL_SS_CNTL, temp & ~EVERGREEN_PxPLL_SS_EN);
611 	    OUTREG(EVERGREEN_P2PLL_SS_CNTL, temp & ~EVERGREEN_PxPLL_SS_EN);
617 	    OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
620 	    OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
761 	OUTREG(AVIVO_D1VGA_CONTROL, 0);
764 	OUTREG(AVIVO_D2VGA_CONTROL, 0);
767 	OUTREG(EVERGREEN_D3VGA_CONTROL, 0);
770 	OUTREG(EVERGREEN_D4VGA_CONTROL, 0);
773 	OUTREG(EVERGREEN_D5VGA_CONTROL, 0);
776 	OUTREG(EVERGREEN_D6VGA_CONTROL, 0);
790     OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
792     OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
794     OUTREG(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
796     OUTREG(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
798     OUTREG(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
799     OUTREG(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
801     OUTREG(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
802     OUTREG(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
803     OUTREG(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
804     OUTREG(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
805     OUTREG(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, info->virtualX);
806     OUTREG(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, info->virtualY);
807     OUTREG(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,
809     OUTREG(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
811     OUTREG(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, mode->VDisplay);
814     OUTREG(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
815     OUTREG(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, (mode->HDisplay << 16) | mode->VDisplay);
818 	OUTREG(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, EVERGREEN_INTERLEAVE_EN);
820 	OUTREG(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
865 	OUTREG(AVIVO_D1VGA_CONTROL, 0);
867 	OUTREG(AVIVO_D2VGA_CONTROL, 0);
880 	    OUTREG(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf);
881 	    OUTREG(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf);
883 	    OUTREG(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf);
884 	    OUTREG(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, (fb_location >> 32) & 0xf);
887     OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
889     OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
891     OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
895 	OUTREG(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
898     OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
899     OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
900     OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
901     OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
902     OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, info->virtualX);
903     OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, info->virtualY);
904     OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
906     OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
908     OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, mode->VDisplay);
911     OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
912     OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
916 	OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
919 	OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
960 	OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
961 	OUTREG(RADEON_CRTC_PITCH, crtc_pitch);
968 	OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
969 	OUTREG(RADEON_CRTC2_PITCH, crtc_pitch);
972 	OUTREG(RADEON_FP_H2_SYNC_STRT_WID,   INREG(RADEON_CRTC2_H_SYNC_STRT_WID));
973 	OUTREG(RADEON_FP_V2_SYNC_STRT_WID,   INREG(RADEON_CRTC2_V_SYNC_STRT_WID));
1117     OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split);
1128     OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split);
1143 		OUTREG(AVIVO_D1MODE_PRIORITY_A_CNT, priority_cnt);
1147 		OUTREG(AVIVO_D1MODE_PRIORITY_B_CNT, priority_cnt);
1153 		OUTREG(AVIVO_D2MODE_PRIORITY_A_CNT, priority_cnt);
1157 		OUTREG(AVIVO_D2MODE_PRIORITY_B_CNT, priority_cnt);
1273 		OUTREG(RS690_DCP_CONTROL, 0);
1276 		OUTREG(RS690_DCP_CONTROL, 2);
1291 	OUTREG(AVIVO_LB_MAX_REQ_OUTSTANDING, lb_max_req_outstanding);
1533 	    OUTREG(AVIVO_D1MODE_PRIORITY_A_CNT, priority_cnt);
1534 	    OUTREG(AVIVO_D1MODE_PRIORITY_B_CNT, priority_cnt);
1536 	    OUTREG(AVIVO_D2MODE_PRIORITY_A_CNT, priority_cnt);
1537 	    OUTREG(AVIVO_D2MODE_PRIORITY_B_CNT, priority_cnt);