Lines Matching refs:sInput
459 args.v3.sInput.usPixelClock = cpu_to_le16(adjusted_clock / 10);
460 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
461 args.v3.sInput.ucEncodeMode = atombios_get_encoder_mode(output);
462 args.v3.sInput.ucDispPllConfig = 0;
463 if (radeon_output->coherent_mode || (args.v3.sInput.ucEncodeMode == ATOM_ENCODER_MODE_DP))
464 args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_COHERENT_MODE;
466 args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_DUAL_LINK;
468 // args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE;
470 /* ErrorF("before %d 0x%x\n", args.v3.sInput.usPixelClock, args.v3.sInput.ucDispPllConfig); */