Lines Matching refs:v3
352 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
459 args.v3.sInput.usPixelClock = cpu_to_le16(adjusted_clock / 10);
460 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
461 args.v3.sInput.ucEncodeMode = atombios_get_encoder_mode(output);
462 args.v3.sInput.ucDispPllConfig = 0;
463 if (radeon_output->coherent_mode || (args.v3.sInput.ucEncodeMode == ATOM_ENCODER_MODE_DP))
464 args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_COHERENT_MODE;
466 args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_DUAL_LINK;
468 // args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE;
470 /* ErrorF("before %d 0x%x\n", args.v3.sInput.usPixelClock, args.v3.sInput.ucDispPllConfig); */
472 adjusted_clock = args.v3.sOutput.ulDispPllFreq * 10;
473 if (args.v3.sOutput.ucRefDiv) {
475 info->pll.reference_div = args.v3.sOutput.ucRefDiv;
477 if (args.v3.sOutput.ucPostDiv) {
479 info->pll.post_div = args.v3.sOutput.ucPostDiv;
481 /* ErrorF("after %d %d %d\n", args.v3.sOutput.ulDispPllFreq,
482 args.v3.sOutput.ucRefDiv, args.v3.sOutput.ucPostDiv); */
504 PIXEL_CLOCK_PARAMETERS_V3 v3;
676 args.v3.usPixelClock = cpu_to_le16(mode->Clock / 10);
677 args.v3.usRefDiv = cpu_to_le16(ref_div);
678 args.v3.usFbDiv = cpu_to_le16(fb_div);
679 args.v3.ucFracFbDiv = frac_fb_div;
680 args.v3.ucPostDiv = post_div;
681 args.v3.ucPpll = radeon_crtc->pll_id;
682 args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2);
683 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
684 args.v3.ucEncoderMode = atombios_get_encoder_mode(output);
Indexes created Thu Jul 23 00:25:05 UTC 2026