Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/evergreen

Lines Matching defs:dst_obj
107     evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
108     evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
109     evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
129     cb_conf.w = accel_state->dst_obj.pitch;
130     cb_conf.h = accel_state->dst_obj.height;
131     cb_conf.base = accel_state->dst_obj.offset;
132     cb_conf.bo = accel_state->dst_obj.bo;
133     cb_conf.surface = accel_state->dst_obj.surface;
135     if (accel_state->dst_obj.bpp == 8) {
138     } else if (accel_state->dst_obj.bpp == 16) {
163     if (accel_state->dst_obj.tiling_flags == 0) {
167     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
178     if (accel_state->dst_obj.bpp == 16) {
186     } else if (accel_state->dst_obj.bpp == 8) {
285     evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
286     evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
287     evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
358     cb_conf.w = accel_state->dst_obj.pitch;
359     cb_conf.h = accel_state->dst_obj.height;
360     cb_conf.base = accel_state->dst_obj.offset;
361     cb_conf.bo = accel_state->dst_obj.bo;
362     cb_conf.surface = accel_state->dst_obj.surface;
363     if (accel_state->dst_obj.bpp == 8) {
366     } else if (accel_state->dst_obj.bpp == 16) {
385     if (accel_state->dst_obj.tiling_flags == 0) {
389     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
456     struct r600_accel_object src_obj, dst_obj;
465     dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
471     dst_obj.offset = 0;
473     dst_obj.bo = radeon_get_pixmap_bo(pDst);
474     dst_obj.surface = radeon_get_pixmap_surface(pDst);
476     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
486     dst_obj.width = pDst->drawable.width;
487     dst_obj.height = pDst->drawable.height;
488     dst_obj.bpp = pDst->drawable.bitsPerPixel;
489     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
494 			   &dst_obj,
501 				       drmmode_get_height_align(pScrn, accel_state->dst_obj.tiling_flags));
502 	unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
504 	if (accel_state->dst_obj.surface)
505 		size = accel_state->dst_obj.surface->bo_size;
582 	uint32_t orig_dst_domain = accel_state->dst_obj.domain;
585 	uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
586 	struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
588 	struct radeon_surface *orig_dst_surface = accel_state->dst_obj.surface;
592 	accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
593 	accel_state->dst_obj.bo = accel_state->copy_area_bo;
594 	accel_state->dst_obj.offset = 0;
595 	accel_state->dst_obj.tiling_flags = 0;
597 	accel_state->dst_obj.surface = NULL;
608 	accel_state->dst_obj.domain = orig_dst_domain;
609 	accel_state->dst_obj.bo = orig_bo;
610 	accel_state->dst_obj.offset = 0;
611 	accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
613 	accel_state->dst_obj.surface = orig_dst_surface;
1141     struct r600_accel_object src_obj, mask_obj, dst_obj;
1154     dst_obj.offset = 0;
1155     dst_obj.bo = radeon_get_pixmap_bo(pDst);
1157     dst_obj.surface = radeon_get_pixmap_surface(pDst);
1159     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
1162     dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
1169     dst_obj.width = pDst->drawable.width;
1170     dst_obj.height = pDst->drawable.height;
1171     dst_obj.bpp = pDst->drawable.bitsPerPixel;
1172     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
1196 			       &dst_obj,
1216 			       &dst_obj,
1245     evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1246     evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1247     evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1290     cb_conf.w = accel_state->dst_obj.pitch;
1291     cb_conf.h = accel_state->dst_obj.height;
1292     cb_conf.base = accel_state->dst_obj.offset;
1294     cb_conf.bo = accel_state->dst_obj.bo;
1295     cb_conf.surface = accel_state->dst_obj.surface;
1328     if (accel_state->dst_obj.tiling_flags == 0) {
1333     switch (dst_obj.bpp) {
1344     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
1510     struct r600_accel_object src_obj, dst_obj;
1550     dst_obj.pitch = dst_pitch_hw;
1551     dst_obj.width = pDst->drawable.width;
1552     dst_obj.height = pDst->drawable.height;
1553     dst_obj.offset = 0;
1554     dst_obj.bpp = bpp;
1555     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
1556     dst_obj.bo = radeon_get_pixmap_bo(pDst);
1557     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
1558     dst_obj.surface = radeon_get_pixmap_surface(pDst);
1563 			   &dst_obj,
1627     struct r600_accel_object src_obj, dst_obj;
1674     accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
1675     radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, accel_state->dst_obj.domain);
1691     dst_obj.pitch = scratch_pitch;
1692     dst_obj.width = w;
1693     dst_obj.height = h;
1694     dst_obj.offset = 0;
1695     dst_obj.bo = scratch;
1696     dst_obj.bpp = bpp;
1697     dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
1698     dst_obj.tiling_flags = 0;
1699     dst_obj.surface = NULL;
1704 			   &dst_obj,
1974     info->accel_state->dst_obj.bo = NULL;