Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/evergreen

Lines Matching defs:src_obj
308     tex_res.w                   = accel_state->src_obj[0].width;
309     tex_res.h                   = accel_state->src_obj[0].height;
310     tex_res.pitch               = accel_state->src_obj[0].pitch;
313     tex_res.base                = accel_state->src_obj[0].offset;
314     tex_res.mip_base            = accel_state->src_obj[0].offset;
316     tex_res.bo                  = accel_state->src_obj[0].bo;
317     tex_res.mip_bo              = accel_state->src_obj[0].bo;
318     tex_res.surface             = accel_state->src_obj[0].surface;
319     if (accel_state->src_obj[0].bpp == 8) {
325     } else if (accel_state->src_obj[0].bpp == 16) {
342     if (accel_state->src_obj[0].tiling_flags == 0)
344     evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
456     struct r600_accel_object src_obj, dst_obj;
466     src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
470     src_obj.offset = 0;
472     src_obj.bo = radeon_get_pixmap_bo(pSrc);
475     src_obj.surface = radeon_get_pixmap_surface(pSrc);
477     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
481     src_obj.width = pSrc->drawable.width;
482     src_obj.height = pSrc->drawable.height;
483     src_obj.bpp = pSrc->drawable.bitsPerPixel;
484     src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
492 			   &src_obj,
583 	uint32_t orig_src_domain = accel_state->src_obj[0].domain;
584 	uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
589 	struct radeon_surface *orig_src_surface = accel_state->src_obj[0].surface;
603 	accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
604 	accel_state->src_obj[0].bo = accel_state->copy_area_bo;
605 	accel_state->src_obj[0].offset = 0;
606 	accel_state->src_obj[0].tiling_flags = 0;
607 	accel_state->src_obj[0].surface = NULL;
619 	accel_state->src_obj[0].domain = orig_src_domain;
620 	accel_state->src_obj[0].bo = orig_bo;
621 	accel_state->src_obj[0].offset = 0;
622 	accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
623 	accel_state->src_obj[0].surface = orig_src_surface;
864     tex_res.pitch               = accel_state->src_obj[unit].pitch;
867     tex_res.base                = accel_state->src_obj[unit].offset;
868     tex_res.mip_base            = accel_state->src_obj[unit].offset;
871     tex_res.bo                  = accel_state->src_obj[unit].bo;
872     tex_res.mip_bo              = accel_state->src_obj[unit].bo;
873     tex_res.surface             = accel_state->src_obj[unit].surface;
876     switch (accel_state->src_obj[unit].bpp) {
1005     if (accel_state->src_obj[unit].tiling_flags == 0)
1007     evergreen_set_tex_resource  (pScrn, &tex_res, accel_state->src_obj[unit].domain);
1141     struct r600_accel_object src_obj, mask_obj, dst_obj;
1153     src_obj.offset = 0;
1156     src_obj.bo = radeon_get_pixmap_bo(pSrc);
1158     src_obj.surface = radeon_get_pixmap_surface(pSrc);
1160     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
1161     src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
1164     src_obj.width = pSrc->drawable.width;
1165     src_obj.height = pSrc->drawable.height;
1166     src_obj.bpp = pSrc->drawable.bitsPerPixel;
1167     src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
1194 			       &src_obj,
1214 			       &src_obj,
1510     struct r600_accel_object src_obj, dst_obj;
1540     src_obj.pitch = scratch_pitch;
1541     src_obj.width = w;
1542     src_obj.height = h;
1543     src_obj.offset = 0;
1544     src_obj.bpp = bpp;
1545     src_obj.domain = RADEON_GEM_DOMAIN_GTT;
1546     src_obj.bo = scratch;
1547     src_obj.tiling_flags = 0;
1548     src_obj.surface = NULL;
1561 			   &src_obj,
1627     struct r600_accel_object src_obj, dst_obj;
1672     accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
1673     radeon_add_pixmap(info->cs, pSrc, info->accel_state->src_obj[0].domain, 0);
1681     src_obj.pitch = src_pitch_hw;
1682     src_obj.width = pSrc->drawable.width;
1683     src_obj.height = pSrc->drawable.height;
1684     src_obj.offset = 0;
1685     src_obj.bpp = bpp;
1686     src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
1687     src_obj.bo = radeon_get_pixmap_bo(pSrc);
1688     src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
1689     src_obj.surface = radeon_get_pixmap_surface(pSrc);
1702 			   &src_obj,
1972     info->accel_state->src_obj[0].bo = NULL;
1973     info->accel_state->src_obj[1].bo = NULL;